Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T4,T25,T43

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T4,T25,T43

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T4,T25,T43

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T25,T43
1	0	Covered	T1,T5,T6
1	1	Covered	T4,T25,T43

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T25,T43
0	1	Covered	T86,T107
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T25,T43
0	1	Covered	T4,T25,T43
1	0	Covered	T83

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T25,T43
1	-	Covered	T4,T25,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T25,T43
DetectSt	168	Covered	T4,T25,T43
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T4,T25,T43

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T25,T43
DebounceSt->IdleSt	163	Covered	T4,T44,T63
DetectSt->IdleSt	186	Covered	T86,T107
DetectSt->StableSt	191	Covered	T4,T25,T43
IdleSt->DebounceSt	148	Covered	T4,T25,T43
StableSt->IdleSt	206	Covered	T4,T25,T43

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T25,T43
0	1	Covered	T4,T25,T43
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T25,T43
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T25,T43
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T50
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T25,T43
DebounceSt	-	0	1	0	-	-	-	Covered	T4,T44,T63
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T25,T43
DetectSt	-	-	-	-	1	-	-	Covered	T86,T107
DetectSt	-	-	-	-	0	1	-	Covered	T4,T25,T43
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T4,T25,T43
StableSt	-	-	-	-	-	-	0	Covered	T4,T25,T43
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9452567	269	0	0
CntIncr_A	9452567	79613	0	0
CntNoWrap_A	9452567	8790207	0	0
DetectStDropOut_A	9452567	2	0	0
DetectedOut_A	9452567	833	0	0
DetectedPulseOut_A	9452567	118	0	0
DisabledIdleSt_A	9452567	8704494	0	0
DisabledNoDetection_A	9452567	8706870	0	0
EnterDebounceSt_A	9452567	152	0	0
EnterDetectSt_A	9452567	120	0	0
EnterStableSt_A	9452567	118	0	0
PulseIsPulse_A	9452567	118	0	0
StayInStableSt	9452567	715	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9452567	7172	0	0
gen_low_level_sva.LowLevelEvent_A	9452567	8792903	0	0
gen_not_sticky_sva.StableStDropOut_A	9452567	117	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	269	0	0
T4	24722	3	0	0
T7	15140	0	0	0
T8	1043	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T20	0	2	0	0
T25	686	4	0	0
T26	618	0	0	0
T27	5516	0	0	0
T32	0	4	0	0
T36	0	4	0	0
T43	0	2	0	0
T44	0	5	0	0
T47	523	0	0	0
T48	761	0	0	0
T55	0	5	0	0
T63	0	3	0	0
T96	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	79613	0	0
T4	24722	114	0	0
T7	15140	0	0	0
T8	1043	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T20	0	60	0	0
T25	686	74	0	0
T26	618	0	0	0
T27	5516	0	0	0
T32	0	110	0	0
T36	0	153	0	0
T43	0	43	0	0
T44	0	146	0	0
T47	523	0	0	0
T48	761	0	0	0
T55	0	224	0	0
T63	0	109	0	0
T96	0	94	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	8790207	0	0
T1	26361	25911	0	0
T2	13744	13317	0	0
T3	2057	1656	0	0
T4	24722	20700	0	0
T5	8493	8083	0	0
T6	422	21	0	0
T7	15140	14720	0	0
T13	507	106	0	0
T14	507	106	0	0
T15	501	100	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	2	0	0
T86	10968	1	0	0
T107	0	1	0	0
T108	407	0	0	0
T109	497	0	0	0
T110	527	0	0	0
T111	1193	0	0	0
T112	1320	0	0	0
T113	523	0	0	0
T114	41822	0	0	0
T115	891	0	0	0
T116	8360	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	833	0	0
T4	24722	8	0	0
T7	15140	0	0	0
T8	1043	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T20	0	9	0	0
T25	686	17	0	0
T26	618	0	0	0
T27	5516	0	0	0
T32	0	19	0	0
T36	0	17	0	0
T43	0	3	0	0
T44	0	22	0	0
T47	523	0	0	0
T48	761	0	0	0
T55	0	19	0	0
T63	0	6	0	0
T96	0	7	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	118	0	0
T4	24722	1	0	0
T7	15140	0	0	0
T8	1043	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T20	0	1	0	0
T25	686	2	0	0
T26	618	0	0	0
T27	5516	0	0	0
T32	0	2	0	0
T36	0	2	0	0
T43	0	1	0	0
T44	0	2	0	0
T47	523	0	0	0
T48	761	0	0	0
T55	0	2	0	0
T63	0	1	0	0
T96	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	8704494	0	0
T1	26361	25911	0	0
T2	13744	13317	0	0
T3	2057	1656	0	0
T4	24722	20523	0	0
T5	8493	8083	0	0
T6	422	21	0	0
T7	15140	14720	0	0
T13	507	106	0	0
T14	507	106	0	0
T15	501	100	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	8706870	0	0
T1	26361	25920	0	0
T2	13744	13321	0	0
T3	2057	1657	0	0
T4	24722	20540	0	0
T5	8493	8086	0	0
T6	422	22	0	0
T7	15140	14724	0	0
T13	507	107	0	0
T14	507	107	0	0
T15	501	101	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	152	0	0
T4	24722	2	0	0
T7	15140	0	0	0
T8	1043	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T20	0	1	0	0
T25	686	2	0	0
T26	618	0	0	0
T27	5516	0	0	0
T32	0	2	0	0
T36	0	2	0	0
T43	0	1	0	0
T44	0	3	0	0
T47	523	0	0	0
T48	761	0	0	0
T55	0	3	0	0
T63	0	2	0	0
T96	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	120	0	0
T4	24722	1	0	0
T7	15140	0	0	0
T8	1043	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T20	0	1	0	0
T25	686	2	0	0
T26	618	0	0	0
T27	5516	0	0	0
T32	0	2	0	0
T36	0	2	0	0
T43	0	1	0	0
T44	0	2	0	0
T47	523	0	0	0
T48	761	0	0	0
T55	0	2	0	0
T63	0	1	0	0
T96	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	118	0	0
T4	24722	1	0	0
T7	15140	0	0	0
T8	1043	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T20	0	1	0	0
T25	686	2	0	0
T26	618	0	0	0
T27	5516	0	0	0
T32	0	2	0	0
T36	0	2	0	0
T43	0	1	0	0
T44	0	2	0	0
T47	523	0	0	0
T48	761	0	0	0
T55	0	2	0	0
T63	0	1	0	0
T96	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	118	0	0
T4	24722	1	0	0
T7	15140	0	0	0
T8	1043	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T20	0	1	0	0
T25	686	2	0	0
T26	618	0	0	0
T27	5516	0	0	0
T32	0	2	0	0
T36	0	2	0	0
T43	0	1	0	0
T44	0	2	0	0
T47	523	0	0	0
T48	761	0	0	0
T55	0	2	0	0
T63	0	1	0	0
T96	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	715	0	0
T4	24722	7	0	0
T7	15140	0	0	0
T8	1043	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T20	0	8	0	0
T25	686	15	0	0
T26	618	0	0	0
T27	5516	0	0	0
T32	0	17	0	0
T36	0	15	0	0
T43	0	2	0	0
T44	0	20	0	0
T47	523	0	0	0
T48	761	0	0	0
T55	0	17	0	0
T63	0	5	0	0
T96	0	5	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	7172	0	0
T1	26361	11	0	0
T2	13744	12	0	0
T3	2057	9	0	0
T4	24722	17	0	0
T5	8493	12	0	0
T6	422	3	0	0
T7	15140	32	0	0
T13	507	6	0	0
T14	507	5	0	0
T15	501	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	8792903	0	0
T1	26361	25920	0	0
T2	13744	13321	0	0
T3	2057	1657	0	0
T4	24722	20721	0	0
T5	8493	8086	0	0
T6	422	22	0	0
T7	15140	14724	0	0
T13	507	107	0	0
T14	507	107	0	0
T15	501	101	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	117	0	0
T4	24722	1	0	0
T7	15140	0	0	0
T8	1043	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T20	0	1	0	0
T25	686	2	0	0
T26	618	0	0	0
T27	5516	0	0	0
T32	0	2	0	0
T36	0	2	0	0
T43	0	1	0	0
T44	0	2	0	0
T47	523	0	0	0
T48	761	0	0	0
T55	0	2	0	0
T63	0	1	0	0
T96	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T3,T19,T76

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T3,T19,T76

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T3,T19,T76

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T19,T20
1	0	Covered	T1,T5,T6
1	1	Covered	T3,T19,T76

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T19,T76
0	1	Covered	T76,T78,T79
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T19,T76
0	1	Unreachable
1	0	Covered	T3,T19,T76

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T19,T76
DetectSt	168	Covered	T3,T19,T76
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T3,T19,T76

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T19,T76
DebounceSt->IdleSt	163	Covered	T76,T78,T80
DetectSt->IdleSt	186	Covered	T76,T78,T79
DetectSt->StableSt	191	Covered	T3,T19,T76
IdleSt->DebounceSt	148	Covered	T3,T19,T76
StableSt->IdleSt	206	Covered	T3,T19,T76

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T19,T76
0	1	Covered	T3,T19,T76
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T19,T76
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T19,T76
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T83,T50
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T19,T76
DebounceSt	-	0	1	0	-	-	-	Covered	T76,T78,T80
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T19,T76
DetectSt	-	-	-	-	1	-	-	Covered	T76,T78,T79
DetectSt	-	-	-	-	0	1	-	Covered	T3,T19,T76
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T19,T76
StableSt	-	-	-	-	-	-	0	Covered	T3,T19,T76
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9452567	173	0	0
CntIncr_A	9452567	126418	0	0
CntNoWrap_A	9452567	8790303	0	0
DetectStDropOut_A	9452567	11	0	0
DetectedOut_A	9452567	593685	0	0
DetectedPulseOut_A	9452567	47	0	0
DisabledIdleSt_A	9452567	6764114	0	0
DisabledNoDetection_A	9452567	6766540	0	0
EnterDebounceSt_A	9452567	115	0	0
EnterDetectSt_A	9452567	58	0	0
EnterStableSt_A	9452567	47	0	0
PulseIsPulse_A	9452567	47	0	0
StayInStableSt	9452567	593638	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9452567	7172	0	0
gen_low_level_sva.LowLevelEvent_A	9452567	8792903	0	0
gen_sticky_sva.StableStDropOut_A	9452567	670636	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	173	0	0
T3	2057	4	0	0
T4	24722	0	0	0
T7	15140	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T19	0	4	0	0
T25	686	0	0	0
T26	618	0	0	0
T27	5516	0	0	0
T47	523	0	0	0
T48	761	0	0	0
T76	0	5	0	0
T77	0	2	0	0
T78	0	6	0	0
T79	0	4	0	0
T80	0	3	0	0
T81	0	3	0	0
T82	0	6	0	0
T120	0	3	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	126418	0	0
T3	2057	182	0	0
T4	24722	0	0	0
T7	15140	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T19	0	134	0	0
T25	686	0	0	0
T26	618	0	0	0
T27	5516	0	0	0
T47	523	0	0	0
T48	761	0	0	0
T76	0	51	0	0
T77	0	79	0	0
T78	0	208	0	0
T79	0	154	0	0
T80	0	160	0	0
T81	0	135	0	0
T82	0	192	0	0
T120	0	204	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	8790303	0	0
T1	26361	25911	0	0
T2	13744	13317	0	0
T3	2057	1652	0	0
T4	24722	20703	0	0
T5	8493	8083	0	0
T6	422	21	0	0
T7	15140	14720	0	0
T13	507	106	0	0
T14	507	106	0	0
T15	501	100	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	11	0	0
T76	747	1	0	0
T78	0	2	0	0
T79	0	1	0	0
T80	0	1	0	0
T82	0	3	0	0
T90	0	1	0	0
T96	645	0	0	0
T123	0	1	0	0
T124	0	1	0	0
T125	437	0	0	0
T126	417	0	0	0
T127	23961	0	0	0
T128	566	0	0	0
T129	22371	0	0	0
T130	16012	0	0	0
T131	440	0	0	0
T132	522	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	593685	0	0
T3	2057	1212	0	0
T4	24722	0	0	0
T7	15140	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T19	0	529	0	0
T25	686	0	0	0
T26	618	0	0	0
T27	5516	0	0	0
T47	523	0	0	0
T48	761	0	0	0
T76	0	18	0	0
T77	0	20	0	0
T79	0	79	0	0
T90	0	236	0	0
T92	0	108	0	0
T93	0	420	0	0
T121	0	1	0	0
T122	0	736	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	47	0	0
T3	2057	2	0	0
T4	24722	0	0	0
T7	15140	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T19	0	2	0	0
T25	686	0	0	0
T26	618	0	0	0
T27	5516	0	0	0
T47	523	0	0	0
T48	761	0	0	0
T76	0	1	0	0
T77	0	1	0	0
T79	0	1	0	0
T90	0	1	0	0
T92	0	1	0	0
T93	0	2	0	0
T121	0	1	0	0
T122	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	6764114	0	0
T1	26361	25911	0	0
T2	13744	13317	0	0
T3	2057	45	0	0
T4	24722	20703	0	0
T5	8493	8083	0	0
T6	422	21	0	0
T7	15140	14720	0	0
T13	507	106	0	0
T14	507	106	0	0
T15	501	100	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	6766540	0	0
T1	26361	25920	0	0
T2	13744	13321	0	0
T3	2057	46	0	0
T4	24722	20721	0	0
T5	8493	8086	0	0
T6	422	22	0	0
T7	15140	14724	0	0
T13	507	107	0	0
T14	507	107	0	0
T15	501	101	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	115	0	0
T3	2057	2	0	0
T4	24722	0	0	0
T7	15140	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T19	0	2	0	0
T25	686	0	0	0
T26	618	0	0	0
T27	5516	0	0	0
T47	523	0	0	0
T48	761	0	0	0
T76	0	3	0	0
T77	0	1	0	0
T78	0	4	0	0
T79	0	2	0	0
T80	0	2	0	0
T81	0	3	0	0
T82	0	3	0	0
T120	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	58	0	0
T3	2057	2	0	0
T4	24722	0	0	0
T7	15140	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T19	0	2	0	0
T25	686	0	0	0
T26	618	0	0	0
T27	5516	0	0	0
T47	523	0	0	0
T48	761	0	0	0
T76	0	2	0	0
T77	0	1	0	0
T78	0	2	0	0
T79	0	2	0	0
T80	0	1	0	0
T82	0	3	0	0
T90	0	2	0	0
T121	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	47	0	0
T3	2057	2	0	0
T4	24722	0	0	0
T7	15140	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T19	0	2	0	0
T25	686	0	0	0
T26	618	0	0	0
T27	5516	0	0	0
T47	523	0	0	0
T48	761	0	0	0
T76	0	1	0	0
T77	0	1	0	0
T79	0	1	0	0
T90	0	1	0	0
T92	0	1	0	0
T93	0	2	0	0
T121	0	1	0	0
T122	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	47	0	0
T3	2057	2	0	0
T4	24722	0	0	0
T7	15140	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T19	0	2	0	0
T25	686	0	0	0
T26	618	0	0	0
T27	5516	0	0	0
T47	523	0	0	0
T48	761	0	0	0
T76	0	1	0	0
T77	0	1	0	0
T79	0	1	0	0
T90	0	1	0	0
T92	0	1	0	0
T93	0	2	0	0
T121	0	1	0	0
T122	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	593638	0	0
T3	2057	1210	0	0
T4	24722	0	0	0
T7	15140	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T19	0	527	0	0
T25	686	0	0	0
T26	618	0	0	0
T27	5516	0	0	0
T47	523	0	0	0
T48	761	0	0	0
T76	0	17	0	0
T77	0	19	0	0
T79	0	78	0	0
T90	0	235	0	0
T92	0	107	0	0
T93	0	418	0	0
T122	0	734	0	0
T133	0	253	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	7172	0	0
T1	26361	11	0	0
T2	13744	12	0	0
T3	2057	9	0	0
T4	24722	17	0	0
T5	8493	12	0	0
T6	422	3	0	0
T7	15140	32	0	0
T13	507	6	0	0
T14	507	5	0	0
T15	501	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	8792903	0	0
T1	26361	25920	0	0
T2	13744	13321	0	0
T3	2057	1657	0	0
T4	24722	20721	0	0
T5	8493	8086	0	0
T6	422	22	0	0
T7	15140	14724	0	0
T13	507	107	0	0
T14	507	107	0	0
T15	501	101	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	670636	0	0
T3	2057	185	0	0
T4	24722	0	0	0
T7	15140	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T19	0	171	0	0
T25	686	0	0	0
T26	618	0	0	0
T27	5516	0	0	0
T47	523	0	0	0
T48	761	0	0	0
T76	0	114	0	0
T77	0	90099	0	0
T79	0	275	0	0
T90	0	285129	0	0
T92	0	104262	0	0
T93	0	514	0	0
T121	0	54	0	0
T122	0	568	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T6,T13,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T6,T13,T3
1	1	Covered	T6,T13,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T3,T19,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T3,T19,T20

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T3,T19,T20

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T19,T20
1	0	Covered	T6,T13,T4
1	1	Covered	T3,T19,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T19,T76
0	1	Covered	T20,T78,T93
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T19,T76
0	1	Unreachable
1	0	Covered	T3,T19,T76

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T19,T20
DetectSt	168	Covered	T3,T19,T20
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T3,T19,T76

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T19,T20
DebounceSt->IdleSt	163	Covered	T78,T93,T134
DetectSt->IdleSt	186	Covered	T20,T78,T93
DetectSt->StableSt	191	Covered	T3,T19,T76
IdleSt->DebounceSt	148	Covered	T3,T19,T20
StableSt->IdleSt	206	Covered	T3,T19,T76

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T19,T20
0	1	Covered	T3,T19,T20
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T19,T20
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T19,T20
IdleSt	0	-	-	-	-	-	-	Covered	T6,T13,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T83,T50
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T19,T20
DebounceSt	-	0	1	0	-	-	-	Covered	T78,T93,T134
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T19,T20
DetectSt	-	-	-	-	1	-	-	Covered	T20,T78,T93
DetectSt	-	-	-	-	0	1	-	Covered	T3,T19,T76
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T19,T76
StableSt	-	-	-	-	-	-	0	Covered	T3,T19,T76
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9452567	178	0	0
CntIncr_A	9452567	679483	0	0
CntNoWrap_A	9452567	8790298	0	0
DetectStDropOut_A	9452567	13	0	0
DetectedOut_A	9452567	235640	0	0
DetectedPulseOut_A	9452567	52	0	0
DisabledIdleSt_A	9452567	6764114	0	0
DisabledNoDetection_A	9452567	6766540	0	0
EnterDebounceSt_A	9452567	113	0	0
EnterDetectSt_A	9452567	65	0	0
EnterStableSt_A	9452567	52	0	0
PulseIsPulse_A	9452567	52	0	0
StayInStableSt	9452567	235588	0	0
gen_high_level_sva.HighLevelEvent_A	9452567	8792903	0	0
gen_sticky_sva.StableStDropOut_A	9452567	891714	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	178	0	0
T3	2057	4	0	0
T4	24722	0	0	0
T7	15140	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T19	0	4	0	0
T20	0	2	0	0
T25	686	0	0	0
T26	618	0	0	0
T27	5516	0	0	0
T47	523	0	0	0
T48	761	0	0	0
T76	0	2	0	0
T77	0	2	0	0
T78	0	7	0	0
T79	0	2	0	0
T80	0	2	0	0
T81	0	2	0	0
T82	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	679483	0	0
T3	2057	36	0	0
T4	24722	0	0	0
T7	15140	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T19	0	100	0	0
T20	0	34	0	0
T25	686	0	0	0
T26	618	0	0	0
T27	5516	0	0	0
T47	523	0	0	0
T48	761	0	0	0
T76	0	27	0	0
T77	0	49040	0	0
T78	0	348	0	0
T79	0	94	0	0
T80	0	81	0	0
T81	0	29	0	0
T82	0	83	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	8790298	0	0
T1	26361	25911	0	0
T2	13744	13317	0	0
T3	2057	1652	0	0
T4	24722	20703	0	0
T5	8493	8083	0	0
T6	422	21	0	0
T7	15140	14720	0	0
T13	507	106	0	0
T14	507	106	0	0
T15	501	100	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	13	0	0
T20	10877	1	0	0
T55	26860	0	0	0
T56	238519	0	0	0
T62	495	0	0	0
T63	2245	0	0	0
T64	497	0	0	0
T78	0	3	0	0
T93	0	4	0	0
T97	5122	0	0	0
T134	0	1	0	0
T135	0	4	0	0
T136	424	0	0	0
T137	522	0	0	0
T138	527	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	235640	0	0
T3	2057	224	0	0
T4	24722	0	0	0
T7	15140	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T19	0	454	0	0
T25	686	0	0	0
T26	618	0	0	0
T27	5516	0	0	0
T47	523	0	0	0
T48	761	0	0	0
T76	0	156	0	0
T77	0	41135	0	0
T79	0	453	0	0
T80	0	172	0	0
T81	0	91	0	0
T82	0	327	0	0
T90	0	507	0	0
T120	0	145	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	52	0	0
T3	2057	2	0	0
T4	24722	0	0	0
T7	15140	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T19	0	2	0	0
T25	686	0	0	0
T26	618	0	0	0
T27	5516	0	0	0
T47	523	0	0	0
T48	761	0	0	0
T76	0	1	0	0
T77	0	1	0	0
T79	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0
T90	0	2	0	0
T120	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	6764114	0	0
T1	26361	25911	0	0
T2	13744	13317	0	0
T3	2057	45	0	0
T4	24722	20703	0	0
T5	8493	8083	0	0
T6	422	21	0	0
T7	15140	14720	0	0
T13	507	106	0	0
T14	507	106	0	0
T15	501	100	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	6766540	0	0
T1	26361	25920	0	0
T2	13744	13321	0	0
T3	2057	46	0	0
T4	24722	20721	0	0
T5	8493	8086	0	0
T6	422	22	0	0
T7	15140	14724	0	0
T13	507	107	0	0
T14	507	107	0	0
T15	501	101	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	113	0	0
T3	2057	2	0	0
T4	24722	0	0	0
T7	15140	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T19	0	2	0	0
T20	0	1	0	0
T25	686	0	0	0
T26	618	0	0	0
T27	5516	0	0	0
T47	523	0	0	0
T48	761	0	0	0
T76	0	1	0	0
T77	0	1	0	0
T78	0	4	0	0
T79	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	65	0	0
T3	2057	2	0	0
T4	24722	0	0	0
T7	15140	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T19	0	2	0	0
T20	0	1	0	0
T25	686	0	0	0
T26	618	0	0	0
T27	5516	0	0	0
T47	523	0	0	0
T48	761	0	0	0
T76	0	1	0	0
T77	0	1	0	0
T78	0	3	0	0
T79	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	52	0	0
T3	2057	2	0	0
T4	24722	0	0	0
T7	15140	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T19	0	2	0	0
T25	686	0	0	0
T26	618	0	0	0
T27	5516	0	0	0
T47	523	0	0	0
T48	761	0	0	0
T76	0	1	0	0
T77	0	1	0	0
T79	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0
T90	0	2	0	0
T120	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	52	0	0
T3	2057	2	0	0
T4	24722	0	0	0
T7	15140	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T19	0	2	0	0
T25	686	0	0	0
T26	618	0	0	0
T27	5516	0	0	0
T47	523	0	0	0
T48	761	0	0	0
T76	0	1	0	0
T77	0	1	0	0
T79	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0
T90	0	2	0	0
T120	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	235588	0	0
T3	2057	222	0	0
T4	24722	0	0	0
T7	15140	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T19	0	452	0	0
T25	686	0	0	0
T26	618	0	0	0
T27	5516	0	0	0
T47	523	0	0	0
T48	761	0	0	0
T76	0	155	0	0
T77	0	41134	0	0
T79	0	452	0	0
T80	0	171	0	0
T81	0	90	0	0
T82	0	326	0	0
T90	0	505	0	0
T120	0	143	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	8792903	0	0
T1	26361	25920	0	0
T2	13744	13321	0	0
T3	2057	1657	0	0
T4	24722	20721	0	0
T5	8493	8086	0	0
T6	422	22	0	0
T7	15140	14724	0	0
T13	507	107	0	0
T14	507	107	0	0
T15	501	101	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	891714	0	0
T3	2057	1305	0	0
T4	24722	0	0	0
T7	15140	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T19	0	267	0	0
T25	686	0	0	0
T26	618	0	0	0
T27	5516	0	0	0
T47	523	0	0	0
T48	761	0	0	0
T76	0	120	0	0
T77	0	31	0	0
T79	0	78	0	0
T80	0	69	0	0
T81	0	79	0	0
T82	0	141	0	0
T90	0	285160	0	0
T120	0	372	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T3,T19,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T3,T19,T20

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T3,T19,T20

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T19,T20
1	0	Covered	T1,T5,T6
1	1	Covered	T3,T19,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T19,T20
0	1	Covered	T90,T91,T92
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T19,T20
0	1	Unreachable
1	0	Covered	T3,T19,T20

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T19,T20
DetectSt	168	Covered	T3,T19,T20
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T3,T19,T20

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T19,T20
DebounceSt->IdleSt	163	Covered	T79,T91,T94
DetectSt->IdleSt	186	Covered	T90,T91,T92
DetectSt->StableSt	191	Covered	T3,T19,T20
IdleSt->DebounceSt	148	Covered	T3,T19,T20
StableSt->IdleSt	206	Covered	T3,T19,T20

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T19,T20
0	1	Covered	T3,T19,T20
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T19,T20
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T19,T20
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T83,T50
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T19,T20
DebounceSt	-	0	1	0	-	-	-	Covered	T79,T91,T94
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T19,T20
DetectSt	-	-	-	-	1	-	-	Covered	T90,T91,T92
DetectSt	-	-	-	-	0	1	-	Covered	T3,T19,T20
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T19,T20
StableSt	-	-	-	-	-	-	0	Covered	T3,T19,T20
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9452567	183	0	0
CntIncr_A	9452567	157692	0	0
CntNoWrap_A	9452567	8790293	0	0
DetectStDropOut_A	9452567	15	0	0
DetectedOut_A	9452567	252709	0	0
DetectedPulseOut_A	9452567	51	0	0
DisabledIdleSt_A	9452567	6764114	0	0
DisabledNoDetection_A	9452567	6766540	0	0
EnterDebounceSt_A	9452567	117	0	0
EnterDetectSt_A	9452567	66	0	0
EnterStableSt_A	9452567	51	0	0
PulseIsPulse_A	9452567	51	0	0
StayInStableSt	9452567	252658	0	0
gen_high_event_sva.HighLevelEvent_A	9452567	8792903	0	0
gen_high_level_sva.HighLevelEvent_A	9452567	8792903	0	0
gen_sticky_sva.StableStDropOut_A	9452567	1165651	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	183	0	0
T3	2057	4	0	0
T4	24722	0	0	0
T7	15140	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T19	0	4	0	0
T20	0	2	0	0
T25	686	0	0	0
T26	618	0	0	0
T27	5516	0	0	0
T47	523	0	0	0
T48	761	0	0	0
T76	0	2	0	0
T77	0	2	0	0
T78	0	2	0	0
T79	0	3	0	0
T80	0	2	0	0
T81	0	2	0	0
T82	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	157692	0	0
T3	2057	182	0	0
T4	24722	0	0	0
T7	15140	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T19	0	116	0	0
T20	0	32	0	0
T25	686	0	0	0
T26	618	0	0	0
T27	5516	0	0	0
T47	523	0	0	0
T48	761	0	0	0
T76	0	67	0	0
T77	0	83	0	0
T78	0	60	0	0
T79	0	148	0	0
T80	0	80	0	0
T81	0	21	0	0
T82	0	97	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	8790293	0	0
T1	26361	25911	0	0
T2	13744	13317	0	0
T3	2057	1652	0	0
T4	24722	20703	0	0
T5	8493	8083	0	0
T6	422	21	0	0
T7	15140	14720	0	0
T13	507	106	0	0
T14	507	106	0	0
T15	501	100	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	15	0	0
T90	293831	1	0	0
T91	8238	1	0	0
T92	0	2	0	0
T124	0	2	0	0
T139	0	2	0	0
T140	0	1	0	0
T141	0	2	0	0
T142	0	2	0	0
T143	0	1	0	0
T144	0	1	0	0
T145	26891	0	0	0
T146	6729	0	0	0
T147	443	0	0	0
T148	618	0	0	0
T149	445	0	0	0
T150	402	0	0	0
T151	25993	0	0	0
T152	494	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	252709	0	0
T3	2057	998	0	0
T4	24722	0	0	0
T7	15140	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T19	0	620	0	0
T20	0	23	0	0
T25	686	0	0	0
T26	618	0	0	0
T27	5516	0	0	0
T47	523	0	0	0
T48	761	0	0	0
T76	0	204	0	0
T77	0	61	0	0
T78	0	198	0	0
T79	0	76	0	0
T80	0	207	0	0
T81	0	53	0	0
T82	0	424	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	51	0	0
T3	2057	2	0	0
T4	24722	0	0	0
T7	15140	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T19	0	2	0	0
T20	0	1	0	0
T25	686	0	0	0
T26	618	0	0	0
T27	5516	0	0	0
T47	523	0	0	0
T48	761	0	0	0
T76	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0
T79	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	6764114	0	0
T1	26361	25911	0	0
T2	13744	13317	0	0
T3	2057	45	0	0
T4	24722	20703	0	0
T5	8493	8083	0	0
T6	422	21	0	0
T7	15140	14720	0	0
T13	507	106	0	0
T14	507	106	0	0
T15	501	100	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	6766540	0	0
T1	26361	25920	0	0
T2	13744	13321	0	0
T3	2057	46	0	0
T4	24722	20721	0	0
T5	8493	8086	0	0
T6	422	22	0	0
T7	15140	14724	0	0
T13	507	107	0	0
T14	507	107	0	0
T15	501	101	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	117	0	0
T3	2057	2	0	0
T4	24722	0	0	0
T7	15140	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T19	0	2	0	0
T20	0	1	0	0
T25	686	0	0	0
T26	618	0	0	0
T27	5516	0	0	0
T47	523	0	0	0
T48	761	0	0	0
T76	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0
T79	0	2	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	66	0	0
T3	2057	2	0	0
T4	24722	0	0	0
T7	15140	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T19	0	2	0	0
T20	0	1	0	0
T25	686	0	0	0
T26	618	0	0	0
T27	5516	0	0	0
T47	523	0	0	0
T48	761	0	0	0
T76	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0
T79	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	51	0	0
T3	2057	2	0	0
T4	24722	0	0	0
T7	15140	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T19	0	2	0	0
T20	0	1	0	0
T25	686	0	0	0
T26	618	0	0	0
T27	5516	0	0	0
T47	523	0	0	0
T48	761	0	0	0
T76	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0
T79	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	51	0	0
T3	2057	2	0	0
T4	24722	0	0	0
T7	15140	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T19	0	2	0	0
T20	0	1	0	0
T25	686	0	0	0
T26	618	0	0	0
T27	5516	0	0	0
T47	523	0	0	0
T48	761	0	0	0
T76	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0
T79	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	252658	0	0
T3	2057	996	0	0
T4	24722	0	0	0
T7	15140	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T19	0	618	0	0
T20	0	22	0	0
T25	686	0	0	0
T26	618	0	0	0
T27	5516	0	0	0
T47	523	0	0	0
T48	761	0	0	0
T76	0	203	0	0
T77	0	60	0	0
T78	0	197	0	0
T79	0	75	0	0
T80	0	206	0	0
T81	0	52	0	0
T82	0	423	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	8792903	0	0
T1	26361	25920	0	0
T2	13744	13321	0	0
T3	2057	1657	0	0
T4	24722	20721	0	0
T5	8493	8086	0	0
T6	422	22	0	0
T7	15140	14724	0	0
T13	507	107	0	0
T14	507	107	0	0
T15	501	101	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	8792903	0	0
T1	26361	25920	0	0
T2	13744	13321	0	0
T3	2057	1657	0	0
T4	24722	20721	0	0
T5	8493	8086	0	0
T6	422	22	0	0
T7	15140	14724	0	0
T13	507	107	0	0
T14	507	107	0	0
T15	501	101	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	1165651	0	0
T3	2057	417	0	0
T4	24722	0	0	0
T7	15140	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T19	0	104	0	0
T20	0	69	0	0
T25	686	0	0	0
T26	618	0	0	0
T27	5516	0	0	0
T47	523	0	0	0
T48	761	0	0	0
T76	0	46	0	0
T77	0	90069	0	0
T78	0	205	0	0
T79	0	286	0	0
T80	0	43	0	0
T81	0	136	0	0
T82	0	38	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T8,T37,T32

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T8,T37,T32

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T8,T37,T32

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T37
1	0	Covered	T1,T5,T6
1	1	Covered	T8,T37,T32

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T37,T32
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T37,T32
0	1	Covered	T153,T86,T154
1	0	Covered	T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T37,T32
1	-	Covered	T153,T86,T154

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T37,T32
DetectSt	168	Covered	T8,T37,T32
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T8,T37,T32

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T37,T32
DebounceSt->IdleSt	163	Covered	T8,T83,T155
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T8,T37,T32
IdleSt->DebounceSt	148	Covered	T8,T37,T32
StableSt->IdleSt	206	Covered	T32,T153,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T37,T32
0	1	Covered	T8,T37,T32
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T37,T32
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T37,T32
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T83
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T37,T32
DebounceSt	-	0	1	0	-	-	-	Covered	T8,T155
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T37,T32
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T8,T37,T32
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T153,T86,T154
StableSt	-	-	-	-	-	-	0	Covered	T8,T37,T32
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9452567	93	0	0
CntIncr_A	9452567	40899	0	0
CntNoWrap_A	9452567	8790383	0	0
DetectStDropOut_A	9452567	0	0	0
DetectedOut_A	9452567	81527	0	0
DetectedPulseOut_A	9452567	45	0	0
DisabledIdleSt_A	9452567	8409332	0	0
DisabledNoDetection_A	9452567	8411697	0	0
EnterDebounceSt_A	9452567	48	0	0
EnterDetectSt_A	9452567	45	0	0
EnterStableSt_A	9452567	45	0	0
PulseIsPulse_A	9452567	45	0	0
StayInStableSt	9452567	81457	0	0
gen_high_level_sva.HighLevelEvent_A	9452567	8792903	0	0
gen_not_sticky_sva.StableStDropOut_A	9452567	19	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	93	0	0
T8	1043	3	0	0
T9	933	0	0	0
T10	47669	0	0	0
T21	492	0	0	0
T22	495	0	0	0
T32	0	4	0	0
T34	0	2	0	0
T37	0	2	0	0
T43	644	0	0	0
T49	752	0	0	0
T65	522	0	0	0
T66	430	0	0	0
T67	426	0	0	0
T71	0	2	0	0
T85	0	2	0	0
T86	0	4	0	0
T153	0	4	0	0
T156	0	2	0	0
T157	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	40899	0	0
T8	1043	148	0	0
T9	933	0	0	0
T10	47669	0	0	0
T21	492	0	0	0
T22	495	0	0	0
T32	0	66	0	0
T34	0	53	0	0
T37	0	55	0	0
T43	644	0	0	0
T49	752	0	0	0
T65	522	0	0	0
T66	430	0	0	0
T67	426	0	0	0
T71	0	98	0	0
T85	0	85	0	0
T86	0	169	0	0
T153	0	58	0	0
T156	0	74	0	0
T157	0	55	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	8790383	0	0
T1	26361	25911	0	0
T2	13744	13317	0	0
T3	2057	1656	0	0
T4	24722	20703	0	0
T5	8493	8083	0	0
T6	422	21	0	0
T7	15140	14720	0	0
T13	507	106	0	0
T14	507	106	0	0
T15	501	100	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	81527	0	0
T8	1043	186	0	0
T9	933	0	0	0
T10	47669	0	0	0
T21	492	0	0	0
T22	495	0	0	0
T32	0	164	0	0
T34	0	40	0	0
T37	0	38	0	0
T43	644	0	0	0
T49	752	0	0	0
T65	522	0	0	0
T66	430	0	0	0
T67	426	0	0	0
T71	0	42	0	0
T85	0	345	0	0
T86	0	200	0	0
T153	0	86	0	0
T156	0	42	0	0
T157	0	42	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	45	0	0
T8	1043	1	0	0
T9	933	0	0	0
T10	47669	0	0	0
T21	492	0	0	0
T22	495	0	0	0
T32	0	2	0	0
T34	0	1	0	0
T37	0	1	0	0
T43	644	0	0	0
T49	752	0	0	0
T65	522	0	0	0
T66	430	0	0	0
T67	426	0	0	0
T71	0	1	0	0
T85	0	1	0	0
T86	0	2	0	0
T153	0	2	0	0
T156	0	1	0	0
T157	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	8409332	0	0
T1	26361	25911	0	0
T2	13744	13317	0	0
T3	2057	1656	0	0
T4	24722	20703	0	0
T5	8493	8083	0	0
T6	422	21	0	0
T7	15140	14720	0	0
T13	507	106	0	0
T14	507	106	0	0
T15	501	100	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	8411697	0	0
T1	26361	25920	0	0
T2	13744	13321	0	0
T3	2057	1657	0	0
T4	24722	20721	0	0
T5	8493	8086	0	0
T6	422	22	0	0
T7	15140	14724	0	0
T13	507	107	0	0
T14	507	107	0	0
T15	501	101	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	48	0	0
T8	1043	2	0	0
T9	933	0	0	0
T10	47669	0	0	0
T21	492	0	0	0
T22	495	0	0	0
T32	0	2	0	0
T34	0	1	0	0
T37	0	1	0	0
T43	644	0	0	0
T49	752	0	0	0
T65	522	0	0	0
T66	430	0	0	0
T67	426	0	0	0
T71	0	1	0	0
T85	0	1	0	0
T86	0	2	0	0
T153	0	2	0	0
T156	0	1	0	0
T157	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	45	0	0
T8	1043	1	0	0
T9	933	0	0	0
T10	47669	0	0	0
T21	492	0	0	0
T22	495	0	0	0
T32	0	2	0	0
T34	0	1	0	0
T37	0	1	0	0
T43	644	0	0	0
T49	752	0	0	0
T65	522	0	0	0
T66	430	0	0	0
T67	426	0	0	0
T71	0	1	0	0
T85	0	1	0	0
T86	0	2	0	0
T153	0	2	0	0
T156	0	1	0	0
T157	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	45	0	0
T8	1043	1	0	0
T9	933	0	0	0
T10	47669	0	0	0
T21	492	0	0	0
T22	495	0	0	0
T32	0	2	0	0
T34	0	1	0	0
T37	0	1	0	0
T43	644	0	0	0
T49	752	0	0	0
T65	522	0	0	0
T66	430	0	0	0
T67	426	0	0	0
T71	0	1	0	0
T85	0	1	0	0
T86	0	2	0	0
T153	0	2	0	0
T156	0	1	0	0
T157	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	45	0	0
T8	1043	1	0	0
T9	933	0	0	0
T10	47669	0	0	0
T21	492	0	0	0
T22	495	0	0	0
T32	0	2	0	0
T34	0	1	0	0
T37	0	1	0	0
T43	644	0	0	0
T49	752	0	0	0
T65	522	0	0	0
T66	430	0	0	0
T67	426	0	0	0
T71	0	1	0	0
T85	0	1	0	0
T86	0	2	0	0
T153	0	2	0	0
T156	0	1	0	0
T157	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	81457	0	0
T8	1043	184	0	0
T9	933	0	0	0
T10	47669	0	0	0
T21	492	0	0	0
T22	495	0	0	0
T32	0	160	0	0
T34	0	38	0	0
T37	0	36	0	0
T43	644	0	0	0
T49	752	0	0	0
T65	522	0	0	0
T66	430	0	0	0
T67	426	0	0	0
T71	0	40	0	0
T85	0	343	0	0
T86	0	197	0	0
T153	0	83	0	0
T156	0	40	0	0
T157	0	40	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	8792903	0	0
T1	26361	25920	0	0
T2	13744	13321	0	0
T3	2057	1657	0	0
T4	24722	20721	0	0
T5	8493	8086	0	0
T6	422	22	0	0
T7	15140	14724	0	0
T13	507	107	0	0
T14	507	107	0	0
T15	501	101	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	19	0	0
T57	4993	0	0	0
T76	747	0	0	0
T86	0	1	0	0
T96	645	0	0	0
T98	6463	0	0	0
T125	437	0	0	0
T133	0	2	0	0
T148	0	1	0	0
T153	592	1	0	0
T154	0	3	0	0
T158	0	1	0	0
T159	0	1	0	0
T160	0	1	0	0
T161	0	1	0	0
T162	0	1	0	0
T163	431	0	0	0
T164	493	0	0	0
T165	4402	0	0	0
T166	497	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T8,T24,T37

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T8,T24,T37

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T8,T24,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T24
1	0	Covered	T1,T5,T6
1	1	Covered	T8,T24,T37

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T24,T37
0	1	Covered	T160,T167,T168
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T24,T37
0	1	Covered	T8,T24,T37
1	0	Covered	T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T24,T37
1	-	Covered	T8,T24,T37

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T24,T37
DetectSt	168	Covered	T8,T24,T37
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T8,T24,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T24,T37
DebounceSt->IdleSt	163	Covered	T32,T169,T158
DetectSt->IdleSt	186	Covered	T160,T167,T168
DetectSt->StableSt	191	Covered	T8,T24,T37
IdleSt->DebounceSt	148	Covered	T8,T24,T37
StableSt->IdleSt	206	Covered	T8,T24,T37

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T24,T37
0	1	Covered	T8,T24,T37
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T24,T37
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T24,T37
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T83
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T24,T37
DebounceSt	-	0	1	0	-	-	-	Covered	T32,T169,T158
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T24,T37
DetectSt	-	-	-	-	1	-	-	Covered	T160,T167,T168
DetectSt	-	-	-	-	0	1	-	Covered	T8,T24,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T24,T37
StableSt	-	-	-	-	-	-	0	Covered	T8,T24,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9452567	135	0	0
CntIncr_A	9452567	44528	0	0
CntNoWrap_A	9452567	8790341	0	0
DetectStDropOut_A	9452567	3	0	0
DetectedOut_A	9452567	5827	0	0
DetectedPulseOut_A	9452567	61	0	0
DisabledIdleSt_A	9452567	8524582	0	0
DisabledNoDetection_A	9452567	8526958	0	0
EnterDebounceSt_A	9452567	71	0	0
EnterDetectSt_A	9452567	64	0	0
EnterStableSt_A	9452567	61	0	0
PulseIsPulse_A	9452567	61	0	0
StayInStableSt	9452567	5742	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9452567	2734	0	0
gen_low_level_sva.LowLevelEvent_A	9452567	8792903	0	0
gen_not_sticky_sva.StableStDropOut_A	9452567	36	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	135	0	0
T8	1043	4	0	0
T9	933	0	0	0
T10	47669	0	0	0
T21	492	0	0	0
T22	495	0	0	0
T24	0	4	0	0
T32	0	3	0	0
T34	0	2	0	0
T35	0	2	0	0
T37	0	2	0	0
T38	0	2	0	0
T43	644	0	0	0
T49	752	0	0	0
T65	522	0	0	0
T66	430	0	0	0
T67	426	0	0	0
T71	0	2	0	0
T72	0	4	0	0
T85	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	44528	0	0
T8	1043	148	0	0
T9	933	0	0	0
T10	47669	0	0	0
T21	492	0	0	0
T22	495	0	0	0
T24	0	118	0	0
T32	0	61	0	0
T34	0	53	0	0
T35	0	90	0	0
T37	0	55	0	0
T38	0	21	0	0
T43	644	0	0	0
T49	752	0	0	0
T65	522	0	0	0
T66	430	0	0	0
T67	426	0	0	0
T71	0	98	0	0
T72	0	76	0	0
T85	0	85	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	8790341	0	0
T1	26361	25911	0	0
T2	13744	13317	0	0
T3	2057	1656	0	0
T4	24722	20703	0	0
T5	8493	8083	0	0
T6	422	21	0	0
T7	15140	14720	0	0
T13	507	106	0	0
T14	507	106	0	0
T15	501	100	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	3	0	0
T88	18738	0	0	0
T160	623	1	0	0
T167	0	1	0	0
T168	0	1	0	0
T170	497	0	0	0
T171	12846	0	0	0
T172	522	0	0	0
T173	777	0	0	0
T174	647	0	0	0
T175	4917	0	0	0
T176	404	0	0	0
T177	522	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	5827	0	0
T8	1043	219	0	0
T9	933	0	0	0
T10	47669	0	0	0
T21	492	0	0	0
T22	495	0	0	0
T24	0	202	0	0
T32	0	91	0	0
T34	0	160	0	0
T35	0	197	0	0
T37	0	203	0	0
T38	0	75	0	0
T43	644	0	0	0
T49	752	0	0	0
T65	522	0	0	0
T66	430	0	0	0
T67	426	0	0	0
T71	0	69	0	0
T72	0	125	0	0
T85	0	156	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	61	0	0
T8	1043	2	0	0
T9	933	0	0	0
T10	47669	0	0	0
T21	492	0	0	0
T22	495	0	0	0
T24	0	2	0	0
T32	0	1	0	0
T34	0	1	0	0
T35	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T43	644	0	0	0
T49	752	0	0	0
T65	522	0	0	0
T66	430	0	0	0
T67	426	0	0	0
T71	0	1	0	0
T72	0	2	0	0
T85	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	8524582	0	0
T1	26361	25911	0	0
T2	13744	13317	0	0
T3	2057	1656	0	0
T4	24722	20703	0	0
T5	8493	8083	0	0
T6	422	21	0	0
T7	15140	14720	0	0
T13	507	106	0	0
T14	507	106	0	0
T15	501	100	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	8526958	0	0
T1	26361	25920	0	0
T2	13744	13321	0	0
T3	2057	1657	0	0
T4	24722	20721	0	0
T5	8493	8086	0	0
T6	422	22	0	0
T7	15140	14724	0	0
T13	507	107	0	0
T14	507	107	0	0
T15	501	101	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	71	0	0
T8	1043	2	0	0
T9	933	0	0	0
T10	47669	0	0	0
T21	492	0	0	0
T22	495	0	0	0
T24	0	2	0	0
T32	0	2	0	0
T34	0	1	0	0
T35	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T43	644	0	0	0
T49	752	0	0	0
T65	522	0	0	0
T66	430	0	0	0
T67	426	0	0	0
T71	0	1	0	0
T72	0	2	0	0
T85	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	64	0	0
T8	1043	2	0	0
T9	933	0	0	0
T10	47669	0	0	0
T21	492	0	0	0
T22	495	0	0	0
T24	0	2	0	0
T32	0	1	0	0
T34	0	1	0	0
T35	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T43	644	0	0	0
T49	752	0	0	0
T65	522	0	0	0
T66	430	0	0	0
T67	426	0	0	0
T71	0	1	0	0
T72	0	2	0	0
T85	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	61	0	0
T8	1043	2	0	0
T9	933	0	0	0
T10	47669	0	0	0
T21	492	0	0	0
T22	495	0	0	0
T24	0	2	0	0
T32	0	1	0	0
T34	0	1	0	0
T35	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T43	644	0	0	0
T49	752	0	0	0
T65	522	0	0	0
T66	430	0	0	0
T67	426	0	0	0
T71	0	1	0	0
T72	0	2	0	0
T85	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	61	0	0
T8	1043	2	0	0
T9	933	0	0	0
T10	47669	0	0	0
T21	492	0	0	0
T22	495	0	0	0
T24	0	2	0	0
T32	0	1	0	0
T34	0	1	0	0
T35	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T43	644	0	0	0
T49	752	0	0	0
T65	522	0	0	0
T66	430	0	0	0
T67	426	0	0	0
T71	0	1	0	0
T72	0	2	0	0
T85	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	5742	0	0
T8	1043	217	0	0
T9	933	0	0	0
T10	47669	0	0	0
T21	492	0	0	0
T22	495	0	0	0
T24	0	199	0	0
T32	0	90	0	0
T34	0	159	0	0
T35	0	195	0	0
T37	0	202	0	0
T38	0	74	0	0
T43	644	0	0	0
T49	752	0	0	0
T65	522	0	0	0
T66	430	0	0	0
T67	426	0	0	0
T71	0	68	0	0
T72	0	122	0	0
T85	0	155	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	2734	0	0
T2	13744	0	0	0
T3	2057	0	0	0
T4	24722	8	0	0
T6	422	2	0	0
T7	15140	0	0	0
T8	0	2	0	0
T13	507	4	0	0
T14	507	6	0	0
T15	501	7	0	0
T21	0	5	0	0
T22	0	4	0	0
T27	5516	0	0	0
T47	523	6	0	0
T65	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	8792903	0	0
T1	26361	25920	0	0
T2	13744	13321	0	0
T3	2057	1657	0	0
T4	24722	20721	0	0
T5	8493	8086	0	0
T6	422	22	0	0
T7	15140	14724	0	0
T13	507	107	0	0
T14	507	107	0	0
T15	501	101	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	36	0	0
T8	1043	2	0	0
T9	933	0	0	0
T10	47669	0	0	0
T21	492	0	0	0
T22	495	0	0	0
T24	0	1	0	0
T32	0	1	0	0
T34	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T43	644	0	0	0
T49	752	0	0	0
T65	522	0	0	0
T66	430	0	0	0
T67	426	0	0	0
T71	0	1	0	0
T72	0	1	0	0
T85	0	1	0	0
T157	0	1	0	0