Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T8,T9,T37

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T8,T9,T37

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T8,T9,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T37
1	0	Covered	T1,T5,T6
1	1	Covered	T8,T9,T37

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T36
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T36
0	1	Covered	T8,T9,T36
1	0	Covered	T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T9,T36
1	-	Covered	T8,T9,T36

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T9,T37
DetectSt	168	Covered	T8,T9,T36
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T8,T9,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T9,T36
DebounceSt->IdleSt	163	Covered	T37,T178,T83
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T8,T9,T36
IdleSt->DebounceSt	148	Covered	T8,T9,T37
StableSt->IdleSt	206	Covered	T8,T9,T36

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T9,T37
0	1	Covered	T8,T9,T37
0	0	Excluded	T1,T5,T6	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T36
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T9,T37
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T83
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T9,T36
DebounceSt	-	0	1	0	-	-	-	Covered	T37,T178
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T9,T37
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T8,T9,T36
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T9,T36
StableSt	-	-	-	-	-	-	0	Covered	T8,T9,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9452567	83	0	0
CntIncr_A	9452567	40595	0	0
CntNoWrap_A	9452567	8790393	0	0
DetectStDropOut_A	9452567	0	0	0
DetectedOut_A	9452567	41412	0	0
DetectedPulseOut_A	9452567	40	0	0
DisabledIdleSt_A	9452567	8536820	0	0
DisabledNoDetection_A	9452567	8539194	0	0
EnterDebounceSt_A	9452567	43	0	0
EnterDetectSt_A	9452567	40	0	0
EnterStableSt_A	9452567	40	0	0
PulseIsPulse_A	9452567	40	0	0
StayInStableSt	9452567	41354	0	0
gen_high_level_sva.HighLevelEvent_A	9452567	8792903	0	0
gen_not_sticky_sva.StableStDropOut_A	9452567	21	0	0

CntClr_A

Name	Attempts	Real Successes
Total	9452567	83
T8	1043	2
T9	933	2
T10	47669	0
T21	492	0
T22	495	0
T32	0	6
T34	0	2
T36	0	4
T37	0	1
T38	0	2
T43	644	0
T49	752	0
T65	522	0
T66	430	0
T67	426	0
T71	0	2
T87	0	6
T154	0	6

CntIncr_A

Name	Attempts	Real Successes
Total	9452567	40595
T8	1043	74
T9	933	94
T10	47669	0
T21	492	0
T22	495	0
T32	0	69
T34	0	53
T36	0	72
T37	0	55
T38	0	21
T43	644	0
T49	752	0
T65	522	0
T66	430	0
T67	426	0
T71	0	98
T87	0	126
T154	0	204

CntNoWrap_A

Name	Attempts	Real Successes
Total	9452567	8790393
T1	26361	25911
T2	13744	13317
T3	2057	1656
T4	24722	20703
T5	8493	8083
T6	422	21
T7	15140	14720
T13	507	106
T14	507	106
T15	501	100

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	0	0	0

DetectedOut_A

Name	Attempts	Real Successes
Total	9452567	41412
T8	1043	45
T9	933	40
T10	47669	0
T21	492	0
T22	495	0
T32	0	137
T34	0	44
T36	0	94
T38	0	39
T43	644	0
T49	752	0
T65	522	0
T66	430	0
T67	426	0
T71	0	42
T87	0	125
T90	0	98
T154	0	131

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	9452567	40
T8	1043	1
T9	933	1
T10	47669	0
T21	492	0
T22	495	0
T32	0	3
T34	0	1
T36	0	2
T38	0	1
T43	644	0
T49	752	0
T65	522	0
T66	430	0
T67	426	0
T71	0	1
T87	0	3
T90	0	2
T154	0	3

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	9452567	8536820
T1	26361	25911
T2	13744	13317
T3	2057	1656
T4	24722	20703
T5	8493	8083
T6	422	21
T7	15140	14720
T13	507	106
T14	507	106
T15	501	100

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	9452567	8539194
T1	26361	25920
T2	13744	13321
T3	2057	1657
T4	24722	20721
T5	8493	8086
T6	422	22
T7	15140	14724
T13	507	107
T14	507	107
T15	501	101

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	9452567	43
T8	1043	1
T9	933	1
T10	47669	0
T21	492	0
T22	495	0
T32	0	3
T34	0	1
T36	0	2
T37	0	1
T38	0	1
T43	644	0
T49	752	0
T65	522	0
T66	430	0
T67	426	0
T71	0	1
T87	0	3
T154	0	3

EnterDetectSt_A

Name	Attempts	Real Successes
Total	9452567	40
T8	1043	1
T9	933	1
T10	47669	0
T21	492	0
T22	495	0
T32	0	3
T34	0	1
T36	0	2
T38	0	1
T43	644	0
T49	752	0
T65	522	0
T66	430	0
T67	426	0
T71	0	1
T87	0	3
T90	0	2
T154	0	3

EnterStableSt_A

Name	Attempts	Real Successes
Total	9452567	40
T8	1043	1
T9	933	1
T10	47669	0
T21	492	0
T22	495	0
T32	0	3
T34	0	1
T36	0	2
T38	0	1
T43	644	0
T49	752	0
T65	522	0
T66	430	0
T67	426	0
T71	0	1
T87	0	3
T90	0	2
T154	0	3

PulseIsPulse_A

Name	Attempts	Real Successes
Total	9452567	40
T8	1043	1
T9	933	1
T10	47669	0
T21	492	0
T22	495	0
T32	0	3
T34	0	1
T36	0	2
T38	0	1
T43	644	0
T49	752	0
T65	522	0
T66	430	0
T67	426	0
T71	0	1
T87	0	3
T90	0	2
T154	0	3

StayInStableSt

Name	Attempts	Real Successes
Total	9452567	41354
T8	1043	44
T9	933	39
T10	47669	0
T21	492	0
T22	495	0
T32	0	133
T34	0	43
T36	0	91
T38	0	37
T43	644	0
T49	752	0
T65	522	0
T66	430	0
T67	426	0
T71	0	40
T87	0	121
T90	0	95
T154	0	127

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes
Total	9452567	8792903
T1	26361	25920
T2	13744	13321
T3	2057	1657
T4	24722	20721
T5	8493	8086
T6	422	22
T7	15140	14724
T13	507	107
T14	507	107
T15	501	101

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	9452567	21
T8	1043	1
T9	933	1
T10	47669	0
T21	492	0
T22	495	0
T32	0	2
T34	0	1
T36	0	1
T43	644	0
T49	752	0
T65	522	0
T66	430	0
T67	426	0
T87	0	2
T90	0	1
T91	0	1
T154	0	2
T179	0	1

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T8,T9,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T8,T9,T24

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T8,T9,T24

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T24
1	0	Covered	T1,T5,T6
1	1	Covered	T8,T9,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T24
0	1	Covered	T154,T133,T180
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T24
0	1	Covered	T8,T24,T36
1	0	Covered	T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T9,T24
1	-	Covered	T8,T24,T36

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T9,T24
DetectSt	168	Covered	T8,T9,T24
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T8,T9,T24

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T9,T24
DebounceSt->IdleSt	163	Covered	T9,T36,T35
DetectSt->IdleSt	186	Covered	T154,T133,T180
DetectSt->StableSt	191	Covered	T8,T9,T24
IdleSt->DebounceSt	148	Covered	T8,T9,T24
StableSt->IdleSt	206	Covered	T8,T24,T36

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T9,T24
0	1	Covered	T8,T9,T24
0	0	Excluded	T1,T5,T6	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T24
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T9,T24
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T83
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T9,T24
DebounceSt	-	0	1	0	-	-	-	Covered	T9,T36,T35
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T9,T24
DetectSt	-	-	-	-	1	-	-	Covered	T154,T133,T180
DetectSt	-	-	-	-	0	1	-	Covered	T8,T9,T24
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T24,T36
StableSt	-	-	-	-	-	-	0	Covered	T8,T9,T24
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9452567	135	0	0
CntIncr_A	9452567	80428	0	0
CntNoWrap_A	9452567	8790341	0	0
DetectStDropOut_A	9452567	3	0	0
DetectedOut_A	9452567	87147	0	0
DetectedPulseOut_A	9452567	61	0	0
DisabledIdleSt_A	9452567	8537232	0	0
DisabledNoDetection_A	9452567	8539609	0	0
EnterDebounceSt_A	9452567	71	0	0
EnterDetectSt_A	9452567	64	0	0
EnterStableSt_A	9452567	61	0	0
PulseIsPulse_A	9452567	61	0	0
StayInStableSt	9452567	87058	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9452567	3122	0	0
gen_low_level_sva.LowLevelEvent_A	9452567	8792903	0	0
gen_not_sticky_sva.StableStDropOut_A	9452567	32	0	0

CntClr_A

Name	Attempts	Real Successes
Total	9452567	135
T8	1043	4
T9	933	3
T10	47669	0
T20	0	2
T21	492	0
T22	495	0
T24	0	2
T32	0	4
T35	0	3
T36	0	3
T43	644	0
T49	752	0
T65	522	0
T66	430	0
T67	426	0
T85	0	2
T156	0	2
T181	0	2

CntIncr_A

Name	Attempts	Real Successes
Total	9452567	80428
T8	1043	148
T9	933	188
T10	47669	0
T20	0	32
T21	492	0
T22	495	0
T24	0	59
T32	0	51
T35	0	180
T36	0	72
T43	644	0
T49	752	0
T65	522	0
T66	430	0
T67	426	0
T85	0	85
T156	0	74
T181	0	68

CntNoWrap_A

Name	Attempts	Real Successes
Total	9452567	8790341
T1	26361	25911
T2	13744	13317
T3	2057	1656
T4	24722	20703
T5	8493	8083
T6	422	21
T7	15140	14720
T13	507	106
T14	507	106
T15	501	100

DetectStDropOut_A

Name	Attempts	Real Successes
Total	9452567	3
T133	0	1
T154	13854	1
T180	0	1
T182	503	0
T183	492	0
T184	493	0
T185	425	0
T186	407	0
T187	502	0
T188	528	0
T189	404	0
T190	12544	0

DetectedOut_A

Name	Attempts	Real Successes
Total	9452567	87147
T8	1043	365
T9	933	200
T10	47669	0
T20	0	73
T21	492	0
T22	495	0
T24	0	41
T32	0	85
T35	0	197
T36	0	2
T43	644	0
T49	752	0
T65	522	0
T66	430	0
T67	426	0
T85	0	475
T156	0	41
T181	0	75

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	9452567	61
T8	1043	2
T9	933	1
T10	47669	0
T20	0	1
T21	492	0
T22	495	0
T24	0	1
T32	0	2
T35	0	1
T36	0	1
T43	644	0
T49	752	0
T65	522	0
T66	430	0
T67	426	0
T85	0	1
T156	0	1
T181	0	1

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	9452567	8537232
T1	26361	25911
T2	13744	13317
T3	2057	1656
T4	24722	20703
T5	8493	8083
T6	422	21
T7	15140	14720
T13	507	106
T14	507	106
T15	501	100

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	9452567	8539609
T1	26361	25920
T2	13744	13321
T3	2057	1657
T4	24722	20721
T5	8493	8086
T6	422	22
T7	15140	14724
T13	507	107
T14	507	107
T15	501	101

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	9452567	71
T8	1043	2
T9	933	2
T10	47669	0
T20	0	1
T21	492	0
T22	495	0
T24	0	1
T32	0	2
T35	0	2
T36	0	2
T43	644	0
T49	752	0
T65	522	0
T66	430	0
T67	426	0
T85	0	1
T156	0	1
T181	0	1

EnterDetectSt_A

Name	Attempts	Real Successes
Total	9452567	64
T8	1043	2
T9	933	1
T10	47669	0
T20	0	1
T21	492	0
T22	495	0
T24	0	1
T32	0	2
T35	0	1
T36	0	1
T43	644	0
T49	752	0
T65	522	0
T66	430	0
T67	426	0
T85	0	1
T156	0	1
T181	0	1

EnterStableSt_A

Name	Attempts	Real Successes
Total	9452567	61
T8	1043	2
T9	933	1
T10	47669	0
T20	0	1
T21	492	0
T22	495	0
T24	0	1
T32	0	2
T35	0	1
T36	0	1
T43	644	0
T49	752	0
T65	522	0
T66	430	0
T67	426	0
T85	0	1
T156	0	1
T181	0	1

PulseIsPulse_A

Name	Attempts	Real Successes
Total	9452567	61
T8	1043	2
T9	933	1
T10	47669	0
T20	0	1
T21	492	0
T22	495	0
T24	0	1
T32	0	2
T35	0	1
T36	0	1
T43	644	0
T49	752	0
T65	522	0
T66	430	0
T67	426	0
T85	0	1
T156	0	1
T181	0	1

StayInStableSt

Name	Attempts	Real Successes
Total	9452567	87058
T8	1043	362
T9	933	198
T10	47669	0
T20	0	71
T21	492	0
T22	495	0
T24	0	40
T32	0	83
T35	0	195
T36	0	1
T43	644	0
T49	752	0
T65	522	0
T66	430	0
T67	426	0
T85	0	473
T156	0	39
T181	0	73

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes
Total	9452567	3122
T2	13744	0
T3	2057	0
T4	24722	12
T6	422	4
T7	15140	0
T8	0	2
T9	0	2
T13	507	6
T14	507	5
T15	501	5
T21	0	5
T27	5516	0
T47	523	5
T48	0	2

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes
Total	9452567	8792903
T1	26361	25920
T2	13744	13321
T3	2057	1657
T4	24722	20721
T5	8493	8086
T6	422	22
T7	15140	14724
T13	507	107
T14	507	107
T15	501	101

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	9452567	32
T8	1043	1
T9	933	0
T10	47669	0
T21	492	0
T22	495	0
T24	0	1
T32	0	2
T36	0	1
T43	644	0
T49	752	0
T65	522	0
T66	430	0
T67	426	0
T87	0	3
T91	0	1
T148	0	1
T179	0	1
T191	0	2
T192	0	1

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T9,T36,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T9,T36,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T9,T36,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T36,T38
1	0	Covered	T1,T5,T6
1	1	Covered	T9,T36,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T36,T38
0	1	Covered	T9,T193
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T36,T38
0	1	Covered	T36,T38,T32
1	0	Covered	T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T36,T38
1	-	Covered	T36,T38,T32

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T36,T38
DetectSt	168	Covered	T9,T36,T38
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T9,T36,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T36,T38
DebounceSt->IdleSt	163	Covered	T32,T133,T194
DetectSt->IdleSt	186	Covered	T9,T193
DetectSt->StableSt	191	Covered	T9,T36,T38
IdleSt->DebounceSt	148	Covered	T9,T36,T38
StableSt->IdleSt	206	Covered	T36,T38,T32

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T36,T38
0	1	Covered	T9,T36,T38
0	0	Excluded	T1,T5,T6	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T9,T36,T38
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T36,T38
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T83
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T36,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T32,T133,T194
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T36,T38
DetectSt	-	-	-	-	1	-	-	Covered	T9,T193
DetectSt	-	-	-	-	0	1	-	Covered	T9,T36,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T36,T38,T32
StableSt	-	-	-	-	-	-	0	Covered	T9,T36,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9452567	103	0	0
CntIncr_A	9452567	4800	0	0
CntNoWrap_A	9452567	8790373	0	0
DetectStDropOut_A	9452567	2	0	0
DetectedOut_A	9452567	5389	0	0
DetectedPulseOut_A	9452567	47	0	0
DisabledIdleSt_A	9452567	8764479	0	0
DisabledNoDetection_A	9452567	8766860	0	0
EnterDebounceSt_A	9452567	54	0	0
EnterDetectSt_A	9452567	49	0	0
EnterStableSt_A	9452567	47	0	0
PulseIsPulse_A	9452567	47	0	0
StayInStableSt	9452567	5327	0	0
gen_high_level_sva.HighLevelEvent_A	9452567	8792903	0	0
gen_not_sticky_sva.StableStDropOut_A	9452567	31	0	0

CntClr_A

Name	Attempts	Real Successes
Total	9452567	103
T9	933	4
T10	47669	0
T11	33091	0
T22	495	0
T32	0	8
T35	0	2
T36	0	2
T38	0	4
T49	752	0
T65	522	0
T66	430	0
T67	426	0
T68	525	0
T69	529	0
T72	0	2
T85	0	4
T86	0	6
T87	0	4
T169	0	2

CntIncr_A

Name	Attempts	Real Successes
Total	9452567	4800
T9	933	188
T10	47669	0
T11	33091	0
T22	495	0
T32	0	115
T35	0	90
T36	0	36
T38	0	42
T49	752	0
T65	522	0
T66	430	0
T67	426	0
T68	525	0
T69	529	0
T72	0	38
T85	0	170
T86	0	239
T87	0	84
T169	0	2303

CntNoWrap_A

Name	Attempts	Real Successes
Total	9452567	8790373
T1	26361	25911
T2	13744	13317
T3	2057	1656
T4	24722	20703
T5	8493	8083
T6	422	21
T7	15140	14720
T13	507	106
T14	507	106
T15	501	100

DetectStDropOut_A

Name	Attempts	Real Successes
Total	9452567	2
T9	933	1
T10	47669	0
T11	33091	0
T22	495	0
T49	752	0
T65	522	0
T66	430	0
T67	426	0
T68	525	0
T69	529	0
T193	0	1

DetectedOut_A

Name	Attempts	Real Successes
Total	9452567	5389
T9	933	199
T10	47669	0
T11	33091	0
T22	495	0
T32	0	149
T35	0	189
T36	0	41
T38	0	51
T49	752	0
T65	522	0
T66	430	0
T67	426	0
T68	525	0
T69	529	0
T72	0	42
T85	0	87
T86	0	346
T87	0	124
T169	0	1553

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	9452567	47
T9	933	1
T10	47669	0
T11	33091	0
T22	495	0
T32	0	3
T35	0	1
T36	0	1
T38	0	2
T49	752	0
T65	522	0
T66	430	0
T67	426	0
T68	525	0
T69	529	0
T72	0	1
T85	0	2
T86	0	3
T87	0	2
T169	0	1

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	9452567	8764479
T1	26361	25911
T2	13744	13317
T3	2057	1656
T4	24722	20703
T5	8493	8083
T6	422	21
T7	15140	14720
T13	507	106
T14	507	106
T15	501	100

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	9452567	8766860
T1	26361	25920
T2	13744	13321
T3	2057	1657
T4	24722	20721
T5	8493	8086
T6	422	22
T7	15140	14724
T13	507	107
T14	507	107
T15	501	101

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	9452567	54
T9	933	2
T10	47669	0
T11	33091	0
T22	495	0
T32	0	5
T35	0	1
T36	0	1
T38	0	2
T49	752	0
T65	522	0
T66	430	0
T67	426	0
T68	525	0
T69	529	0
T72	0	1
T85	0	2
T86	0	3
T87	0	2
T169	0	1

EnterDetectSt_A

Name	Attempts	Real Successes
Total	9452567	49
T9	933	2
T10	47669	0
T11	33091	0
T22	495	0
T32	0	3
T35	0	1
T36	0	1
T38	0	2
T49	752	0
T65	522	0
T66	430	0
T67	426	0
T68	525	0
T69	529	0
T72	0	1
T85	0	2
T86	0	3
T87	0	2
T169	0	1

EnterStableSt_A

Name	Attempts	Real Successes
Total	9452567	47
T9	933	1
T10	47669	0
T11	33091	0
T22	495	0
T32	0	3
T35	0	1
T36	0	1
T38	0	2
T49	752	0
T65	522	0
T66	430	0
T67	426	0
T68	525	0
T69	529	0
T72	0	1
T85	0	2
T86	0	3
T87	0	2
T169	0	1

PulseIsPulse_A

Name	Attempts	Real Successes
Total	9452567	47
T9	933	1
T10	47669	0
T11	33091	0
T22	495	0
T32	0	3
T35	0	1
T36	0	1
T38	0	2
T49	752	0
T65	522	0
T66	430	0
T67	426	0
T68	525	0
T69	529	0
T72	0	1
T85	0	2
T86	0	3
T87	0	2
T169	0	1

StayInStableSt

Name	Attempts	Real Successes
Total	9452567	5327
T9	933	197
T10	47669	0
T11	33091	0
T22	495	0
T32	0	145
T35	0	188
T36	0	40
T38	0	48
T49	752	0
T65	522	0
T66	430	0
T67	426	0
T68	525	0
T69	529	0
T72	0	40
T85	0	84
T86	0	341
T87	0	122
T169	0	1552

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes
Total	9452567	8792903
T1	26361	25920
T2	13744	13321
T3	2057	1657
T4	24722	20721
T5	8493	8086
T6	422	22
T7	15140	14724
T13	507	107
T14	507	107
T15	501	101

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	9452567	31
T32	0	2
T33	1104	0
T35	0	1
T36	1730	1
T38	589	1
T40	12809	0
T73	5166	0
T85	0	1
T86	0	1
T87	0	2
T133	0	2
T159	0	1
T169	0	1
T195	430	0
T196	1047	0
T197	502	0
T198	402	0
T199	522	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T24,T36,T32

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T24,T36,T32

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T24,T36,T32

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T24,T36,T32
1	0	Covered	T1,T5,T6
1	1	Covered	T24,T36,T32

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T24,T36,T32
0	1	Covered	T85
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T24,T36,T32
0	1	Covered	T24,T32,T86
1	0	Covered	T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T24,T36,T32
1	-	Covered	T24,T32,T86

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T24,T36,T32
DetectSt	168	Covered	T24,T36,T32
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T24,T36,T32

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T24,T36,T32
DebounceSt->IdleSt	163	Covered	T133,T83
DetectSt->IdleSt	186	Covered	T85
DetectSt->StableSt	191	Covered	T24,T36,T32
IdleSt->DebounceSt	148	Covered	T24,T36,T32
StableSt->IdleSt	206	Covered	T24,T32,T86

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T24,T36,T32
0	1	Covered	T24,T36,T32
0	0	Excluded	T1,T5,T6	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T24,T36,T32
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T24,T36,T32
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T83
DebounceSt	-	0	1	1	-	-	-	Covered	T24,T36,T32
DebounceSt	-	0	1	0	-	-	-	Covered	T133
DebounceSt	-	0	0	-	-	-	-	Covered	T24,T36,T32
DetectSt	-	-	-	-	1	-	-	Covered	T85
DetectSt	-	-	-	-	0	1	-	Covered	T24,T36,T32
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T24,T32,T86
StableSt	-	-	-	-	-	-	0	Covered	T24,T36,T32
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9452567	82	0	0
CntIncr_A	9452567	2562	0	0
CntNoWrap_A	9452567	8790394	0	0
DetectStDropOut_A	9452567	1	0	0
DetectedOut_A	9452567	3077	0	0
DetectedPulseOut_A	9452567	39	0	0
DisabledIdleSt_A	9452567	8412304	0	0
DisabledNoDetection_A	9452567	8414677	0	0
EnterDebounceSt_A	9452567	42	0	0
EnterDetectSt_A	9452567	40	0	0
EnterStableSt_A	9452567	39	0	0
PulseIsPulse_A	9452567	39	0	0
StayInStableSt	9452567	3017	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9452567	6831	0	0
gen_low_level_sva.LowLevelEvent_A	9452567	8792903	0	0
gen_not_sticky_sva.StableStDropOut_A	9452567	17	0	0

CntClr_A

Name	Attempts	Real Successes
Total	9452567	82
T19	1675	0
T23	492	0
T24	970	2
T31	775	0
T32	0	6
T36	0	2
T41	6452	0
T44	674	0
T52	23237	0
T71	0	2
T85	0	2
T86	0	2
T90	0	2
T154	0	2
T179	0	6
T192	0	2
T200	434	0
T201	502	0
T202	405	0

CntIncr_A

Name	Attempts	Real Successes
Total	9452567	2562
T19	1675	0
T23	492	0
T24	970	59
T31	775	0
T32	0	94
T36	0	36
T41	6452	0
T44	674	0
T52	23237	0
T71	0	98
T85	0	85
T86	0	70
T90	0	12
T154	0	68
T179	0	195
T192	0	63
T200	434	0
T201	502	0
T202	405	0

CntNoWrap_A

Name	Attempts	Real Successes
Total	9452567	8790394
T1	26361	25911
T2	13744	13317
T3	2057	1656
T4	24722	20703
T5	8493	8083
T6	422	21
T7	15140	14720
T13	507	106
T14	507	106
T15	501	100

DetectStDropOut_A

Name	Attempts	Real Successes
Total	9452567	1
T77	90649	0
T85	11288	1
T203	497	0
T204	635	0
T205	2220	0
T206	403	0
T207	27762	0
T208	34612	0
T209	744	0
T210	497	0

DetectedOut_A

Name	Attempts	Real Successes
Total	9452567	3077
T19	1675	0
T23	492	0
T24	970	39
T31	775	0
T32	0	223
T36	0	60
T41	6452	0
T44	674	0
T52	23237	0
T71	0	41
T86	0	41
T90	0	62
T154	0	305
T179	0	150
T192	0	211
T200	434	0
T201	502	0
T202	405	0
T211	0	21

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	9452567	39
T19	1675	0
T23	492	0
T24	970	1
T31	775	0
T32	0	3
T36	0	1
T41	6452	0
T44	674	0
T52	23237	0
T71	0	1
T86	0	1
T90	0	1
T154	0	1
T179	0	3
T192	0	1
T200	434	0
T201	502	0
T202	405	0
T211	0	1

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	9452567	8412304
T1	26361	25911
T2	13744	13317
T3	2057	1656
T4	24722	20703
T5	8493	8083
T6	422	21
T7	15140	14720
T13	507	106
T14	507	106
T15	501	100

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	9452567	8414677
T1	26361	25920
T2	13744	13321
T3	2057	1657
T4	24722	20721
T5	8493	8086
T6	422	22
T7	15140	14724
T13	507	107
T14	507	107
T15	501	101

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	9452567	42
T19	1675	0
T23	492	0
T24	970	1
T31	775	0
T32	0	3
T36	0	1
T41	6452	0
T44	674	0
T52	23237	0
T71	0	1
T85	0	1
T86	0	1
T90	0	1
T154	0	1
T179	0	3
T192	0	1
T200	434	0
T201	502	0
T202	405	0

EnterDetectSt_A

Name	Attempts	Real Successes
Total	9452567	40
T19	1675	0
T23	492	0
T24	970	1
T31	775	0
T32	0	3
T36	0	1
T41	6452	0
T44	674	0
T52	23237	0
T71	0	1
T85	0	1
T86	0	1
T90	0	1
T154	0	1
T179	0	3
T192	0	1
T200	434	0
T201	502	0
T202	405	0

EnterStableSt_A

Name	Attempts	Real Successes
Total	9452567	39
T19	1675	0
T23	492	0
T24	970	1
T31	775	0
T32	0	3
T36	0	1
T41	6452	0
T44	674	0
T52	23237	0
T71	0	1
T86	0	1
T90	0	1
T154	0	1
T179	0	3
T192	0	1
T200	434	0
T201	502	0
T202	405	0
T211	0	1

PulseIsPulse_A

Name	Attempts	Real Successes
Total	9452567	39
T19	1675	0
T23	492	0
T24	970	1
T31	775	0
T32	0	3
T36	0	1
T41	6452	0
T44	674	0
T52	23237	0
T71	0	1
T86	0	1
T90	0	1
T154	0	1
T179	0	3
T192	0	1
T200	434	0
T201	502	0
T202	405	0
T211	0	1

StayInStableSt

Name	Attempts	Real Successes
Total	9452567	3017
T19	1675	0
T23	492	0
T24	970	38
T31	775	0
T32	0	218
T36	0	58
T41	6452	0
T44	674	0
T52	23237	0
T71	0	39
T86	0	40
T90	0	61
T154	0	303
T179	0	146
T192	0	209
T200	434	0
T201	502	0
T202	405	0
T211	0	20

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes
Total	9452567	6831
T1	26361	13
T2	13744	6
T3	2057	9
T4	24722	17
T5	8493	8
T6	422	3
T7	15140	25
T13	507	5
T14	507	5
T15	501	4

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes
Total	9452567	8792903
T1	26361	25920
T2	13744	13321
T3	2057	1657
T4	24722	20721
T5	8493	8086
T6	422	22
T7	15140	14724
T13	507	107
T14	507	107
T15	501	101

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	9452567	17
T19	1675	0
T23	492	0
T24	970	1
T31	775	0
T32	0	1
T41	6452	0
T44	674	0
T52	23237	0
T86	0	1
T90	0	1
T133	0	2
T160	0	1
T178	0	1
T179	0	2
T200	434	0
T201	502	0
T202	405	0
T211	0	1
T212	0	1

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T8,T9,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T8,T9,T24

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T8,T9,T24

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T24
1	0	Covered	T1,T5,T6
1	1	Covered	T8,T9,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T24
0	1	Covered	T24,T140,T213
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T24
0	1	Covered	T8,T9,T24
1	0	Covered	T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T9,T24
1	-	Covered	T8,T9,T24

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T9,T24
DetectSt	168	Covered	T8,T9,T24
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T8,T9,T24

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T9,T24
DebounceSt->IdleSt	163	Covered	T38,T32,T35
DetectSt->IdleSt	186	Covered	T24,T140,T213
DetectSt->StableSt	191	Covered	T8,T9,T24
IdleSt->DebounceSt	148	Covered	T8,T9,T24
StableSt->IdleSt	206	Covered	T8,T9,T24

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T9,T24
0	1	Covered	T8,T9,T24
0	0	Excluded	T1,T5,T6	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T24
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T9,T24
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T83
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T9,T24
DebounceSt	-	0	1	0	-	-	-	Covered	T38,T32,T35
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T9,T24
DetectSt	-	-	-	-	1	-	-	Covered	T24,T140,T213
DetectSt	-	-	-	-	0	1	-	Covered	T8,T9,T24
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T9,T24
StableSt	-	-	-	-	-	-	0	Covered	T8,T9,T24
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9452567	125	0	0
CntIncr_A	9452567	65322	0	0
CntNoWrap_A	9452567	8790351	0	0
DetectStDropOut_A	9452567	3	0	0
DetectedOut_A	9452567	4151	0	0
DetectedPulseOut_A	9452567	56	0	0
DisabledIdleSt_A	9452567	8648149	0	0
DisabledNoDetection_A	9452567	8650525	0	0
EnterDebounceSt_A	9452567	67	0	0
EnterDetectSt_A	9452567	59	0	0
EnterStableSt_A	9452567	56	0	0
PulseIsPulse_A	9452567	56	0	0
StayInStableSt	9452567	4074	0	0
gen_high_level_sva.HighLevelEvent_A	9452567	8792903	0	0
gen_not_sticky_sva.StableStDropOut_A	9452567	34	0	0

CntClr_A

Name	Attempts	Real Successes
Total	9452567	125
T8	1043	4
T9	933	2
T10	47669	0
T20	0	2
T21	492	0
T22	495	0
T24	0	6
T32	0	1
T35	0	1
T37	0	2
T38	0	3
T43	644	0
T49	752	0
T65	522	0
T66	430	0
T67	426	0
T78	0	2
T86	0	4

CntIncr_A

Name	Attempts	Real Successes
Total	9452567	65322
T8	1043	148
T9	933	94
T10	47669	0
T20	0	32
T21	492	0
T22	495	0
T24	0	177
T32	0	33
T35	0	90
T37	0	55
T38	0	42
T43	644	0
T49	752	0
T65	522	0
T66	430	0
T67	426	0
T78	0	29
T86	0	140

CntNoWrap_A

Name	Attempts	Real Successes
Total	9452567	8790351
T1	26361	25911
T2	13744	13317
T3	2057	1656
T4	24722	20703
T5	8493	8083
T6	422	21
T7	15140	14720
T13	507	106
T14	507	106
T15	501	100

DetectStDropOut_A

Name	Attempts	Real Successes
Total	9452567	3
T19	1675	0
T23	492	0
T24	970	1
T31	775	0
T41	6452	0
T44	674	0
T52	23237	0
T140	0	1
T200	434	0
T201	502	0
T202	405	0
T213	0	1

DetectedOut_A

Name	Attempts	Real Successes
Total	9452567	4151
T8	1043	116
T9	933	202
T10	47669	0
T20	0	74
T21	492	0
T22	495	0
T24	0	182
T37	0	145
T38	0	13
T43	644	0
T49	752	0
T65	522	0
T66	430	0
T67	426	0
T78	0	40
T86	0	294
T87	0	87
T191	0	192

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	9452567	56
T8	1043	2
T9	933	1
T10	47669	0
T20	0	1
T21	492	0
T22	495	0
T24	0	2
T37	0	1
T38	0	1
T43	644	0
T49	752	0
T65	522	0
T66	430	0
T67	426	0
T78	0	1
T86	0	2
T87	0	1
T191	0	3

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	9452567	8648149
T1	26361	25911
T2	13744	13317
T3	2057	1656
T4	24722	20703
T5	8493	8083
T6	422	21
T7	15140	14720
T13	507	106
T14	507	106
T15	501	100

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	9452567	8650525
T1	26361	25920
T2	13744	13321
T3	2057	1657
T4	24722	20721
T5	8493	8086
T6	422	22
T7	15140	14724
T13	507	107
T14	507	107
T15	501	101

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	9452567	67
T8	1043	2
T9	933	1
T10	47669	0
T20	0	1
T21	492	0
T22	495	0
T24	0	3
T32	0	1
T35	0	1
T37	0	1
T38	0	2
T43	644	0
T49	752	0
T65	522	0
T66	430	0
T67	426	0
T78	0	1
T86	0	2

EnterDetectSt_A

Name	Attempts	Real Successes
Total	9452567	59
T8	1043	2
T9	933	1
T10	47669	0
T20	0	1
T21	492	0
T22	495	0
T24	0	3
T37	0	1
T38	0	1
T43	644	0
T49	752	0
T65	522	0
T66	430	0
T67	426	0
T78	0	1
T86	0	2
T87	0	1
T191	0	3

EnterStableSt_A

Name	Attempts	Real Successes
Total	9452567	56
T8	1043	2
T9	933	1
T10	47669	0
T20	0	1
T21	492	0
T22	495	0
T24	0	2
T37	0	1
T38	0	1
T43	644	0
T49	752	0
T65	522	0
T66	430	0
T67	426	0
T78	0	1
T86	0	2
T87	0	1
T191	0	3

PulseIsPulse_A

Name	Attempts	Real Successes
Total	9452567	56
T8	1043	2
T9	933	1
T10	47669	0
T20	0	1
T21	492	0
T22	495	0
T24	0	2
T37	0	1
T38	0	1
T43	644	0
T49	752	0
T65	522	0
T66	430	0
T67	426	0
T78	0	1
T86	0	2
T87	0	1
T191	0	3

StayInStableSt

Name	Attempts	Real Successes
Total	9452567	4074
T8	1043	114
T9	933	201
T10	47669	0
T20	0	72
T21	492	0
T22	495	0
T24	0	179
T37	0	143
T38	0	12
T43	644	0
T49	752	0
T65	522	0
T66	430	0
T67	426	0
T78	0	38
T86	0	292
T87	0	86
T191	0	188

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes
Total	9452567	8792903
T1	26361	25920
T2	13744	13321
T3	2057	1657
T4	24722	20721
T5	8493	8086
T6	422	22
T7	15140	14724
T13	507	107
T14	507	107
T15	501	101

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	9452567	34
T8	1043	2
T9	933	1
T10	47669	0
T21	492	0
T22	495	0
T24	0	1
T38	0	1
T43	644	0
T49	752	0
T65	522	0
T66	430	0
T67	426	0
T86	0	2
T87	0	1
T148	0	1
T154	0	1
T191	0	2
T192	0	1

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T24,T33,T32

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T24,T33,T32

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T24,T33,T32

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T24,T37,T33
1	0	Covered	T1,T5,T6
1	1	Covered	T24,T33,T32

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T24,T33,T32
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T24,T33,T32
0	1	Covered	T24,T32,T154
1	0	Covered	T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T24,T33,T32
1	-	Covered	T24,T32,T154

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T24,T33,T32
DetectSt	168	Covered	T24,T33,T32
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T24,T33,T32

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T24,T33,T32
DebounceSt->IdleSt	163	Covered	T83,T214
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T24,T33,T32
IdleSt->DebounceSt	148	Covered	T24,T33,T32
StableSt->IdleSt	206	Covered	T24,T32,T154

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T24,T33,T32
0	1	Covered	T24,T33,T32
0	0	Excluded	T1,T5,T6	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T24,T33,T32
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T24,T33,T32
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T83
DebounceSt	-	0	1	1	-	-	-	Covered	T24,T33,T32
DebounceSt	-	0	1	0	-	-	-	Covered	T214
DebounceSt	-	0	0	-	-	-	-	Covered	T24,T33,T32
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T24,T33,T32
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T24,T32,T154
StableSt	-	-	-	-	-	-	0	Covered	T24,T33,T32
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9452567	62	0	0
CntIncr_A	9452567	63271	0	0
CntNoWrap_A	9452567	8790414	0	0
DetectStDropOut_A	9452567	0	0	0
DetectedOut_A	9452567	2517	0	0
DetectedPulseOut_A	9452567	30	0	0
DisabledIdleSt_A	9452567	8653529	0	0
DisabledNoDetection_A	9452567	8655911	0	0
EnterDebounceSt_A	9452567	32	0	0
EnterDetectSt_A	9452567	30	0	0
EnterStableSt_A	9452567	30	0	0
PulseIsPulse_A	9452567	30	0	0
StayInStableSt	9452567	2471	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9452567	6552	0	0
gen_low_level_sva.LowLevelEvent_A	9452567	8792903	0	0
gen_not_sticky_sva.StableStDropOut_A	9452567	13	0	0

CntClr_A

Name	Attempts	Real Successes
Total	9452567	62
T19	1675	0
T23	492	0
T24	970	4
T31	775	0
T32	0	4
T33	0	2
T41	6452	0
T44	674	0
T52	23237	0
T90	0	2
T133	0	6
T148	0	2
T154	0	2
T157	0	2
T159	0	2
T200	434	0
T201	502	0
T202	405	0
T211	0	2

CntIncr_A

Name	Attempts	Real Successes
Total	9452567	63271
T19	1675	0
T23	492	0
T24	970	118
T31	775	0
T32	0	61
T33	0	99
T41	6452	0
T44	674	0
T52	23237	0
T90	0	12
T133	0	71
T148	0	24
T154	0	18
T157	0	55
T159	0	43
T200	434	0
T201	502	0
T202	405	0
T211	0	79

CntNoWrap_A

Name	Attempts	Real Successes
Total	9452567	8790414
T1	26361	25911
T2	13744	13317
T3	2057	1656
T4	24722	20703
T5	8493	8083
T6	422	21
T7	15140	14720
T13	507	106
T14	507	106
T15	501	100

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	0	0	0

DetectedOut_A

Name	Attempts	Real Successes
Total	9452567	2517
T19	1675	0
T23	492	0
T24	970	80
T31	775	0
T32	0	153
T33	0	169
T41	6452	0
T44	674	0
T52	23237	0
T90	0	61
T133	0	223
T148	0	43
T154	0	50
T157	0	42
T159	0	42
T200	434	0
T201	502	0
T202	405	0
T211	0	277

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	9452567	30
T19	1675	0
T23	492	0
T24	970	2
T31	775	0
T32	0	2
T33	0	1
T41	6452	0
T44	674	0
T52	23237	0
T90	0	1
T133	0	3
T148	0	1
T154	0	1
T157	0	1
T159	0	1
T200	434	0
T201	502	0
T202	405	0
T211	0	1

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	9452567	8653529
T1	26361	25911
T2	13744	13317
T3	2057	1656
T4	24722	20703
T5	8493	8083
T6	422	21
T7	15140	14720
T13	507	106
T14	507	106
T15	501	100

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	9452567	8655911
T1	26361	25920
T2	13744	13321
T3	2057	1657
T4	24722	20721
T5	8493	8086
T6	422	22
T7	15140	14724
T13	507	107
T14	507	107
T15	501	101

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	9452567	32
T19	1675	0
T23	492	0
T24	970	2
T31	775	0
T32	0	2
T33	0	1
T41	6452	0
T44	674	0
T52	23237	0
T90	0	1
T133	0	3
T148	0	1
T154	0	1
T157	0	1
T159	0	1
T200	434	0
T201	502	0
T202	405	0
T211	0	1

EnterDetectSt_A

Name	Attempts	Real Successes
Total	9452567	30
T19	1675	0
T23	492	0
T24	970	2
T31	775	0
T32	0	2
T33	0	1
T41	6452	0
T44	674	0
T52	23237	0
T90	0	1
T133	0	3
T148	0	1
T154	0	1
T157	0	1
T159	0	1
T200	434	0
T201	502	0
T202	405	0
T211	0	1

EnterStableSt_A

Name	Attempts	Real Successes
Total	9452567	30
T19	1675	0
T23	492	0
T24	970	2
T31	775	0
T32	0	2
T33	0	1
T41	6452	0
T44	674	0
T52	23237	0
T90	0	1
T133	0	3
T148	0	1
T154	0	1
T157	0	1
T159	0	1
T200	434	0
T201	502	0
T202	405	0
T211	0	1

PulseIsPulse_A

Name	Attempts	Real Successes
Total	9452567	30
T19	1675	0
T23	492	0
T24	970	2
T31	775	0
T32	0	2
T33	0	1
T41	6452	0
T44	674	0
T52	23237	0
T90	0	1
T133	0	3
T148	0	1
T154	0	1
T157	0	1
T159	0	1
T200	434	0
T201	502	0
T202	405	0
T211	0	1

StayInStableSt

Name	Attempts	Real Successes
Total	9452567	2471
T19	1675	0
T23	492	0
T24	970	78
T31	775	0
T32	0	150
T33	0	167
T41	6452	0
T44	674	0
T52	23237	0
T90	0	60
T133	0	219
T148	0	41
T154	0	49
T157	0	40
T159	0	41
T200	434	0
T201	502	0
T202	405	0
T211	0	275

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes
Total	9452567	6552
T1	26361	12
T2	13744	10
T3	2057	0
T4	24722	13
T5	8493	8
T6	422	4
T7	15140	30
T13	507	4
T14	507	3
T15	501	5
T27	0	25

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes
Total	9452567	8792903
T1	26361	25920
T2	13744	13321
T3	2057	1657
T4	24722	20721
T5	8493	8086
T6	422	22
T7	15140	14724
T13	507	107
T14	507	107
T15	501	101

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	9452567	13
T19	1675	0
T23	492	0
T24	970	2
T31	775	0
T32	0	1
T41	6452	0
T44	674	0
T52	23237	0
T90	0	1
T133	0	2
T154	0	1
T159	0	1
T200	434	0
T201	502	0
T202	405	0
T215	0	1
T216	0	1
T217	0	1
T218	0	1

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr