Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T8,T24,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T8,T24,T36

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T8,T24,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T24,T36
1	0	Covered	T1,T5,T6
1	1	Covered	T8,T24,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T24,T36
0	1	Covered	T85,T133
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T24,T36
0	1	Covered	T8,T24,T36
1	0	Covered	T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T24,T36
1	-	Covered	T8,T24,T36

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T24,T36
DetectSt	168	Covered	T8,T24,T36
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T8,T24,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T24,T36
DebounceSt->IdleSt	163	Covered	T90,T160,T83
DetectSt->IdleSt	186	Covered	T85,T133
DetectSt->StableSt	191	Covered	T8,T24,T36
IdleSt->DebounceSt	148	Covered	T8,T24,T36
StableSt->IdleSt	206	Covered	T8,T24,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T24,T36
0	1	Covered	T8,T24,T36
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T24,T36
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T24,T36
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T83
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T24,T36
DebounceSt	-	0	1	0	-	-	-	Covered	T90,T160,T168
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T24,T36
DetectSt	-	-	-	-	1	-	-	Covered	T85,T133
DetectSt	-	-	-	-	0	1	-	Covered	T8,T24,T36
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T24,T36
StableSt	-	-	-	-	-	-	0	Covered	T8,T24,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9452567	119	0	0
CntIncr_A	9452567	67603	0	0
CntNoWrap_A	9452567	8790357	0	0
DetectStDropOut_A	9452567	2	0	0
DetectedOut_A	9452567	72701	0	0
DetectedPulseOut_A	9452567	55	0	0
DisabledIdleSt_A	9452567	8639002	0	0
DisabledNoDetection_A	9452567	8641377	0	0
EnterDebounceSt_A	9452567	63	0	0
EnterDetectSt_A	9452567	57	0	0
EnterStableSt_A	9452567	55	0	0
PulseIsPulse_A	9452567	55	0	0
StayInStableSt	9452567	72623	0	0
gen_high_level_sva.HighLevelEvent_A	9452567	8792903	0	0
gen_not_sticky_sva.StableStDropOut_A	9452567	31	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	119	0	0
T8	1043	2	0	0
T9	933	0	0	0
T10	47669	0	0	0
T21	492	0	0	0
T22	495	0	0	0
T24	0	2	0	0
T32	0	6	0	0
T33	0	4	0	0
T34	0	2	0	0
T36	0	4	0	0
T43	644	0	0	0
T49	752	0	0	0
T65	522	0	0	0
T66	430	0	0	0
T67	426	0	0	0
T71	0	2	0	0
T72	0	2	0	0
T85	0	4	0	0
T181	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	67603	0	0
T8	1043	74	0	0
T9	933	0	0	0
T10	47669	0	0	0
T21	492	0	0	0
T22	495	0	0	0
T24	0	59	0	0
T32	0	74	0	0
T33	0	198	0	0
T34	0	53	0	0
T36	0	72	0	0
T43	644	0	0	0
T49	752	0	0	0
T65	522	0	0	0
T66	430	0	0	0
T67	426	0	0	0
T71	0	98	0	0
T72	0	38	0	0
T85	0	170	0	0
T181	0	68	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	8790357	0	0
T1	26361	25911	0	0
T2	13744	13317	0	0
T3	2057	1656	0	0
T4	24722	20703	0	0
T5	8493	8083	0	0
T6	422	21	0	0
T7	15140	14720	0	0
T13	507	106	0	0
T14	507	106	0	0
T15	501	100	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	2	0	0
T77	90649	0	0	0
T85	11288	1	0	0
T133	0	1	0	0
T203	497	0	0	0
T204	635	0	0	0
T205	2220	0	0	0
T206	403	0	0	0
T207	27762	0	0	0
T208	34612	0	0	0
T209	744	0	0	0
T210	497	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	72701	0	0
T8	1043	160	0	0
T9	933	0	0	0
T10	47669	0	0	0
T21	492	0	0	0
T22	495	0	0	0
T24	0	53	0	0
T32	0	174	0	0
T33	0	482	0	0
T34	0	106	0	0
T36	0	131	0	0
T43	644	0	0	0
T49	752	0	0	0
T65	522	0	0	0
T66	430	0	0	0
T67	426	0	0	0
T71	0	69	0	0
T72	0	111	0	0
T85	0	45	0	0
T181	0	76	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	55	0	0
T8	1043	1	0	0
T9	933	0	0	0
T10	47669	0	0	0
T21	492	0	0	0
T22	495	0	0	0
T24	0	1	0	0
T32	0	3	0	0
T33	0	2	0	0
T34	0	1	0	0
T36	0	2	0	0
T43	644	0	0	0
T49	752	0	0	0
T65	522	0	0	0
T66	430	0	0	0
T67	426	0	0	0
T71	0	1	0	0
T72	0	1	0	0
T85	0	1	0	0
T181	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	8639002	0	0
T1	26361	25911	0	0
T2	13744	13317	0	0
T3	2057	1656	0	0
T4	24722	20703	0	0
T5	8493	8083	0	0
T6	422	21	0	0
T7	15140	14720	0	0
T13	507	106	0	0
T14	507	106	0	0
T15	501	100	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	8641377	0	0
T1	26361	25920	0	0
T2	13744	13321	0	0
T3	2057	1657	0	0
T4	24722	20721	0	0
T5	8493	8086	0	0
T6	422	22	0	0
T7	15140	14724	0	0
T13	507	107	0	0
T14	507	107	0	0
T15	501	101	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	63	0	0
T8	1043	1	0	0
T9	933	0	0	0
T10	47669	0	0	0
T21	492	0	0	0
T22	495	0	0	0
T24	0	1	0	0
T32	0	3	0	0
T33	0	2	0	0
T34	0	1	0	0
T36	0	2	0	0
T43	644	0	0	0
T49	752	0	0	0
T65	522	0	0	0
T66	430	0	0	0
T67	426	0	0	0
T71	0	1	0	0
T72	0	1	0	0
T85	0	2	0	0
T181	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	57	0	0
T8	1043	1	0	0
T9	933	0	0	0
T10	47669	0	0	0
T21	492	0	0	0
T22	495	0	0	0
T24	0	1	0	0
T32	0	3	0	0
T33	0	2	0	0
T34	0	1	0	0
T36	0	2	0	0
T43	644	0	0	0
T49	752	0	0	0
T65	522	0	0	0
T66	430	0	0	0
T67	426	0	0	0
T71	0	1	0	0
T72	0	1	0	0
T85	0	2	0	0
T181	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	55	0	0
T8	1043	1	0	0
T9	933	0	0	0
T10	47669	0	0	0
T21	492	0	0	0
T22	495	0	0	0
T24	0	1	0	0
T32	0	3	0	0
T33	0	2	0	0
T34	0	1	0	0
T36	0	2	0	0
T43	644	0	0	0
T49	752	0	0	0
T65	522	0	0	0
T66	430	0	0	0
T67	426	0	0	0
T71	0	1	0	0
T72	0	1	0	0
T85	0	1	0	0
T181	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	55	0	0
T8	1043	1	0	0
T9	933	0	0	0
T10	47669	0	0	0
T21	492	0	0	0
T22	495	0	0	0
T24	0	1	0	0
T32	0	3	0	0
T33	0	2	0	0
T34	0	1	0	0
T36	0	2	0	0
T43	644	0	0	0
T49	752	0	0	0
T65	522	0	0	0
T66	430	0	0	0
T67	426	0	0	0
T71	0	1	0	0
T72	0	1	0	0
T85	0	1	0	0
T181	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	72623	0	0
T8	1043	159	0	0
T9	933	0	0	0
T10	47669	0	0	0
T21	492	0	0	0
T22	495	0	0	0
T24	0	52	0	0
T32	0	170	0	0
T33	0	479	0	0
T34	0	105	0	0
T36	0	128	0	0
T43	644	0	0	0
T49	752	0	0	0
T65	522	0	0	0
T66	430	0	0	0
T67	426	0	0	0
T71	0	68	0	0
T72	0	109	0	0
T85	0	43	0	0
T181	0	74	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	8792903	0	0
T1	26361	25920	0	0
T2	13744	13321	0	0
T3	2057	1657	0	0
T4	24722	20721	0	0
T5	8493	8086	0	0
T6	422	22	0	0
T7	15140	14724	0	0
T13	507	107	0	0
T14	507	107	0	0
T15	501	101	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	31	0	0
T8	1043	1	0	0
T9	933	0	0	0
T10	47669	0	0	0
T21	492	0	0	0
T22	495	0	0	0
T24	0	1	0	0
T32	0	2	0	0
T33	0	1	0	0
T34	0	1	0	0
T36	0	1	0	0
T43	644	0	0	0
T49	752	0	0	0
T65	522	0	0	0
T66	430	0	0	0
T67	426	0	0	0
T71	0	1	0	0
T86	0	2	0	0
T111	0	1	0	0
T169	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T36,T33,T32

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T36,T33,T32

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T32,T34,T35

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T36,T33,T32
1	0	Covered	T1,T5,T6
1	1	Covered	T36,T33,T32

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T32,T34,T35
0	1	Covered	T154,T148,T219
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T32,T34,T35
0	1	Covered	T35,T159,T133
1	0	Covered	T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T32,T34,T35
1	-	Covered	T35,T159,T133

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T36,T33,T32
DetectSt	168	Covered	T32,T34,T35
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T32,T34,T35

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T32,T34,T35
DebounceSt->IdleSt	163	Covered	T36,T33,T83
DetectSt->IdleSt	186	Covered	T154,T148,T219
DetectSt->StableSt	191	Covered	T32,T34,T35
IdleSt->DebounceSt	148	Covered	T36,T33,T32
StableSt->IdleSt	206	Covered	T32,T34,T35

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T36,T33,T32
0	1	Covered	T36,T33,T32
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T32,T34,T35
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T36,T33,T32
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T83
DebounceSt	-	0	1	1	-	-	-	Covered	T32,T34,T35
DebounceSt	-	0	1	0	-	-	-	Covered	T36,T33
DebounceSt	-	0	0	-	-	-	-	Covered	T36,T33,T32
DetectSt	-	-	-	-	1	-	-	Covered	T154,T148,T219
DetectSt	-	-	-	-	0	1	-	Covered	T32,T34,T35
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T35,T159,T133
StableSt	-	-	-	-	-	-	0	Covered	T32,T34,T35
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9452567	65	0	0
CntIncr_A	9452567	4057	0	0
CntNoWrap_A	9452567	8790411	0	0
DetectStDropOut_A	9452567	3	0	0
DetectedOut_A	9452567	1926	0	0
DetectedPulseOut_A	9452567	28	0	0
DisabledIdleSt_A	9452567	8640933	0	0
DisabledNoDetection_A	9452567	8643313	0	0
EnterDebounceSt_A	9452567	34	0	0
EnterDetectSt_A	9452567	31	0	0
EnterStableSt_A	9452567	28	0	0
PulseIsPulse_A	9452567	28	0	0
StayInStableSt	9452567	1880	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9452567	6465	0	0
gen_low_level_sva.LowLevelEvent_A	9452567	8792903	0	0
gen_not_sticky_sva.StableStDropOut_A	9452567	9	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	65	0	0
T32	0	2	0	0
T33	1104	1	0	0
T34	0	2	0	0
T35	0	2	0	0
T36	1730	1	0	0
T38	589	0	0	0
T40	12809	0	0	0
T73	5166	0	0	0
T78	0	2	0	0
T148	0	2	0	0
T154	0	6	0	0
T156	0	2	0	0
T169	0	2	0	0
T195	430	0	0	0
T196	1047	0	0	0
T197	502	0	0	0
T198	402	0	0	0
T199	522	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	4057	0	0
T32	0	13	0	0
T33	1104	99	0	0
T34	0	53	0	0
T35	0	90	0	0
T36	1730	36	0	0
T38	589	0	0	0
T40	12809	0	0	0
T73	5166	0	0	0
T78	0	29	0	0
T148	0	24	0	0
T154	0	204	0	0
T156	0	74	0	0
T169	0	2303	0	0
T195	430	0	0	0
T196	1047	0	0	0
T197	502	0	0	0
T198	402	0	0	0
T199	522	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	8790411	0	0
T1	26361	25911	0	0
T2	13744	13317	0	0
T3	2057	1656	0	0
T4	24722	20703	0	0
T5	8493	8083	0	0
T6	422	21	0	0
T7	15140	14720	0	0
T13	507	106	0	0
T14	507	106	0	0
T15	501	100	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	3	0	0
T148	0	1	0	0
T154	13854	1	0	0
T182	503	0	0	0
T183	492	0	0	0
T184	493	0	0	0
T185	425	0	0	0
T186	407	0	0	0
T187	502	0	0	0
T188	528	0	0	0
T189	404	0	0	0
T190	12544	0	0	0
T219	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	1926	0	0
T32	41648	129	0	0
T34	0	94	0	0
T35	0	58	0	0
T46	2973	0	0	0
T60	496	0	0	0
T71	717	0	0	0
T72	679	0	0	0
T74	21671	0	0	0
T78	0	97	0	0
T154	0	176	0	0
T156	0	42	0	0
T158	0	72	0	0
T159	0	162	0	0
T169	0	44	0	0
T211	0	53	0	0
T220	492	0	0	0
T221	404	0	0	0
T222	1017	0	0	0
T223	412	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	28	0	0
T32	41648	1	0	0
T34	0	1	0	0
T35	0	1	0	0
T46	2973	0	0	0
T60	496	0	0	0
T71	717	0	0	0
T72	679	0	0	0
T74	21671	0	0	0
T78	0	1	0	0
T154	0	2	0	0
T156	0	1	0	0
T158	0	1	0	0
T159	0	2	0	0
T169	0	1	0	0
T211	0	1	0	0
T220	492	0	0	0
T221	404	0	0	0
T222	1017	0	0	0
T223	412	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	8640933	0	0
T1	26361	25911	0	0
T2	13744	13317	0	0
T3	2057	1656	0	0
T4	24722	20703	0	0
T5	8493	8083	0	0
T6	422	21	0	0
T7	15140	14720	0	0
T13	507	106	0	0
T14	507	106	0	0
T15	501	100	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	8643313	0	0
T1	26361	25920	0	0
T2	13744	13321	0	0
T3	2057	1657	0	0
T4	24722	20721	0	0
T5	8493	8086	0	0
T6	422	22	0	0
T7	15140	14724	0	0
T13	507	107	0	0
T14	507	107	0	0
T15	501	101	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	34	0	0
T32	0	1	0	0
T33	1104	1	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	1730	1	0	0
T38	589	0	0	0
T40	12809	0	0	0
T73	5166	0	0	0
T78	0	1	0	0
T148	0	1	0	0
T154	0	3	0	0
T156	0	1	0	0
T169	0	1	0	0
T195	430	0	0	0
T196	1047	0	0	0
T197	502	0	0	0
T198	402	0	0	0
T199	522	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	31	0	0
T32	41648	1	0	0
T34	0	1	0	0
T35	0	1	0	0
T46	2973	0	0	0
T60	496	0	0	0
T71	717	0	0	0
T72	679	0	0	0
T74	21671	0	0	0
T78	0	1	0	0
T148	0	1	0	0
T154	0	3	0	0
T156	0	1	0	0
T158	0	1	0	0
T159	0	2	0	0
T169	0	1	0	0
T220	492	0	0	0
T221	404	0	0	0
T222	1017	0	0	0
T223	412	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	28	0	0
T32	41648	1	0	0
T34	0	1	0	0
T35	0	1	0	0
T46	2973	0	0	0
T60	496	0	0	0
T71	717	0	0	0
T72	679	0	0	0
T74	21671	0	0	0
T78	0	1	0	0
T154	0	2	0	0
T156	0	1	0	0
T158	0	1	0	0
T159	0	2	0	0
T169	0	1	0	0
T211	0	1	0	0
T220	492	0	0	0
T221	404	0	0	0
T222	1017	0	0	0
T223	412	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	28	0	0
T32	41648	1	0	0
T34	0	1	0	0
T35	0	1	0	0
T46	2973	0	0	0
T60	496	0	0	0
T71	717	0	0	0
T72	679	0	0	0
T74	21671	0	0	0
T78	0	1	0	0
T154	0	2	0	0
T156	0	1	0	0
T158	0	1	0	0
T159	0	2	0	0
T169	0	1	0	0
T211	0	1	0	0
T220	492	0	0	0
T221	404	0	0	0
T222	1017	0	0	0
T223	412	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	1880	0	0
T32	41648	127	0	0
T34	0	92	0	0
T35	0	57	0	0
T46	2973	0	0	0
T60	496	0	0	0
T71	717	0	0	0
T72	679	0	0	0
T74	21671	0	0	0
T78	0	95	0	0
T154	0	172	0	0
T156	0	40	0	0
T158	0	70	0	0
T159	0	159	0	0
T169	0	42	0	0
T211	0	51	0	0
T220	492	0	0	0
T221	404	0	0	0
T222	1017	0	0	0
T223	412	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	6465	0	0
T1	26361	10	0	0
T2	13744	8	0	0
T3	2057	0	0	0
T4	24722	16	0	0
T5	8493	9	0	0
T6	422	4	0	0
T7	15140	26	0	0
T13	507	5	0	0
T14	507	4	0	0
T15	501	5	0	0
T27	0	26	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	8792903	0	0
T1	26361	25920	0	0
T2	13744	13321	0	0
T3	2057	1657	0	0
T4	24722	20721	0	0
T5	8493	8086	0	0
T6	422	22	0	0
T7	15140	14724	0	0
T13	507	107	0	0
T14	507	107	0	0
T15	501	101	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	9	0	0
T35	1209	1	0	0
T133	0	1	0	0
T155	0	1	0	0
T159	0	1	0	0
T217	0	1	0	0
T218	0	1	0	0
T219	0	1	0	0
T224	0	1	0	0
T225	0	1	0	0
T226	526	0	0	0
T227	19416	0	0	0
T228	418	0	0	0
T229	1212	0	0	0
T230	2334	0	0	0
T231	486	0	0	0
T232	494	0	0	0
T233	9266	0	0	0
T234	539	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T8,T9,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T8,T9,T24

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T8,T9,T24

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T24
1	0	Covered	T1,T5,T6
1	1	Covered	T8,T9,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T24
0	1	Covered	T154,T180,T235
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T24
0	1	Covered	T8,T9,T24
1	0	Covered	T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T9,T24
1	-	Covered	T8,T9,T24

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T9,T24
DetectSt	168	Covered	T8,T9,T24
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T8,T9,T24

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T9,T24
DebounceSt->IdleSt	163	Covered	T20,T154,T158
DetectSt->IdleSt	186	Covered	T154,T180,T235
DetectSt->StableSt	191	Covered	T8,T9,T24
IdleSt->DebounceSt	148	Covered	T8,T9,T24
StableSt->IdleSt	206	Covered	T8,T9,T24

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T9,T24
0	1	Covered	T8,T9,T24
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T24
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T9,T24
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T83
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T9,T24
DebounceSt	-	0	1	0	-	-	-	Covered	T20,T154,T158
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T9,T24
DetectSt	-	-	-	-	1	-	-	Covered	T154,T180,T235
DetectSt	-	-	-	-	0	1	-	Covered	T8,T9,T24
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T9,T24
StableSt	-	-	-	-	-	-	0	Covered	T8,T9,T24
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9452567	115	0	0
CntIncr_A	9452567	5666	0	0
CntNoWrap_A	9452567	8790361	0	0
DetectStDropOut_A	9452567	4	0	0
DetectedOut_A	9452567	13136	0	0
DetectedPulseOut_A	9452567	51	0	0
DisabledIdleSt_A	9452567	8763975	0	0
DisabledNoDetection_A	9452567	8766355	0	0
EnterDebounceSt_A	9452567	60	0	0
EnterDetectSt_A	9452567	55	0	0
EnterStableSt_A	9452567	51	0	0
PulseIsPulse_A	9452567	51	0	0
StayInStableSt	9452567	13062	0	0
gen_high_level_sva.HighLevelEvent_A	9452567	8792903	0	0
gen_not_sticky_sva.StableStDropOut_A	9452567	27	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	115	0	0
T8	1043	4	0	0
T9	933	2	0	0
T10	47669	0	0	0
T20	0	1	0	0
T21	492	0	0	0
T22	495	0	0	0
T24	0	2	0	0
T32	0	2	0	0
T34	0	2	0	0
T38	0	2	0	0
T43	644	0	0	0
T49	752	0	0	0
T65	522	0	0	0
T66	430	0	0	0
T67	426	0	0	0
T71	0	2	0	0
T72	0	2	0	0
T156	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	5666	0	0
T8	1043	148	0	0
T9	933	94	0	0
T10	47669	0	0	0
T20	0	32	0	0
T21	492	0	0	0
T22	495	0	0	0
T24	0	59	0	0
T32	0	33	0	0
T34	0	53	0	0
T38	0	21	0	0
T43	644	0	0	0
T49	752	0	0	0
T65	522	0	0	0
T66	430	0	0	0
T67	426	0	0	0
T71	0	98	0	0
T72	0	38	0	0
T156	0	74	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	8790361	0	0
T1	26361	25911	0	0
T2	13744	13317	0	0
T3	2057	1656	0	0
T4	24722	20703	0	0
T5	8493	8083	0	0
T6	422	21	0	0
T7	15140	14720	0	0
T13	507	106	0	0
T14	507	106	0	0
T15	501	100	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	4	0	0
T140	0	1	0	0
T154	13854	1	0	0
T180	0	1	0	0
T182	503	0	0	0
T183	492	0	0	0
T184	493	0	0	0
T185	425	0	0	0
T186	407	0	0	0
T187	502	0	0	0
T188	528	0	0	0
T189	404	0	0	0
T190	12544	0	0	0
T235	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	13136	0	0
T8	1043	105	0	0
T9	933	296	0	0
T10	47669	0	0	0
T21	492	0	0	0
T22	495	0	0	0
T24	0	100	0	0
T32	0	61	0	0
T34	0	106	0	0
T38	0	40	0	0
T43	644	0	0	0
T49	752	0	0	0
T65	522	0	0	0
T66	430	0	0	0
T67	426	0	0	0
T71	0	42	0	0
T72	0	111	0	0
T156	0	26	0	0
T169	0	8552	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	51	0	0
T8	1043	2	0	0
T9	933	1	0	0
T10	47669	0	0	0
T21	492	0	0	0
T22	495	0	0	0
T24	0	1	0	0
T32	0	1	0	0
T34	0	1	0	0
T38	0	1	0	0
T43	644	0	0	0
T49	752	0	0	0
T65	522	0	0	0
T66	430	0	0	0
T67	426	0	0	0
T71	0	1	0	0
T72	0	1	0	0
T156	0	1	0	0
T169	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	8763975	0	0
T1	26361	25911	0	0
T2	13744	13317	0	0
T3	2057	1656	0	0
T4	24722	20703	0	0
T5	8493	8083	0	0
T6	422	21	0	0
T7	15140	14720	0	0
T13	507	106	0	0
T14	507	106	0	0
T15	501	100	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	8766355	0	0
T1	26361	25920	0	0
T2	13744	13321	0	0
T3	2057	1657	0	0
T4	24722	20721	0	0
T5	8493	8086	0	0
T6	422	22	0	0
T7	15140	14724	0	0
T13	507	107	0	0
T14	507	107	0	0
T15	501	101	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	60	0	0
T8	1043	2	0	0
T9	933	1	0	0
T10	47669	0	0	0
T20	0	1	0	0
T21	492	0	0	0
T22	495	0	0	0
T24	0	1	0	0
T32	0	1	0	0
T34	0	1	0	0
T38	0	1	0	0
T43	644	0	0	0
T49	752	0	0	0
T65	522	0	0	0
T66	430	0	0	0
T67	426	0	0	0
T71	0	1	0	0
T72	0	1	0	0
T156	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	55	0	0
T8	1043	2	0	0
T9	933	1	0	0
T10	47669	0	0	0
T21	492	0	0	0
T22	495	0	0	0
T24	0	1	0	0
T32	0	1	0	0
T34	0	1	0	0
T38	0	1	0	0
T43	644	0	0	0
T49	752	0	0	0
T65	522	0	0	0
T66	430	0	0	0
T67	426	0	0	0
T71	0	1	0	0
T72	0	1	0	0
T156	0	1	0	0
T169	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	51	0	0
T8	1043	2	0	0
T9	933	1	0	0
T10	47669	0	0	0
T21	492	0	0	0
T22	495	0	0	0
T24	0	1	0	0
T32	0	1	0	0
T34	0	1	0	0
T38	0	1	0	0
T43	644	0	0	0
T49	752	0	0	0
T65	522	0	0	0
T66	430	0	0	0
T67	426	0	0	0
T71	0	1	0	0
T72	0	1	0	0
T156	0	1	0	0
T169	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	51	0	0
T8	1043	2	0	0
T9	933	1	0	0
T10	47669	0	0	0
T21	492	0	0	0
T22	495	0	0	0
T24	0	1	0	0
T32	0	1	0	0
T34	0	1	0	0
T38	0	1	0	0
T43	644	0	0	0
T49	752	0	0	0
T65	522	0	0	0
T66	430	0	0	0
T67	426	0	0	0
T71	0	1	0	0
T72	0	1	0	0
T156	0	1	0	0
T169	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	13062	0	0
T8	1043	102	0	0
T9	933	295	0	0
T10	47669	0	0	0
T21	492	0	0	0
T22	495	0	0	0
T24	0	99	0	0
T32	0	59	0	0
T34	0	105	0	0
T38	0	39	0	0
T43	644	0	0	0
T49	752	0	0	0
T65	522	0	0	0
T66	430	0	0	0
T67	426	0	0	0
T71	0	40	0	0
T72	0	110	0	0
T156	0	25	0	0
T169	0	8550	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	8792903	0	0
T1	26361	25920	0	0
T2	13744	13321	0	0
T3	2057	1657	0	0
T4	24722	20721	0	0
T5	8493	8086	0	0
T6	422	22	0	0
T7	15140	14724	0	0
T13	507	107	0	0
T14	507	107	0	0
T15	501	101	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	27	0	0
T8	1043	1	0	0
T9	933	1	0	0
T10	47669	0	0	0
T21	492	0	0	0
T22	495	0	0	0
T24	0	1	0	0
T34	0	1	0	0
T38	0	1	0	0
T43	644	0	0	0
T49	752	0	0	0
T65	522	0	0	0
T66	430	0	0	0
T67	426	0	0	0
T72	0	1	0	0
T90	0	1	0	0
T91	0	1	0	0
T154	0	1	0	0
T156	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T8,T9,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T8,T9,T24

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T8,T9,T24

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T24
1	0	Covered	T1,T5,T6
1	1	Covered	T8,T9,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T24
0	1	Covered	T87,T160
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T24
0	1	Covered	T8,T33,T86
1	0	Covered	T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T9,T24
1	-	Covered	T8,T33,T86

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T9,T24
DetectSt	168	Covered	T8,T9,T24
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T8,T9,T24

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T9,T24
DebounceSt->IdleSt	163	Covered	T212,T83
DetectSt->IdleSt	186	Covered	T87,T160
DetectSt->StableSt	191	Covered	T8,T9,T24
IdleSt->DebounceSt	148	Covered	T8,T9,T24
StableSt->IdleSt	206	Covered	T8,T33,T32

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T9,T24
0	1	Covered	T8,T9,T24
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T24
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T9,T24
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T83
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T9,T24
DebounceSt	-	0	1	0	-	-	-	Covered	T212
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T9,T24
DetectSt	-	-	-	-	1	-	-	Covered	T87,T160
DetectSt	-	-	-	-	0	1	-	Covered	T8,T9,T24
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T33,T86
StableSt	-	-	-	-	-	-	0	Covered	T8,T9,T24
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9452567	86	0	0
CntIncr_A	9452567	2385	0	0
CntNoWrap_A	9452567	8790390	0	0
DetectStDropOut_A	9452567	2	0	0
DetectedOut_A	9452567	3668	0	0
DetectedPulseOut_A	9452567	40	0	0
DisabledIdleSt_A	9452567	8638447	0	0
DisabledNoDetection_A	9452567	8640824	0	0
EnterDebounceSt_A	9452567	44	0	0
EnterDetectSt_A	9452567	42	0	0
EnterStableSt_A	9452567	40	0	0
PulseIsPulse_A	9452567	40	0	0
StayInStableSt	9452567	3608	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9452567	6427	0	0
gen_low_level_sva.LowLevelEvent_A	9452567	8792903	0	0
gen_not_sticky_sva.StableStDropOut_A	9452567	19	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	86	0	0
T8	1043	2	0	0
T9	933	2	0	0
T10	47669	0	0	0
T21	492	0	0	0
T22	495	0	0	0
T24	0	2	0	0
T32	0	4	0	0
T33	0	4	0	0
T36	0	2	0	0
T37	0	2	0	0
T38	0	2	0	0
T43	644	0	0	0
T49	752	0	0	0
T65	522	0	0	0
T66	430	0	0	0
T67	426	0	0	0
T72	0	2	0	0
T86	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	2385	0	0
T8	1043	74	0	0
T9	933	94	0	0
T10	47669	0	0	0
T21	492	0	0	0
T22	495	0	0	0
T24	0	59	0	0
T32	0	51	0	0
T33	0	198	0	0
T36	0	36	0	0
T37	0	55	0	0
T38	0	21	0	0
T43	644	0	0	0
T49	752	0	0	0
T65	522	0	0	0
T66	430	0	0	0
T67	426	0	0	0
T72	0	38	0	0
T86	0	70	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	8790390	0	0
T1	26361	25911	0	0
T2	13744	13317	0	0
T3	2057	1656	0	0
T4	24722	20703	0	0
T5	8493	8083	0	0
T6	422	21	0	0
T7	15140	14720	0	0
T13	507	106	0	0
T14	507	106	0	0
T15	501	100	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	2	0	0
T87	835	1	0	0
T160	0	1	0	0
T236	10870	0	0	0
T237	489	0	0	0
T238	666	0	0	0
T239	434	0	0	0
T240	441	0	0	0
T241	409	0	0	0
T242	10314	0	0	0
T243	8117	0	0	0
T244	446	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	3668	0	0
T8	1043	305	0	0
T9	933	39	0	0
T10	47669	0	0	0
T21	492	0	0	0
T22	495	0	0	0
T24	0	341	0	0
T32	0	113	0	0
T33	0	83	0	0
T36	0	52	0	0
T37	0	145	0	0
T38	0	62	0	0
T43	644	0	0	0
T49	752	0	0	0
T65	522	0	0	0
T66	430	0	0	0
T67	426	0	0	0
T72	0	42	0	0
T86	0	28	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	40	0	0
T8	1043	1	0	0
T9	933	1	0	0
T10	47669	0	0	0
T21	492	0	0	0
T22	495	0	0	0
T24	0	1	0	0
T32	0	2	0	0
T33	0	2	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T43	644	0	0	0
T49	752	0	0	0
T65	522	0	0	0
T66	430	0	0	0
T67	426	0	0	0
T72	0	1	0	0
T86	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	8638447	0	0
T1	26361	25911	0	0
T2	13744	13317	0	0
T3	2057	1656	0	0
T4	24722	20703	0	0
T5	8493	8083	0	0
T6	422	21	0	0
T7	15140	14720	0	0
T13	507	106	0	0
T14	507	106	0	0
T15	501	100	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	8640824	0	0
T1	26361	25920	0	0
T2	13744	13321	0	0
T3	2057	1657	0	0
T4	24722	20721	0	0
T5	8493	8086	0	0
T6	422	22	0	0
T7	15140	14724	0	0
T13	507	107	0	0
T14	507	107	0	0
T15	501	101	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	44	0	0
T8	1043	1	0	0
T9	933	1	0	0
T10	47669	0	0	0
T21	492	0	0	0
T22	495	0	0	0
T24	0	1	0	0
T32	0	2	0	0
T33	0	2	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T43	644	0	0	0
T49	752	0	0	0
T65	522	0	0	0
T66	430	0	0	0
T67	426	0	0	0
T72	0	1	0	0
T86	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	42	0	0
T8	1043	1	0	0
T9	933	1	0	0
T10	47669	0	0	0
T21	492	0	0	0
T22	495	0	0	0
T24	0	1	0	0
T32	0	2	0	0
T33	0	2	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T43	644	0	0	0
T49	752	0	0	0
T65	522	0	0	0
T66	430	0	0	0
T67	426	0	0	0
T72	0	1	0	0
T86	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	40	0	0
T8	1043	1	0	0
T9	933	1	0	0
T10	47669	0	0	0
T21	492	0	0	0
T22	495	0	0	0
T24	0	1	0	0
T32	0	2	0	0
T33	0	2	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T43	644	0	0	0
T49	752	0	0	0
T65	522	0	0	0
T66	430	0	0	0
T67	426	0	0	0
T72	0	1	0	0
T86	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	40	0	0
T8	1043	1	0	0
T9	933	1	0	0
T10	47669	0	0	0
T21	492	0	0	0
T22	495	0	0	0
T24	0	1	0	0
T32	0	2	0	0
T33	0	2	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T43	644	0	0	0
T49	752	0	0	0
T65	522	0	0	0
T66	430	0	0	0
T67	426	0	0	0
T72	0	1	0	0
T86	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	3608	0	0
T8	1043	304	0	0
T9	933	37	0	0
T10	47669	0	0	0
T21	492	0	0	0
T22	495	0	0	0
T24	0	339	0	0
T32	0	109	0	0
T33	0	81	0	0
T36	0	50	0	0
T37	0	143	0	0
T38	0	60	0	0
T43	644	0	0	0
T49	752	0	0	0
T65	522	0	0	0
T66	430	0	0	0
T67	426	0	0	0
T72	0	40	0	0
T86	0	27	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	6427	0	0
T1	26361	11	0	0
T2	13744	16	0	0
T3	2057	0	0	0
T4	24722	19	0	0
T5	8493	13	0	0
T6	422	2	0	0
T7	15140	26	0	0
T13	507	5	0	0
T14	507	5	0	0
T15	501	4	0	0
T27	0	28	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	8792903	0	0
T1	26361	25920	0	0
T2	13744	13321	0	0
T3	2057	1657	0	0
T4	24722	20721	0	0
T5	8493	8086	0	0
T6	422	22	0	0
T7	15140	14724	0	0
T13	507	107	0	0
T14	507	107	0	0
T15	501	101	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	19	0	0
T8	1043	1	0	0
T9	933	0	0	0
T10	47669	0	0	0
T21	492	0	0	0
T22	495	0	0	0
T33	0	2	0	0
T43	644	0	0	0
T49	752	0	0	0
T65	522	0	0	0
T66	430	0	0	0
T67	426	0	0	0
T86	0	1	0	0
T154	0	4	0	0
T159	0	1	0	0
T192	0	1	0	0
T194	0	1	0	0
T224	0	1	0	0
T245	0	1	0	0
T246	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T8,T9,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T8,T9,T24

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T8,T9,T24

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T24
1	0	Covered	T1,T5,T6
1	1	Covered	T8,T9,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T24
0	1	Covered	T24
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T24
0	1	Covered	T33,T32,T72
1	0	Covered	T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T9,T24
1	-	Covered	T33,T32,T72

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T9,T24
DetectSt	168	Covered	T8,T9,T24
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T8,T9,T24

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T9,T24
DebounceSt->IdleSt	163	Covered	T9,T192,T83
DetectSt->IdleSt	186	Covered	T24
DetectSt->StableSt	191	Covered	T8,T9,T24
IdleSt->DebounceSt	148	Covered	T8,T9,T24
StableSt->IdleSt	206	Covered	T33,T32,T72

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T9,T24
0	1	Covered	T8,T9,T24
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T24
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T9,T24
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T83
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T9,T24
DebounceSt	-	0	1	0	-	-	-	Covered	T9,T192
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T9,T24
DetectSt	-	-	-	-	1	-	-	Covered	T24
DetectSt	-	-	-	-	0	1	-	Covered	T8,T9,T24
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T33,T32,T72
StableSt	-	-	-	-	-	-	0	Covered	T8,T9,T24
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9452567	133	0	0
CntIncr_A	9452567	67856	0	0
CntNoWrap_A	9452567	8790343	0	0
DetectStDropOut_A	9452567	1	0	0
DetectedOut_A	9452567	73763	0	0
DetectedPulseOut_A	9452567	64	0	0
DisabledIdleSt_A	9452567	8635899	0	0
DisabledNoDetection_A	9452567	8638274	0	0
EnterDebounceSt_A	9452567	68	0	0
EnterDetectSt_A	9452567	65	0	0
EnterStableSt_A	9452567	64	0	0
PulseIsPulse_A	9452567	64	0	0
StayInStableSt	9452567	73676	0	0
gen_high_level_sva.HighLevelEvent_A	9452567	8792903	0	0
gen_not_sticky_sva.StableStDropOut_A	9452567	40	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	133	0	0
T8	1043	2	0	0
T9	933	3	0	0
T10	47669	0	0	0
T20	0	2	0	0
T21	492	0	0	0
T22	495	0	0	0
T24	0	4	0	0
T32	0	6	0	0
T33	0	4	0	0
T43	644	0	0	0
T49	752	0	0	0
T65	522	0	0	0
T66	430	0	0	0
T67	426	0	0	0
T72	0	2	0	0
T85	0	2	0	0
T86	0	4	0	0
T111	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	67856	0	0
T8	1043	74	0	0
T9	933	188	0	0
T10	47669	0	0	0
T20	0	32	0	0
T21	492	0	0	0
T22	495	0	0	0
T24	0	118	0	0
T32	0	54	0	0
T33	0	198	0	0
T43	644	0	0	0
T49	752	0	0	0
T65	522	0	0	0
T66	430	0	0	0
T67	426	0	0	0
T72	0	38	0	0
T85	0	85	0	0
T86	0	169	0	0
T111	0	174	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	8790343	0	0
T1	26361	25911	0	0
T2	13744	13317	0	0
T3	2057	1656	0	0
T4	24722	20703	0	0
T5	8493	8083	0	0
T6	422	21	0	0
T7	15140	14720	0	0
T13	507	106	0	0
T14	507	106	0	0
T15	501	100	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	1	0	0
T19	1675	0	0	0
T23	492	0	0	0
T24	970	1	0	0
T31	775	0	0	0
T41	6452	0	0	0
T44	674	0	0	0
T52	23237	0	0	0
T200	434	0	0	0
T201	502	0	0	0
T202	405	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	73763	0	0
T8	1043	300	0	0
T9	933	39	0	0
T10	47669	0	0	0
T20	0	74	0	0
T21	492	0	0	0
T22	495	0	0	0
T24	0	342	0	0
T32	0	50	0	0
T33	0	214	0	0
T43	644	0	0	0
T49	752	0	0	0
T65	522	0	0	0
T66	430	0	0	0
T67	426	0	0	0
T72	0	150	0	0
T85	0	215	0	0
T86	0	378	0	0
T111	0	271	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	64	0	0
T8	1043	1	0	0
T9	933	1	0	0
T10	47669	0	0	0
T20	0	1	0	0
T21	492	0	0	0
T22	495	0	0	0
T24	0	1	0	0
T32	0	3	0	0
T33	0	2	0	0
T43	644	0	0	0
T49	752	0	0	0
T65	522	0	0	0
T66	430	0	0	0
T67	426	0	0	0
T72	0	1	0	0
T85	0	1	0	0
T86	0	2	0	0
T111	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	8635899	0	0
T1	26361	25911	0	0
T2	13744	13317	0	0
T3	2057	1656	0	0
T4	24722	20703	0	0
T5	8493	8083	0	0
T6	422	21	0	0
T7	15140	14720	0	0
T13	507	106	0	0
T14	507	106	0	0
T15	501	100	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	8638274	0	0
T1	26361	25920	0	0
T2	13744	13321	0	0
T3	2057	1657	0	0
T4	24722	20721	0	0
T5	8493	8086	0	0
T6	422	22	0	0
T7	15140	14724	0	0
T13	507	107	0	0
T14	507	107	0	0
T15	501	101	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	68	0	0
T8	1043	1	0	0
T9	933	2	0	0
T10	47669	0	0	0
T20	0	1	0	0
T21	492	0	0	0
T22	495	0	0	0
T24	0	2	0	0
T32	0	3	0	0
T33	0	2	0	0
T43	644	0	0	0
T49	752	0	0	0
T65	522	0	0	0
T66	430	0	0	0
T67	426	0	0	0
T72	0	1	0	0
T85	0	1	0	0
T86	0	2	0	0
T111	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	65	0	0
T8	1043	1	0	0
T9	933	1	0	0
T10	47669	0	0	0
T20	0	1	0	0
T21	492	0	0	0
T22	495	0	0	0
T24	0	2	0	0
T32	0	3	0	0
T33	0	2	0	0
T43	644	0	0	0
T49	752	0	0	0
T65	522	0	0	0
T66	430	0	0	0
T67	426	0	0	0
T72	0	1	0	0
T85	0	1	0	0
T86	0	2	0	0
T111	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	64	0	0
T8	1043	1	0	0
T9	933	1	0	0
T10	47669	0	0	0
T20	0	1	0	0
T21	492	0	0	0
T22	495	0	0	0
T24	0	1	0	0
T32	0	3	0	0
T33	0	2	0	0
T43	644	0	0	0
T49	752	0	0	0
T65	522	0	0	0
T66	430	0	0	0
T67	426	0	0	0
T72	0	1	0	0
T85	0	1	0	0
T86	0	2	0	0
T111	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	64	0	0
T8	1043	1	0	0
T9	933	1	0	0
T10	47669	0	0	0
T20	0	1	0	0
T21	492	0	0	0
T22	495	0	0	0
T24	0	1	0	0
T32	0	3	0	0
T33	0	2	0	0
T43	644	0	0	0
T49	752	0	0	0
T65	522	0	0	0
T66	430	0	0	0
T67	426	0	0	0
T72	0	1	0	0
T85	0	1	0	0
T86	0	2	0	0
T111	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	73676	0	0
T8	1043	298	0	0
T9	933	37	0	0
T10	47669	0	0	0
T20	0	72	0	0
T21	492	0	0	0
T22	495	0	0	0
T24	0	340	0	0
T32	0	47	0	0
T33	0	211	0	0
T43	644	0	0	0
T49	752	0	0	0
T65	522	0	0	0
T66	430	0	0	0
T67	426	0	0	0
T72	0	149	0	0
T85	0	214	0	0
T86	0	375	0	0
T111	0	268	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	8792903	0	0
T1	26361	25920	0	0
T2	13744	13321	0	0
T3	2057	1657	0	0
T4	24722	20721	0	0
T5	8493	8086	0	0
T6	422	22	0	0
T7	15140	14724	0	0
T13	507	107	0	0
T14	507	107	0	0
T15	501	101	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	40	0	0
T32	0	3	0	0
T33	1104	1	0	0
T38	589	0	0	0
T53	785	0	0	0
T59	495	0	0	0
T72	0	1	0	0
T85	0	1	0	0
T86	0	1	0	0
T91	0	1	0	0
T111	0	1	0	0
T148	0	1	0	0
T196	1047	0	0	0
T197	502	0	0	0
T198	402	0	0	0
T199	522	0	0	0
T211	0	1	0	0
T247	0	1	0	0
T248	502	0	0	0
T249	525	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T9,T33,T32

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T9,T33,T32

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T9,T33,T32

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T36
1	0	Covered	T1,T5,T6
1	1	Covered	T9,T33,T32

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T33,T32
0	1	Covered	T213
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T33,T32
0	1	Covered	T9,T33,T32
1	0	Covered	T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T33,T32
1	-	Covered	T9,T33,T32

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T33,T32
DetectSt	168	Covered	T9,T33,T32
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T9,T33,T32

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T33,T32
DebounceSt->IdleSt	163	Covered	T83,T168
DetectSt->IdleSt	186	Covered	T213
DetectSt->StableSt	191	Covered	T9,T33,T32
IdleSt->DebounceSt	148	Covered	T9,T33,T32
StableSt->IdleSt	206	Covered	T9,T33,T32

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T33,T32
0	1	Covered	T9,T33,T32
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T33,T32
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T33,T32
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T83
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T33,T32
DebounceSt	-	0	1	0	-	-	-	Covered	T168
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T33,T32
DetectSt	-	-	-	-	1	-	-	Covered	T213
DetectSt	-	-	-	-	0	1	-	Covered	T9,T33,T32
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T33,T32
StableSt	-	-	-	-	-	-	0	Covered	T9,T33,T32
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9452567	70	0	0
CntIncr_A	9452567	1504	0	0
CntNoWrap_A	9452567	8790406	0	0
DetectStDropOut_A	9452567	1	0	0
DetectedOut_A	9452567	3019	0	0
DetectedPulseOut_A	9452567	33	0	0
DisabledIdleSt_A	9452567	8640824	0	0
DisabledNoDetection_A	9452567	8643201	0	0
EnterDebounceSt_A	9452567	36	0	0
EnterDetectSt_A	9452567	34	0	0
EnterStableSt_A	9452567	33	0	0
PulseIsPulse_A	9452567	33	0	0
StayInStableSt	9452567	2965	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9452567	7172	0	0
gen_low_level_sva.LowLevelEvent_A	9452567	8792903	0	0
gen_not_sticky_sva.StableStDropOut_A	9452567	11	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	70	0	0
T9	933	2	0	0
T10	47669	0	0	0
T11	33091	0	0	0
T22	495	0	0	0
T32	0	8	0	0
T33	0	2	0	0
T35	0	2	0	0
T49	752	0	0	0
T65	522	0	0	0
T66	430	0	0	0
T67	426	0	0	0
T68	525	0	0	0
T69	529	0	0	0
T78	0	2	0	0
T85	0	2	0	0
T86	0	2	0	0
T90	0	2	0	0
T111	0	2	0	0
T191	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	1504	0	0
T9	933	94	0	0
T10	47669	0	0	0
T11	33091	0	0	0
T22	495	0	0	0
T32	0	92	0	0
T33	0	99	0	0
T35	0	90	0	0
T49	752	0	0	0
T65	522	0	0	0
T66	430	0	0	0
T67	426	0	0	0
T68	525	0	0	0
T69	529	0	0	0
T78	0	29	0	0
T85	0	85	0	0
T86	0	70	0	0
T90	0	12	0	0
T111	0	87	0	0
T191	0	86	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	8790406	0	0
T1	26361	25911	0	0
T2	13744	13317	0	0
T3	2057	1656	0	0
T4	24722	20703	0	0
T5	8493	8083	0	0
T6	422	21	0	0
T7	15140	14720	0	0
T13	507	106	0	0
T14	507	106	0	0
T15	501	100	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	1	0	0
T213	283736	1	0	0
T214	695	0	0	0
T250	12320	0	0	0
T251	502	0	0	0
T252	688	0	0	0
T253	2067	0	0	0
T254	607	0	0	0
T255	522	0	0	0
T256	409	0	0	0
T257	10067	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	3019	0	0
T9	933	201	0	0
T10	47669	0	0	0
T11	33091	0	0	0
T22	495	0	0	0
T32	0	380	0	0
T33	0	55	0	0
T35	0	44	0	0
T49	752	0	0	0
T65	522	0	0	0
T66	430	0	0	0
T67	426	0	0	0
T68	525	0	0	0
T69	529	0	0	0
T78	0	167	0	0
T85	0	44	0	0
T86	0	369	0	0
T90	0	63	0	0
T111	0	79	0	0
T191	0	244	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	33	0	0
T9	933	1	0	0
T10	47669	0	0	0
T11	33091	0	0	0
T22	495	0	0	0
T32	0	4	0	0
T33	0	1	0	0
T35	0	1	0	0
T49	752	0	0	0
T65	522	0	0	0
T66	430	0	0	0
T67	426	0	0	0
T68	525	0	0	0
T69	529	0	0	0
T78	0	1	0	0
T85	0	1	0	0
T86	0	1	0	0
T90	0	1	0	0
T111	0	1	0	0
T191	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	8640824	0	0
T1	26361	25911	0	0
T2	13744	13317	0	0
T3	2057	1656	0	0
T4	24722	20703	0	0
T5	8493	8083	0	0
T6	422	21	0	0
T7	15140	14720	0	0
T13	507	106	0	0
T14	507	106	0	0
T15	501	100	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	8643201	0	0
T1	26361	25920	0	0
T2	13744	13321	0	0
T3	2057	1657	0	0
T4	24722	20721	0	0
T5	8493	8086	0	0
T6	422	22	0	0
T7	15140	14724	0	0
T13	507	107	0	0
T14	507	107	0	0
T15	501	101	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	36	0	0
T9	933	1	0	0
T10	47669	0	0	0
T11	33091	0	0	0
T22	495	0	0	0
T32	0	4	0	0
T33	0	1	0	0
T35	0	1	0	0
T49	752	0	0	0
T65	522	0	0	0
T66	430	0	0	0
T67	426	0	0	0
T68	525	0	0	0
T69	529	0	0	0
T78	0	1	0	0
T85	0	1	0	0
T86	0	1	0	0
T90	0	1	0	0
T111	0	1	0	0
T191	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	34	0	0
T9	933	1	0	0
T10	47669	0	0	0
T11	33091	0	0	0
T22	495	0	0	0
T32	0	4	0	0
T33	0	1	0	0
T35	0	1	0	0
T49	752	0	0	0
T65	522	0	0	0
T66	430	0	0	0
T67	426	0	0	0
T68	525	0	0	0
T69	529	0	0	0
T78	0	1	0	0
T85	0	1	0	0
T86	0	1	0	0
T90	0	1	0	0
T111	0	1	0	0
T191	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	33	0	0
T9	933	1	0	0
T10	47669	0	0	0
T11	33091	0	0	0
T22	495	0	0	0
T32	0	4	0	0
T33	0	1	0	0
T35	0	1	0	0
T49	752	0	0	0
T65	522	0	0	0
T66	430	0	0	0
T67	426	0	0	0
T68	525	0	0	0
T69	529	0	0	0
T78	0	1	0	0
T85	0	1	0	0
T86	0	1	0	0
T90	0	1	0	0
T111	0	1	0	0
T191	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	33	0	0
T9	933	1	0	0
T10	47669	0	0	0
T11	33091	0	0	0
T22	495	0	0	0
T32	0	4	0	0
T33	0	1	0	0
T35	0	1	0	0
T49	752	0	0	0
T65	522	0	0	0
T66	430	0	0	0
T67	426	0	0	0
T68	525	0	0	0
T69	529	0	0	0
T78	0	1	0	0
T85	0	1	0	0
T86	0	1	0	0
T90	0	1	0	0
T111	0	1	0	0
T191	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	2965	0	0
T9	933	200	0	0
T10	47669	0	0	0
T11	33091	0	0	0
T22	495	0	0	0
T32	0	373	0	0
T33	0	54	0	0
T35	0	43	0	0
T49	752	0	0	0
T65	522	0	0	0
T66	430	0	0	0
T67	426	0	0	0
T68	525	0	0	0
T69	529	0	0	0
T78	0	165	0	0
T85	0	42	0	0
T86	0	367	0	0
T90	0	61	0	0
T111	0	78	0	0
T191	0	241	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	7172	0	0
T1	26361	11	0	0
T2	13744	12	0	0
T3	2057	9	0	0
T4	24722	17	0	0
T5	8493	12	0	0
T6	422	3	0	0
T7	15140	32	0	0
T13	507	6	0	0
T14	507	5	0	0
T15	501	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	8792903	0	0
T1	26361	25920	0	0
T2	13744	13321	0	0
T3	2057	1657	0	0
T4	24722	20721	0	0
T5	8493	8086	0	0
T6	422	22	0	0
T7	15140	14724	0	0
T13	507	107	0	0
T14	507	107	0	0
T15	501	101	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	11	0	0
T9	933	1	0	0
T10	47669	0	0	0
T11	33091	0	0	0
T22	495	0	0	0
T32	0	1	0	0
T33	0	1	0	0
T35	0	1	0	0
T49	752	0	0	0
T65	522	0	0	0
T66	430	0	0	0
T67	426	0	0	0
T68	525	0	0	0
T69	529	0	0	0
T111	0	1	0	0
T133	0	1	0	0
T162	0	1	0	0
T191	0	1	0	0
T224	0	1	0	0
T258	0	1	0	0