Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T7,T27,T11
1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T7,T27,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T7,T27,T11

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T7,T27,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T27,T11
1	0	Covered	T7,T11,T42
1	1	Covered	T7,T27,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T27,T11
0	1	Covered	T7,T27,T42
1	0	Covered	T7,T42,T41

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T39,T40
0	1	Covered	T11,T39,T40
1	0	Covered	T83,T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T39,T40
1	-	Covered	T11,T39,T40

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T27,T11
DetectSt	168	Covered	T7,T27,T11
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T11,T39,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T27,T11
DebounceSt->IdleSt	163	Covered	T83,T259,T50
DetectSt->IdleSt	186	Covered	T7,T27,T42
DetectSt->StableSt	191	Covered	T11,T39,T40
IdleSt->DebounceSt	148	Covered	T7,T27,T11
StableSt->IdleSt	206	Covered	T11,T39,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T7,T27,T11
0	1	Covered	T7,T27,T11
0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T27,T11
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T7,T27,T11
IdleSt	0	-	-	-	-	-	-	Covered	T7,T27,T11
DebounceSt	-	1	-	-	-	-	-	Covered	T83,T50
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T27,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T83,T259,T50
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T27,T11
DetectSt	-	-	-	-	1	-	-	Covered	T7,T27,T42
DetectSt	-	-	-	-	0	1	-	Covered	T11,T39,T40
DetectSt	-	-	-	-	0	0	-	Covered	T7,T27,T11
StableSt	-	-	-	-	-	-	1	Covered	T11,T39,T40
StableSt	-	-	-	-	-	-	0	Covered	T11,T39,T40
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9452567	3040	0	0
CntIncr_A	9452567	102537	0	0
CntNoWrap_A	9452567	8787436	0	0
DetectStDropOut_A	9452567	360	0	0
DetectedOut_A	9452567	80627	0	0
DetectedPulseOut_A	9452567	970	0	0
DisabledIdleSt_A	9452567	8324126	0	0
DisabledNoDetection_A	9452567	8326360	0	0
EnterDebounceSt_A	9452567	1527	0	0
EnterDetectSt_A	9452567	1514	0	0
EnterStableSt_A	9452567	970	0	0
PulseIsPulse_A	9452567	970	0	0
StayInStableSt	9452567	79561	0	0
gen_high_event_sva.HighLevelEvent_A	9452567	8792903	0	0
gen_high_level_sva.HighLevelEvent_A	9452567	8792903	0	0
gen_not_sticky_sva.StableStDropOut_A	9452567	872	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	3040	0	0
T7	15140	22	0	0
T8	1043	0	0	0
T9	933	0	0	0
T11	0	20	0	0
T21	492	0	0	0
T25	686	0	0	0
T26	618	0	0	0
T27	5516	34	0	0
T39	0	46	0	0
T40	0	20	0	0
T41	0	22	0	0
T42	0	48	0	0
T43	644	0	0	0
T47	523	0	0	0
T48	761	0	0	0
T73	0	28	0	0
T74	0	10	0	0
T75	0	8	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	102537	0	0
T7	15140	960	0	0
T8	1043	0	0	0
T9	933	0	0	0
T11	0	620	0	0
T21	492	0	0	0
T25	686	0	0	0
T26	618	0	0	0
T27	5516	972	0	0
T39	0	2093	0	0
T40	0	710	0	0
T41	0	592	0	0
T42	0	1421	0	0
T43	644	0	0	0
T47	523	0	0	0
T48	761	0	0	0
T73	0	708	0	0
T74	0	317	0	0
T75	0	177	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	8787436	0	0
T1	26361	25911	0	0
T2	13744	13317	0	0
T3	2057	1656	0	0
T4	24722	20703	0	0
T5	8493	8083	0	0
T6	422	21	0	0
T7	15140	14698	0	0
T13	507	106	0	0
T14	507	106	0	0
T15	501	100	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	360	0	0
T7	15140	6	0	0
T8	1043	0	0	0
T9	933	0	0	0
T21	492	0	0	0
T25	686	0	0	0
T26	618	0	0	0
T27	5516	17	0	0
T42	0	11	0	0
T43	644	0	0	0
T47	523	0	0	0
T48	761	0	0	0
T73	0	14	0	0
T74	0	2	0	0
T75	0	4	0	0
T97	0	25	0	0
T98	0	2	0	0
T99	0	4	0	0
T260	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	80627	0	0
T11	33091	1394	0	0
T12	28214	0	0	0
T24	970	0	0	0
T31	775	0	0	0
T39	0	2587	0	0
T40	0	358	0	0
T42	6812	0	0	0
T68	525	0	0	0
T69	529	0	0	0
T70	505	0	0	0
T117	0	1243	0	0
T118	0	2930	0	0
T119	758	0	0	0
T127	0	4266	0	0
T233	0	1569	0	0
T261	0	813	0	0
T262	0	1533	0	0
T263	0	453	0	0
T264	406	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	970	0	0
T11	33091	10	0	0
T12	28214	0	0	0
T24	970	0	0	0
T31	775	0	0	0
T39	0	23	0	0
T40	0	10	0	0
T42	6812	0	0	0
T68	525	0	0	0
T69	529	0	0	0
T70	505	0	0	0
T117	0	22	0	0
T118	0	31	0	0
T119	758	0	0	0
T127	0	24	0	0
T233	0	27	0	0
T261	0	22	0	0
T262	0	25	0	0
T263	0	8	0	0
T264	406	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	8324126	0	0
T1	26361	25911	0	0
T2	13744	13317	0	0
T3	2057	1656	0	0
T4	24722	20703	0	0
T5	8493	8083	0	0
T6	422	21	0	0
T7	15140	10162	0	0
T13	507	106	0	0
T14	507	106	0	0
T15	501	100	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	8326360	0	0
T1	26361	25920	0	0
T2	13744	13321	0	0
T3	2057	1657	0	0
T4	24722	20721	0	0
T5	8493	8086	0	0
T6	422	22	0	0
T7	15140	10165	0	0
T13	507	107	0	0
T14	507	107	0	0
T15	501	101	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	1527	0	0
T7	15140	11	0	0
T8	1043	0	0	0
T9	933	0	0	0
T11	0	10	0	0
T21	492	0	0	0
T25	686	0	0	0
T26	618	0	0	0
T27	5516	17	0	0
T39	0	23	0	0
T40	0	10	0	0
T41	0	11	0	0
T42	0	24	0	0
T43	644	0	0	0
T47	523	0	0	0
T48	761	0	0	0
T73	0	14	0	0
T74	0	5	0	0
T75	0	4	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	1514	0	0
T7	15140	11	0	0
T8	1043	0	0	0
T9	933	0	0	0
T11	0	10	0	0
T21	492	0	0	0
T25	686	0	0	0
T26	618	0	0	0
T27	5516	17	0	0
T39	0	23	0	0
T40	0	10	0	0
T41	0	11	0	0
T42	0	24	0	0
T43	644	0	0	0
T47	523	0	0	0
T48	761	0	0	0
T73	0	14	0	0
T74	0	5	0	0
T75	0	4	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	970	0	0
T11	33091	10	0	0
T12	28214	0	0	0
T24	970	0	0	0
T31	775	0	0	0
T39	0	23	0	0
T40	0	10	0	0
T42	6812	0	0	0
T68	525	0	0	0
T69	529	0	0	0
T70	505	0	0	0
T117	0	22	0	0
T118	0	31	0	0
T119	758	0	0	0
T127	0	24	0	0
T233	0	27	0	0
T261	0	22	0	0
T262	0	25	0	0
T263	0	8	0	0
T264	406	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	970	0	0
T11	33091	10	0	0
T12	28214	0	0	0
T24	970	0	0	0
T31	775	0	0	0
T39	0	23	0	0
T40	0	10	0	0
T42	6812	0	0	0
T68	525	0	0	0
T69	529	0	0	0
T70	505	0	0	0
T117	0	22	0	0
T118	0	31	0	0
T119	758	0	0	0
T127	0	24	0	0
T233	0	27	0	0
T261	0	22	0	0
T262	0	25	0	0
T263	0	8	0	0
T264	406	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	79561	0	0
T11	33091	1379	0	0
T12	28214	0	0	0
T24	970	0	0	0
T31	775	0	0	0
T39	0	2558	0	0
T40	0	347	0	0
T42	6812	0	0	0
T68	525	0	0	0
T69	529	0	0	0
T70	505	0	0	0
T117	0	1221	0	0
T118	0	2895	0	0
T119	758	0	0	0
T127	0	4237	0	0
T233	0	1542	0	0
T261	0	791	0	0
T262	0	1505	0	0
T263	0	445	0	0
T264	406	0	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	8792903	0	0
T1	26361	25920	0	0
T2	13744	13321	0	0
T3	2057	1657	0	0
T4	24722	20721	0	0
T5	8493	8086	0	0
T6	422	22	0	0
T7	15140	14724	0	0
T13	507	107	0	0
T14	507	107	0	0
T15	501	101	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	8792903	0	0
T1	26361	25920	0	0
T2	13744	13321	0	0
T3	2057	1657	0	0
T4	24722	20721	0	0
T5	8493	8086	0	0
T6	422	22	0	0
T7	15140	14724	0	0
T13	507	107	0	0
T14	507	107	0	0
T15	501	101	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	872	0	0
T11	33091	5	0	0
T12	28214	0	0	0
T24	970	0	0	0
T31	775	0	0	0
T39	0	17	0	0
T40	0	9	0	0
T42	6812	0	0	0
T68	525	0	0	0
T69	529	0	0	0
T70	505	0	0	0
T117	0	22	0	0
T118	0	27	0	0
T119	758	0	0	0
T127	0	19	0	0
T233	0	27	0	0
T261	0	22	0	0
T262	0	22	0	0
T263	0	8	0	0
T264	406	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T2
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T2

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T1,T5,T2

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T2

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Covered	T5,T10,T78
1	0	Covered	T83,T50

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T2,T4
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T4
1	-	Covered	T1,T2,T4

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T5,T2
DetectSt	168	Covered	T1,T5,T2
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T1,T2,T4

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T5,T2
DebounceSt->IdleSt	163	Covered	T1,T2,T10
DetectSt->IdleSt	186	Covered	T5,T10,T55
DetectSt->StableSt	191	Covered	T1,T2,T4
IdleSt->DebounceSt	148	Covered	T1,T5,T2
StableSt->IdleSt	206	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T5,T2
0	1	Covered	T1,T5,T2
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T2
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T5,T2
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T83,T50
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T5,T2
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T2,T10
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T5,T2
DetectSt	-	-	-	-	1	-	-	Covered	T5,T10,T78
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T4
DetectSt	-	-	-	-	0	0	-	Covered	T1,T5,T2
StableSt	-	-	-	-	-	-	1	Covered	T1,T2,T4
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T4
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9452567	899	0	0
CntIncr_A	9452567	46033	0	0
CntNoWrap_A	9452567	8789577	0	0
DetectStDropOut_A	9452567	56	0	0
DetectedOut_A	9452567	18752	0	0
DetectedPulseOut_A	9452567	348	0	0
DisabledIdleSt_A	9452567	8388807	0	0
DisabledNoDetection_A	9452567	8390492	0	0
EnterDebounceSt_A	9452567	492	0	0
EnterDetectSt_A	9452567	409	0	0
EnterStableSt_A	9452567	348	0	0
PulseIsPulse_A	9452567	348	0	0
StayInStableSt	9452567	18379	0	0
gen_high_level_sva.HighLevelEvent_A	9452567	8792903	0	0
gen_not_sticky_sva.StableStDropOut_A	9452567	320	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	899	0	0
T1	26361	5	0	0
T2	13744	11	0	0
T3	2057	0	0	0
T4	24722	14	0	0
T5	8493	4	0	0
T6	422	0	0	0
T7	15140	0	0	0
T10	0	28	0	0
T11	0	8	0	0
T12	0	4	0	0
T13	507	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T39	0	8	0	0
T52	0	8	0	0
T95	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	46033	0	0
T1	26361	896	0	0
T2	13744	627	0	0
T3	2057	0	0	0
T4	24722	728	0	0
T5	8493	149	0	0
T6	422	0	0	0
T7	15140	0	0	0
T10	0	1740	0	0
T11	0	232	0	0
T12	0	152	0	0
T13	507	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T39	0	368	0	0
T52	0	420	0	0
T95	0	444	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	8789577	0	0
T1	26361	25906	0	0
T2	13744	13306	0	0
T3	2057	1656	0	0
T4	24722	20689	0	0
T5	8493	8079	0	0
T6	422	21	0	0
T7	15140	14720	0	0
T13	507	106	0	0
T14	507	106	0	0
T15	501	100	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	56	0	0
T2	13744	0	0	0
T3	2057	0	0	0
T4	24722	0	0	0
T5	8493	2	0	0
T6	422	0	0	0
T7	15140	0	0	0
T10	0	3	0	0
T13	507	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T27	5516	0	0	0
T78	0	2	0	0
T100	0	5	0	0
T101	0	8	0	0
T102	0	3	0	0
T103	0	4	0	0
T104	0	9	0	0
T105	0	5	0	0
T106	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	18752	0	0
T1	26361	39	0	0
T2	13744	433	0	0
T3	2057	0	0	0
T4	24722	447	0	0
T5	8493	0	0	0
T6	422	0	0	0
T7	15140	0	0	0
T10	0	523	0	0
T11	0	264	0	0
T12	0	106	0	0
T13	507	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T39	0	169	0	0
T40	0	63	0	0
T52	0	279	0	0
T95	0	96	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	348	0	0
T1	26361	2	0	0
T2	13744	5	0	0
T3	2057	0	0	0
T4	24722	7	0	0
T5	8493	0	0	0
T6	422	0	0	0
T7	15140	0	0	0
T10	0	10	0	0
T11	0	4	0	0
T12	0	2	0	0
T13	507	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T39	0	4	0	0
T40	0	1	0	0
T52	0	4	0	0
T95	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	8388807	0	0
T1	26361	18130	0	0
T2	13744	8058	0	0
T3	2057	1656	0	0
T4	24722	17786	0	0
T5	8493	6045	0	0
T6	422	21	0	0
T7	15140	14720	0	0
T13	507	106	0	0
T14	507	106	0	0
T15	501	100	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	8390492	0	0
T1	26361	18130	0	0
T2	13744	8058	0	0
T3	2057	1657	0	0
T4	24722	17797	0	0
T5	8493	6045	0	0
T6	422	22	0	0
T7	15140	14724	0	0
T13	507	107	0	0
T14	507	107	0	0
T15	501	101	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	492	0	0
T1	26361	3	0	0
T2	13744	6	0	0
T3	2057	0	0	0
T4	24722	7	0	0
T5	8493	2	0	0
T6	422	0	0	0
T7	15140	0	0	0
T10	0	15	0	0
T11	0	4	0	0
T12	0	2	0	0
T13	507	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T39	0	4	0	0
T52	0	4	0	0
T95	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	409	0	0
T1	26361	2	0	0
T2	13744	5	0	0
T3	2057	0	0	0
T4	24722	7	0	0
T5	8493	2	0	0
T6	422	0	0	0
T7	15140	0	0	0
T10	0	13	0	0
T11	0	4	0	0
T12	0	2	0	0
T13	507	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T39	0	4	0	0
T52	0	4	0	0
T95	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	348	0	0
T1	26361	2	0	0
T2	13744	5	0	0
T3	2057	0	0	0
T4	24722	7	0	0
T5	8493	0	0	0
T6	422	0	0	0
T7	15140	0	0	0
T10	0	10	0	0
T11	0	4	0	0
T12	0	2	0	0
T13	507	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T39	0	4	0	0
T40	0	1	0	0
T52	0	4	0	0
T95	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	348	0	0
T1	26361	2	0	0
T2	13744	5	0	0
T3	2057	0	0	0
T4	24722	7	0	0
T5	8493	0	0	0
T6	422	0	0	0
T7	15140	0	0	0
T10	0	10	0	0
T11	0	4	0	0
T12	0	2	0	0
T13	507	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T39	0	4	0	0
T40	0	1	0	0
T52	0	4	0	0
T95	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	18379	0	0
T1	26361	37	0	0
T2	13744	428	0	0
T3	2057	0	0	0
T4	24722	440	0	0
T5	8493	0	0	0
T6	422	0	0	0
T7	15140	0	0	0
T10	0	513	0	0
T11	0	260	0	0
T12	0	104	0	0
T13	507	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T39	0	161	0	0
T40	0	62	0	0
T52	0	275	0	0
T95	0	93	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	8792903	0	0
T1	26361	25920	0	0
T2	13744	13321	0	0
T3	2057	1657	0	0
T4	24722	20721	0	0
T5	8493	8086	0	0
T6	422	22	0	0
T7	15140	14724	0	0
T13	507	107	0	0
T14	507	107	0	0
T15	501	101	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	320	0	0
T1	26361	2	0	0
T2	13744	5	0	0
T3	2057	0	0	0
T4	24722	7	0	0
T5	8493	0	0	0
T6	422	0	0	0
T7	15140	0	0	0
T10	0	10	0	0
T11	0	4	0	0
T12	0	2	0	0
T13	507	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T32	0	6	0	0
T40	0	1	0	0
T52	0	4	0	0
T95	0	3	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T7,T27,T11
1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T7,T27,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T7,T27,T11

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T7,T27,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T27,T11
1	0	Covered	T7,T11,T42
1	1	Covered	T7,T27,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T27,T11
0	1	Covered	T27,T42,T73
1	0	Covered	T42,T74,T98

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T11,T41
0	1	Covered	T7,T11,T41
1	0	Covered	T89,T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T11,T41
1	-	Covered	T7,T11,T41

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T27,T11
DetectSt	168	Covered	T7,T27,T11
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T7,T11,T41

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T27,T11
DebounceSt->IdleSt	163	Covered	T83,T259,T50
DetectSt->IdleSt	186	Covered	T27,T42,T73
DetectSt->StableSt	191	Covered	T7,T11,T41
IdleSt->DebounceSt	148	Covered	T7,T27,T11
StableSt->IdleSt	206	Covered	T7,T11,T41

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T7,T27,T11
0	1	Covered	T7,T27,T11
0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T27,T11
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T7,T27,T11
IdleSt	0	-	-	-	-	-	-	Covered	T7,T27,T11
DebounceSt	-	1	-	-	-	-	-	Covered	T83,T50
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T27,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T83,T259,T50
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T27,T11
DetectSt	-	-	-	-	1	-	-	Covered	T27,T42,T73
DetectSt	-	-	-	-	0	1	-	Covered	T7,T11,T41
DetectSt	-	-	-	-	0	0	-	Covered	T7,T27,T11
StableSt	-	-	-	-	-	-	1	Covered	T7,T11,T41
StableSt	-	-	-	-	-	-	0	Covered	T7,T11,T41
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9452567	3217	0	0
CntIncr_A	9452567	105566	0	0
CntNoWrap_A	9452567	8787259	0	0
DetectStDropOut_A	9452567	421	0	0
DetectedOut_A	9452567	82615	0	0
DetectedPulseOut_A	9452567	888	0	0
DisabledIdleSt_A	9452567	8325515	0	0
DisabledNoDetection_A	9452567	8327742	0	0
EnterDebounceSt_A	9452567	1613	0	0
EnterDetectSt_A	9452567	1604	0	0
EnterStableSt_A	9452567	888	0	0
PulseIsPulse_A	9452567	888	0	0
StayInStableSt	9452567	81623	0	0
gen_high_event_sva.HighLevelEvent_A	9452567	8792903	0	0
gen_high_level_sva.HighLevelEvent_A	9452567	8792903	0	0
gen_not_sticky_sva.StableStDropOut_A	9452567	781	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	3217	0	0
T7	15140	16	0	0
T8	1043	0	0	0
T9	933	0	0	0
T11	0	12	0	0
T21	492	0	0	0
T25	686	0	0	0
T26	618	0	0	0
T27	5516	24	0	0
T39	0	24	0	0
T40	0	56	0	0
T41	0	48	0	0
T42	0	24	0	0
T43	644	0	0	0
T47	523	0	0	0
T48	761	0	0	0
T73	0	12	0	0
T74	0	58	0	0
T75	0	16	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	105566	0	0
T7	15140	656	0	0
T8	1043	0	0	0
T9	933	0	0	0
T11	0	330	0	0
T21	492	0	0	0
T25	686	0	0	0
T26	618	0	0	0
T27	5516	690	0	0
T39	0	828	0	0
T40	0	1680	0	0
T41	0	864	0	0
T42	0	703	0	0
T43	644	0	0	0
T47	523	0	0	0
T48	761	0	0	0
T73	0	301	0	0
T74	0	1835	0	0
T75	0	355	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	8787259	0	0
T1	26361	25911	0	0
T2	13744	13317	0	0
T3	2057	1656	0	0
T4	24722	20703	0	0
T5	8493	8083	0	0
T6	422	21	0	0
T7	15140	14704	0	0
T13	507	106	0	0
T14	507	106	0	0
T15	501	100	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	421	0	0
T8	1043	0	0	0
T9	933	0	0	0
T21	492	0	0	0
T22	495	0	0	0
T25	686	0	0	0
T26	618	0	0	0
T27	5516	12	0	0
T42	0	8	0	0
T43	644	0	0	0
T47	523	0	0	0
T48	761	0	0	0
T73	0	6	0	0
T74	0	22	0	0
T75	0	8	0	0
T97	0	29	0	0
T98	0	5	0	0
T262	0	5	0	0
T265	0	11	0	0
T266	0	5	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	82615	0	0
T7	15140	701	0	0
T8	1043	0	0	0
T9	933	0	0	0
T11	0	724	0	0
T21	492	0	0	0
T25	686	0	0	0
T26	618	0	0	0
T27	5516	0	0	0
T39	0	1225	0	0
T40	0	2258	0	0
T41	0	1544	0	0
T43	644	0	0	0
T47	523	0	0	0
T48	761	0	0	0
T117	0	140	0	0
T118	0	1663	0	0
T233	0	448	0	0
T261	0	1710	0	0
T267	0	2918	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	888	0	0
T7	15140	8	0	0
T8	1043	0	0	0
T9	933	0	0	0
T11	0	6	0	0
T21	492	0	0	0
T25	686	0	0	0
T26	618	0	0	0
T27	5516	0	0	0
T39	0	12	0	0
T40	0	28	0	0
T41	0	24	0	0
T43	644	0	0	0
T47	523	0	0	0
T48	761	0	0	0
T117	0	5	0	0
T118	0	22	0	0
T233	0	9	0	0
T261	0	24	0	0
T267	0	23	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	8325515	0	0
T1	26361	25911	0	0
T2	13744	13317	0	0
T3	2057	1656	0	0
T4	24722	20703	0	0
T5	8493	8083	0	0
T6	422	21	0	0
T7	15140	9497	0	0
T13	507	106	0	0
T14	507	106	0	0
T15	501	100	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	8327742	0	0
T1	26361	25920	0	0
T2	13744	13321	0	0
T3	2057	1657	0	0
T4	24722	20721	0	0
T5	8493	8086	0	0
T6	422	22	0	0
T7	15140	9498	0	0
T13	507	107	0	0
T14	507	107	0	0
T15	501	101	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	1613	0	0
T7	15140	8	0	0
T8	1043	0	0	0
T9	933	0	0	0
T11	0	6	0	0
T21	492	0	0	0
T25	686	0	0	0
T26	618	0	0	0
T27	5516	12	0	0
T39	0	12	0	0
T40	0	28	0	0
T41	0	24	0	0
T42	0	12	0	0
T43	644	0	0	0
T47	523	0	0	0
T48	761	0	0	0
T73	0	6	0	0
T74	0	29	0	0
T75	0	8	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	1604	0	0
T7	15140	8	0	0
T8	1043	0	0	0
T9	933	0	0	0
T11	0	6	0	0
T21	492	0	0	0
T25	686	0	0	0
T26	618	0	0	0
T27	5516	12	0	0
T39	0	12	0	0
T40	0	28	0	0
T41	0	24	0	0
T42	0	12	0	0
T43	644	0	0	0
T47	523	0	0	0
T48	761	0	0	0
T73	0	6	0	0
T74	0	29	0	0
T75	0	8	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	888	0	0
T7	15140	8	0	0
T8	1043	0	0	0
T9	933	0	0	0
T11	0	6	0	0
T21	492	0	0	0
T25	686	0	0	0
T26	618	0	0	0
T27	5516	0	0	0
T39	0	12	0	0
T40	0	28	0	0
T41	0	24	0	0
T43	644	0	0	0
T47	523	0	0	0
T48	761	0	0	0
T117	0	5	0	0
T118	0	22	0	0
T233	0	9	0	0
T261	0	24	0	0
T267	0	23	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	888	0	0
T7	15140	8	0	0
T8	1043	0	0	0
T9	933	0	0	0
T11	0	6	0	0
T21	492	0	0	0
T25	686	0	0	0
T26	618	0	0	0
T27	5516	0	0	0
T39	0	12	0	0
T40	0	28	0	0
T41	0	24	0	0
T43	644	0	0	0
T47	523	0	0	0
T48	761	0	0	0
T117	0	5	0	0
T118	0	22	0	0
T233	0	9	0	0
T261	0	24	0	0
T267	0	23	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	81623	0	0
T7	15140	691	0	0
T8	1043	0	0	0
T9	933	0	0	0
T11	0	714	0	0
T21	492	0	0	0
T25	686	0	0	0
T26	618	0	0	0
T27	5516	0	0	0
T39	0	1209	0	0
T40	0	2228	0	0
T41	0	1520	0	0
T43	644	0	0	0
T47	523	0	0	0
T48	761	0	0	0
T117	0	135	0	0
T118	0	1639	0	0
T233	0	438	0	0
T261	0	1686	0	0
T267	0	2894	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	8792903	0	0
T1	26361	25920	0	0
T2	13744	13321	0	0
T3	2057	1657	0	0
T4	24722	20721	0	0
T5	8493	8086	0	0
T6	422	22	0	0
T7	15140	14724	0	0
T13	507	107	0	0
T14	507	107	0	0
T15	501	101	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	8792903	0	0
T1	26361	25920	0	0
T2	13744	13321	0	0
T3	2057	1657	0	0
T4	24722	20721	0	0
T5	8493	8086	0	0
T6	422	22	0	0
T7	15140	14724	0	0
T13	507	107	0	0
T14	507	107	0	0
T15	501	101	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	781	0	0
T7	15140	6	0	0
T8	1043	0	0	0
T9	933	0	0	0
T11	0	2	0	0
T21	492	0	0	0
T25	686	0	0	0
T26	618	0	0	0
T27	5516	0	0	0
T39	0	8	0	0
T40	0	26	0	0
T41	0	24	0	0
T43	644	0	0	0
T47	523	0	0	0
T48	761	0	0	0
T117	0	5	0	0
T118	0	20	0	0
T233	0	8	0	0
T261	0	24	0	0
T267	0	22	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T2
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T2

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T1,T5,T2

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T2

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Covered	T129,T268,T269
1	0	Covered	T83

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Covered	T1,T5,T2
1	0	Covered	T83,T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T5,T2
1	-	Covered	T1,T5,T2

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T5,T2
DetectSt	168	Covered	T1,T5,T2
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T1,T5,T2

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T5,T2
DebounceSt->IdleSt	163	Covered	T1,T10,T12
DetectSt->IdleSt	186	Covered	T55,T129,T268
DetectSt->StableSt	191	Covered	T1,T5,T2
IdleSt->DebounceSt	148	Covered	T1,T5,T2
StableSt->IdleSt	206	Covered	T1,T5,T2

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T5,T2
0	1	Covered	T1,T5,T2
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T2
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T5,T2
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T83,T50
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T5,T2
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T10,T12
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T5,T2
DetectSt	-	-	-	-	1	-	-	Covered	T129,T268,T269
DetectSt	-	-	-	-	0	1	-	Covered	T1,T5,T2
DetectSt	-	-	-	-	0	0	-	Covered	T1,T5,T2
StableSt	-	-	-	-	-	-	1	Covered	T1,T5,T2
StableSt	-	-	-	-	-	-	0	Covered	T1,T5,T2
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9452567	985	0	0
CntIncr_A	9452567	58366	0	0
CntNoWrap_A	9452567	8789491	0	0
DetectStDropOut_A	9452567	68	0	0
DetectedOut_A	9452567	17996	0	0
DetectedPulseOut_A	9452567	396	0	0
DisabledIdleSt_A	9452567	8371332	0	0
DisabledNoDetection_A	9452567	8373028	0	0
EnterDebounceSt_A	9452567	519	0	0
EnterDetectSt_A	9452567	468	0	0
EnterStableSt_A	9452567	396	0	0
PulseIsPulse_A	9452567	396	0	0
StayInStableSt	9452567	17562	0	0
gen_high_level_sva.HighLevelEvent_A	9452567	8792903	0	0
gen_not_sticky_sva.StableStDropOut_A	9452567	356	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	985	0	0
T1	26361	5	0	0
T2	13744	6	0	0
T3	2057	0	0	0
T4	24722	6	0	0
T5	8493	4	0	0
T6	422	0	0	0
T7	15140	4	0	0
T10	0	10	0	0
T11	0	6	0	0
T12	0	21	0	0
T13	507	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T52	0	17	0	0
T95	0	9	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	58366	0	0
T1	26361	894	0	0
T2	13744	552	0	0
T3	2057	0	0	0
T4	24722	360	0	0
T5	8493	140	0	0
T6	422	0	0	0
T7	15140	188	0	0
T10	0	688	0	0
T11	0	174	0	0
T12	0	1223	0	0
T13	507	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T52	0	880	0	0
T95	0	787	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	8789491	0	0
T1	26361	25906	0	0
T2	13744	13311	0	0
T3	2057	1656	0	0
T4	24722	20697	0	0
T5	8493	8079	0	0
T6	422	21	0	0
T7	15140	14716	0	0
T13	507	106	0	0
T14	507	106	0	0
T15	501	100	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	68	0	0
T34	45230	0	0	0
T85	11288	0	0	0
T94	0	2	0	0
T101	0	15	0	0
T129	22371	4	0	0
T130	16012	0	0	0
T131	440	0	0	0
T132	522	0	0	0
T151	0	2	0	0
T262	12934	0	0	0
T268	0	7	0	0
T269	0	2	0	0
T270	0	4	0	0
T271	0	11	0	0
T272	0	1	0	0
T273	0	2	0	0
T274	718	0	0	0
T275	462	0	0	0
T276	406	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	17996	0	0
T1	26361	41	0	0
T2	13744	27	0	0
T3	2057	0	0	0
T4	24722	143	0	0
T5	8493	8	0	0
T6	422	0	0	0
T7	15140	121	0	0
T10	0	71	0	0
T11	0	193	0	0
T12	0	144	0	0
T13	507	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T52	0	550	0	0
T95	0	23	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	396	0	0
T1	26361	2	0	0
T2	13744	3	0	0
T3	2057	0	0	0
T4	24722	3	0	0
T5	8493	2	0	0
T6	422	0	0	0
T7	15140	2	0	0
T10	0	4	0	0
T11	0	3	0	0
T12	0	10	0	0
T13	507	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T52	0	8	0	0
T95	0	4	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	8371332	0	0
T1	26361	18130	0	0
T2	13744	8058	0	0
T3	2057	1656	0	0
T4	24722	17786	0	0
T5	8493	6045	0	0
T6	422	21	0	0
T7	15140	14021	0	0
T13	507	106	0	0
T14	507	106	0	0
T15	501	100	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	8373028	0	0
T1	26361	18130	0	0
T2	13744	8058	0	0
T3	2057	1657	0	0
T4	24722	17797	0	0
T5	8493	6045	0	0
T6	422	22	0	0
T7	15140	14023	0	0
T13	507	107	0	0
T14	507	107	0	0
T15	501	101	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	519	0	0
T1	26361	3	0	0
T2	13744	3	0	0
T3	2057	0	0	0
T4	24722	3	0	0
T5	8493	2	0	0
T6	422	0	0	0
T7	15140	2	0	0
T10	0	6	0	0
T11	0	3	0	0
T12	0	11	0	0
T13	507	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T52	0	9	0	0
T95	0	5	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	468	0	0
T1	26361	2	0	0
T2	13744	3	0	0
T3	2057	0	0	0
T4	24722	3	0	0
T5	8493	2	0	0
T6	422	0	0	0
T7	15140	2	0	0
T10	0	4	0	0
T11	0	3	0	0
T12	0	10	0	0
T13	507	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T52	0	8	0	0
T95	0	4	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	396	0	0
T1	26361	2	0	0
T2	13744	3	0	0
T3	2057	0	0	0
T4	24722	3	0	0
T5	8493	2	0	0
T6	422	0	0	0
T7	15140	2	0	0
T10	0	4	0	0
T11	0	3	0	0
T12	0	10	0	0
T13	507	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T52	0	8	0	0
T95	0	4	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	396	0	0
T1	26361	2	0	0
T2	13744	3	0	0
T3	2057	0	0	0
T4	24722	3	0	0
T5	8493	2	0	0
T6	422	0	0	0
T7	15140	2	0	0
T10	0	4	0	0
T11	0	3	0	0
T12	0	10	0	0
T13	507	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T52	0	8	0	0
T95	0	4	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	17562	0	0
T1	26361	39	0	0
T2	13744	24	0	0
T3	2057	0	0	0
T4	24722	140	0	0
T5	8493	6	0	0
T6	422	0	0	0
T7	15140	119	0	0
T10	0	67	0	0
T11	0	187	0	0
T12	0	134	0	0
T13	507	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T52	0	542	0	0
T95	0	19	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	8792903	0	0
T1	26361	25920	0	0
T2	13744	13321	0	0
T3	2057	1657	0	0
T4	24722	20721	0	0
T5	8493	8086	0	0
T6	422	22	0	0
T7	15140	14724	0	0
T13	507	107	0	0
T14	507	107	0	0
T15	501	101	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	356	0	0
T1	26361	2	0	0
T2	13744	3	0	0
T3	2057	0	0	0
T4	24722	3	0	0
T5	8493	2	0	0
T6	422	0	0	0
T7	15140	2	0	0
T10	0	4	0	0
T12	0	10	0	0
T13	507	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T40	0	1	0	0
T52	0	8	0	0
T95	0	4	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T7,T27,T11
1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T7,T27,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T7,T27,T11

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T7,T27,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T27,T11
1	0	Covered	T7,T11,T42
1	1	Covered	T7,T27,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T27,T11
0	1	Covered	T27,T42,T73
1	0	Covered	T42,T262,T233

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T11,T41
0	1	Covered	T7,T11,T41
1	0	Covered	T88

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T11,T41
1	-	Covered	T7,T11,T41

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T27,T11
DetectSt	168	Covered	T7,T27,T11
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T7,T11,T41

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T27,T11
DebounceSt->IdleSt	163	Covered	T83,T259,T50
DetectSt->IdleSt	186	Covered	T27,T42,T73
DetectSt->StableSt	191	Covered	T7,T11,T41
IdleSt->DebounceSt	148	Covered	T7,T27,T11
StableSt->IdleSt	206	Covered	T7,T11,T41

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T7,T27,T11
0	1	Covered	T7,T27,T11
0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T27,T11
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T7,T27,T11
IdleSt	0	-	-	-	-	-	-	Covered	T7,T27,T11
DebounceSt	-	1	-	-	-	-	-	Covered	T83,T50
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T27,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T83,T259,T50
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T27,T11
DetectSt	-	-	-	-	1	-	-	Covered	T27,T42,T73
DetectSt	-	-	-	-	0	1	-	Covered	T7,T11,T41
DetectSt	-	-	-	-	0	0	-	Covered	T7,T27,T11
StableSt	-	-	-	-	-	-	1	Covered	T7,T11,T41
StableSt	-	-	-	-	-	-	0	Covered	T7,T11,T41
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9452567	3235	0	0
CntIncr_A	9452567	105242	0	0
CntNoWrap_A	9452567	8787241	0	0
DetectStDropOut_A	9452567	425	0	0
DetectedOut_A	9452567	80039	0	0
DetectedPulseOut_A	9452567	933	0	0
DisabledIdleSt_A	9452567	8327527	0	0
DisabledNoDetection_A	9452567	8329745	0	0
EnterDebounceSt_A	9452567	1623	0	0
EnterDetectSt_A	9452567	1612	0	0
EnterStableSt_A	9452567	933	0	0
PulseIsPulse_A	9452567	933	0	0
StayInStableSt	9452567	78994	0	0
gen_high_event_sva.HighLevelEvent_A	9452567	8792903	0	0
gen_high_level_sva.HighLevelEvent_A	9452567	8792903	0	0
gen_not_sticky_sva.StableStDropOut_A	9452567	819	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	3235	0	0
T7	15140	20	0	0
T8	1043	0	0	0
T9	933	0	0	0
T11	0	12	0	0
T21	492	0	0	0
T25	686	0	0	0
T26	618	0	0	0
T27	5516	52	0	0
T39	0	44	0	0
T40	0	38	0	0
T41	0	36	0	0
T42	0	20	0	0
T43	644	0	0	0
T47	523	0	0	0
T48	761	0	0	0
T73	0	6	0	0
T74	0	16	0	0
T75	0	38	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	105242	0	0
T7	15140	820	0	0
T8	1043	0	0	0
T9	933	0	0	0
T11	0	234	0	0
T21	492	0	0	0
T25	686	0	0	0
T26	618	0	0	0
T27	5516	1504	0	0
T39	0	1496	0	0
T40	0	1691	0	0
T41	0	936	0	0
T42	0	591	0	0
T43	644	0	0	0
T47	523	0	0	0
T48	761	0	0	0
T73	0	151	0	0
T74	0	496	0	0
T75	0	853	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	8787241	0	0
T1	26361	25911	0	0
T2	13744	13317	0	0
T3	2057	1656	0	0
T4	24722	20703	0	0
T5	8493	8083	0	0
T6	422	21	0	0
T7	15140	14700	0	0
T13	507	106	0	0
T14	507	106	0	0
T15	501	100	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	425	0	0
T8	1043	0	0	0
T9	933	0	0	0
T21	492	0	0	0
T22	495	0	0	0
T25	686	0	0	0
T26	618	0	0	0
T27	5516	26	0	0
T42	0	3	0	0
T43	644	0	0	0
T47	523	0	0	0
T48	761	0	0	0
T73	0	3	0	0
T75	0	19	0	0
T97	0	30	0	0
T99	0	1	0	0
T233	0	3	0	0
T262	0	2	0	0
T265	0	26	0	0
T266	0	5	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	80039	0	0
T7	15140	1488	0	0
T8	1043	0	0	0
T9	933	0	0	0
T11	0	1197	0	0
T21	492	0	0	0
T25	686	0	0	0
T26	618	0	0	0
T27	5516	0	0	0
T39	0	2779	0	0
T40	0	585	0	0
T41	0	77	0	0
T43	644	0	0	0
T47	523	0	0	0
T48	761	0	0	0
T74	0	1734	0	0
T117	0	38	0	0
T118	0	222	0	0
T261	0	641	0	0
T267	0	339	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	933	0	0
T7	15140	10	0	0
T8	1043	0	0	0
T9	933	0	0	0
T11	0	6	0	0
T21	492	0	0	0
T25	686	0	0	0
T26	618	0	0	0
T27	5516	0	0	0
T39	0	22	0	0
T40	0	19	0	0
T41	0	18	0	0
T43	644	0	0	0
T47	523	0	0	0
T48	761	0	0	0
T74	0	8	0	0
T117	0	6	0	0
T118	0	5	0	0
T261	0	27	0	0
T267	0	7	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	8327527	0	0
T1	26361	25911	0	0
T2	13744	13317	0	0
T3	2057	1656	0	0
T4	24722	20703	0	0
T5	8493	8083	0	0
T6	422	21	0	0
T7	15140	8718	0	0
T13	507	106	0	0
T14	507	106	0	0
T15	501	100	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	8329745	0	0
T1	26361	25920	0	0
T2	13744	13321	0	0
T3	2057	1657	0	0
T4	24722	20721	0	0
T5	8493	8086	0	0
T6	422	22	0	0
T7	15140	8720	0	0
T13	507	107	0	0
T14	507	107	0	0
T15	501	101	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	1623	0	0
T7	15140	10	0	0
T8	1043	0	0	0
T9	933	0	0	0
T11	0	6	0	0
T21	492	0	0	0
T25	686	0	0	0
T26	618	0	0	0
T27	5516	26	0	0
T39	0	22	0	0
T40	0	19	0	0
T41	0	18	0	0
T42	0	10	0	0
T43	644	0	0	0
T47	523	0	0	0
T48	761	0	0	0
T73	0	3	0	0
T74	0	8	0	0
T75	0	19	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	1612	0	0
T7	15140	10	0	0
T8	1043	0	0	0
T9	933	0	0	0
T11	0	6	0	0
T21	492	0	0	0
T25	686	0	0	0
T26	618	0	0	0
T27	5516	26	0	0
T39	0	22	0	0
T40	0	19	0	0
T41	0	18	0	0
T42	0	10	0	0
T43	644	0	0	0
T47	523	0	0	0
T48	761	0	0	0
T73	0	3	0	0
T74	0	8	0	0
T75	0	19	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	933	0	0
T7	15140	10	0	0
T8	1043	0	0	0
T9	933	0	0	0
T11	0	6	0	0
T21	492	0	0	0
T25	686	0	0	0
T26	618	0	0	0
T27	5516	0	0	0
T39	0	22	0	0
T40	0	19	0	0
T41	0	18	0	0
T43	644	0	0	0
T47	523	0	0	0
T48	761	0	0	0
T74	0	8	0	0
T117	0	6	0	0
T118	0	5	0	0
T261	0	27	0	0
T267	0	7	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	933	0	0
T7	15140	10	0	0
T8	1043	0	0	0
T9	933	0	0	0
T11	0	6	0	0
T21	492	0	0	0
T25	686	0	0	0
T26	618	0	0	0
T27	5516	0	0	0
T39	0	22	0	0
T40	0	19	0	0
T41	0	18	0	0
T43	644	0	0	0
T47	523	0	0	0
T48	761	0	0	0
T74	0	8	0	0
T117	0	6	0	0
T118	0	5	0	0
T261	0	27	0	0
T267	0	7	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	78994	0	0
T7	15140	1477	0	0
T8	1043	0	0	0
T9	933	0	0	0
T11	0	1186	0	0
T21	492	0	0	0
T25	686	0	0	0
T26	618	0	0	0
T27	5516	0	0	0
T39	0	2749	0	0
T40	0	564	0	0
T41	0	59	0	0
T43	644	0	0	0
T47	523	0	0	0
T48	761	0	0	0
T74	0	1719	0	0
T117	0	32	0	0
T118	0	217	0	0
T261	0	614	0	0
T267	0	332	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	8792903	0	0
T1	26361	25920	0	0
T2	13744	13321	0	0
T3	2057	1657	0	0
T4	24722	20721	0	0
T5	8493	8086	0	0
T6	422	22	0	0
T7	15140	14724	0	0
T13	507	107	0	0
T14	507	107	0	0
T15	501	101	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	8792903	0	0
T1	26361	25920	0	0
T2	13744	13321	0	0
T3	2057	1657	0	0
T4	24722	20721	0	0
T5	8493	8086	0	0
T6	422	22	0	0
T7	15140	14724	0	0
T13	507	107	0	0
T14	507	107	0	0
T15	501	101	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	819	0	0
T7	15140	9	0	0
T8	1043	0	0	0
T9	933	0	0	0
T11	0	1	0	0
T21	492	0	0	0
T25	686	0	0	0
T26	618	0	0	0
T27	5516	0	0	0
T39	0	14	0	0
T40	0	17	0	0
T41	0	18	0	0
T43	644	0	0	0
T47	523	0	0	0
T48	761	0	0	0
T74	0	1	0	0
T117	0	6	0	0
T118	0	5	0	0
T261	0	27	0	0
T267	0	7	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T2
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T2

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T1,T5,T2

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T2

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Covered	T5,T52,T94
1	0	Covered	T83,T50

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T2,T4
1	0	Covered	T83,T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T4
1	-	Covered	T1,T2,T4

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T5,T2
DetectSt	168	Covered	T1,T5,T2
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T1,T2,T4

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T5,T2
DebounceSt->IdleSt	163	Covered	T10,T52,T32
DetectSt->IdleSt	186	Covered	T5,T52,T55
DetectSt->StableSt	191	Covered	T1,T2,T4
IdleSt->DebounceSt	148	Covered	T1,T5,T2
StableSt->IdleSt	206	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T5,T2
0	1	Covered	T1,T5,T2
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T2
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T5,T2
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T83,T50
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T5,T2
DebounceSt	-	0	1	0	-	-	-	Covered	T10,T52,T32
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T5,T2
DetectSt	-	-	-	-	1	-	-	Covered	T5,T52,T94
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T4
DetectSt	-	-	-	-	0	0	-	Covered	T1,T5,T2
StableSt	-	-	-	-	-	-	1	Covered	T1,T2,T4
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T4
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9452567	891	0	0
CntIncr_A	9452567	49966	0	0
CntNoWrap_A	9452567	8789585	0	0
DetectStDropOut_A	9452567	29	0	0
DetectedOut_A	9452567	19515	0	0
DetectedPulseOut_A	9452567	389	0	0
DisabledIdleSt_A	9452567	8373809	0	0
DisabledNoDetection_A	9452567	8375499	0	0
EnterDebounceSt_A	9452567	471	0	0
EnterDetectSt_A	9452567	422	0	0
EnterStableSt_A	9452567	389	0	0
PulseIsPulse_A	9452567	389	0	0
StayInStableSt	9452567	19094	0	0
gen_high_level_sva.HighLevelEvent_A	9452567	8792903	0	0
gen_not_sticky_sva.StableStDropOut_A	9452567	355	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	891	0	0
T1	26361	14	0	0
T2	13744	2	0	0
T3	2057	0	0	0
T4	24722	10	0	0
T5	8493	2	0	0
T6	422	0	0	0
T7	15140	4	0	0
T10	0	26	0	0
T11	0	10	0	0
T12	0	4	0	0
T13	507	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T52	0	9	0	0
T95	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	49966	0	0
T1	26361	1904	0	0
T2	13744	102	0	0
T3	2057	0	0	0
T4	24722	795	0	0
T5	8493	74	0	0
T6	422	0	0	0
T7	15140	202	0	0
T10	0	1390	0	0
T11	0	310	0	0
T12	0	214	0	0
T13	507	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T52	0	730	0	0
T95	0	474	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	8789585	0	0
T1	26361	25897	0	0
T2	13744	13315	0	0
T3	2057	1656	0	0
T4	24722	20693	0	0
T5	8493	8081	0	0
T6	422	21	0	0
T7	15140	14716	0	0
T13	507	106	0	0
T14	507	106	0	0
T15	501	100	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	29	0	0
T2	13744	0	0	0
T3	2057	0	0	0
T4	24722	0	0	0
T5	8493	1	0	0
T6	422	0	0	0
T7	15140	0	0	0
T13	507	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T27	5516	0	0	0
T50	0	1	0	0
T52	0	4	0	0
T94	0	1	0	0
T101	0	2	0	0
T277	0	1	0	0
T278	0	6	0	0
T279	0	1	0	0
T280	0	4	0	0
T281	0	5	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	19515	0	0
T1	26361	454	0	0
T2	13744	91	0	0
T3	2057	0	0	0
T4	24722	42	0	0
T5	8493	0	0	0
T6	422	0	0	0
T7	15140	107	0	0
T10	0	613	0	0
T11	0	303	0	0
T12	0	44	0	0
T13	507	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T32	0	108	0	0
T39	0	437	0	0
T95	0	68	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	389	0	0
T1	26361	7	0	0
T2	13744	1	0	0
T3	2057	0	0	0
T4	24722	5	0	0
T5	8493	0	0	0
T6	422	0	0	0
T7	15140	2	0	0
T10	0	12	0	0
T11	0	5	0	0
T12	0	2	0	0
T13	507	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T32	0	2	0	0
T39	0	7	0	0
T95	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	8373809	0	0
T1	26361	18130	0	0
T2	13744	8058	0	0
T3	2057	1656	0	0
T4	24722	17786	0	0
T5	8493	6045	0	0
T6	422	21	0	0
T7	15140	13233	0	0
T13	507	106	0	0
T14	507	106	0	0
T15	501	100	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	8375499	0	0
T1	26361	18130	0	0
T2	13744	8058	0	0
T3	2057	1657	0	0
T4	24722	17797	0	0
T5	8493	6045	0	0
T6	422	22	0	0
T7	15140	13236	0	0
T13	507	107	0	0
T14	507	107	0	0
T15	501	101	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	471	0	0
T1	26361	7	0	0
T2	13744	1	0	0
T3	2057	0	0	0
T4	24722	5	0	0
T5	8493	1	0	0
T6	422	0	0	0
T7	15140	2	0	0
T10	0	14	0	0
T11	0	5	0	0
T12	0	2	0	0
T13	507	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T52	0	5	0	0
T95	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	422	0	0
T1	26361	7	0	0
T2	13744	1	0	0
T3	2057	0	0	0
T4	24722	5	0	0
T5	8493	1	0	0
T6	422	0	0	0
T7	15140	2	0	0
T10	0	12	0	0
T11	0	5	0	0
T12	0	2	0	0
T13	507	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T52	0	4	0	0
T95	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	389	0	0
T1	26361	7	0	0
T2	13744	1	0	0
T3	2057	0	0	0
T4	24722	5	0	0
T5	8493	0	0	0
T6	422	0	0	0
T7	15140	2	0	0
T10	0	12	0	0
T11	0	5	0	0
T12	0	2	0	0
T13	507	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T32	0	2	0	0
T39	0	7	0	0
T95	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	389	0	0
T1	26361	7	0	0
T2	13744	1	0	0
T3	2057	0	0	0
T4	24722	5	0	0
T5	8493	0	0	0
T6	422	0	0	0
T7	15140	2	0	0
T10	0	12	0	0
T11	0	5	0	0
T12	0	2	0	0
T13	507	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T32	0	2	0	0
T39	0	7	0	0
T95	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	19094	0	0
T1	26361	447	0	0
T2	13744	90	0	0
T3	2057	0	0	0
T4	24722	37	0	0
T5	8493	0	0	0
T6	422	0	0	0
T7	15140	104	0	0
T10	0	601	0	0
T11	0	293	0	0
T12	0	42	0	0
T13	507	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T32	0	106	0	0
T39	0	423	0	0
T95	0	65	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	8792903	0	0
T1	26361	25920	0	0
T2	13744	13321	0	0
T3	2057	1657	0	0
T4	24722	20721	0	0
T5	8493	8086	0	0
T6	422	22	0	0
T7	15140	14724	0	0
T13	507	107	0	0
T14	507	107	0	0
T15	501	101	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	355	0	0
T1	26361	7	0	0
T2	13744	1	0	0
T3	2057	0	0	0
T4	24722	5	0	0
T5	8493	0	0	0
T6	422	0	0	0
T7	15140	1	0	0
T10	0	12	0	0
T12	0	2	0	0
T13	507	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T32	0	2	0	0
T74	0	7	0	0
T95	0	3	0	0
T282	0	10	0	0