Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T7,T27,T11
1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T7,T27,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T7,T27,T11

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T7,T27,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T27,T11
1	0	Covered	T7,T11,T41
1	1	Covered	T7,T27,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T27,T11
0	1	Covered	T27,T73,T74
1	0	Covered	T41,T74,T261

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T11,T42
0	1	Covered	T7,T11,T42
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T11,T42
1	-	Covered	T7,T11,T42

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T27,T11
DetectSt	168	Covered	T7,T27,T11
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T7,T11,T42

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T27,T11
DebounceSt->IdleSt	163	Covered	T83,T259,T50
DetectSt->IdleSt	186	Covered	T27,T41,T73
DetectSt->StableSt	191	Covered	T7,T11,T42
IdleSt->DebounceSt	148	Covered	T7,T27,T11
StableSt->IdleSt	206	Covered	T7,T11,T42

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T7,T27,T11
0	1	Covered	T7,T27,T11
0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T27,T11
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T7,T27,T11
IdleSt	0	-	-	-	-	-	-	Covered	T7,T27,T11
DebounceSt	-	1	-	-	-	-	-	Covered	T83,T50
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T27,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T83,T259,T50
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T27,T11
DetectSt	-	-	-	-	1	-	-	Covered	T27,T41,T73
DetectSt	-	-	-	-	0	1	-	Covered	T7,T11,T42
DetectSt	-	-	-	-	0	0	-	Covered	T7,T27,T11
StableSt	-	-	-	-	-	-	1	Covered	T7,T11,T42
StableSt	-	-	-	-	-	-	0	Covered	T7,T11,T42
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9452567	3017	0	0
CntIncr_A	9452567	97932	0	0
CntNoWrap_A	9452567	8787459	0	0
DetectStDropOut_A	9452567	333	0	0
DetectedOut_A	9452567	70167	0	0
DetectedPulseOut_A	9452567	918	0	0
DisabledIdleSt_A	9452567	8334806	0	0
DisabledNoDetection_A	9452567	8337050	0	0
EnterDebounceSt_A	9452567	1514	0	0
EnterDetectSt_A	9452567	1503	0	0
EnterStableSt_A	9452567	918	0	0
PulseIsPulse_A	9452567	918	0	0
StayInStableSt	9452567	69164	0	0
gen_high_event_sva.HighLevelEvent_A	9452567	8792903	0	0
gen_high_level_sva.HighLevelEvent_A	9452567	8792903	0	0
gen_not_sticky_sva.StableStDropOut_A	9452567	833	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	3017	0	0
T7	15140	12	0	0
T8	1043	0	0	0
T9	933	0	0	0
T11	0	4	0	0
T21	492	0	0	0
T25	686	0	0	0
T26	618	0	0	0
T27	5516	54	0	0
T39	0	18	0	0
T40	0	28	0	0
T41	0	36	0	0
T42	0	26	0	0
T43	644	0	0	0
T47	523	0	0	0
T48	761	0	0	0
T73	0	44	0	0
T74	0	54	0	0
T75	0	54	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	97932	0	0
T7	15140	444	0	0
T8	1043	0	0	0
T9	933	0	0	0
T11	0	100	0	0
T21	492	0	0	0
T25	686	0	0	0
T26	618	0	0	0
T27	5516	1568	0	0
T39	0	783	0	0
T40	0	742	0	0
T41	0	975	0	0
T42	0	650	0	0
T43	644	0	0	0
T47	523	0	0	0
T48	761	0	0	0
T73	0	1116	0	0
T74	0	1710	0	0
T75	0	1215	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	8787459	0	0
T1	26361	25911	0	0
T2	13744	13317	0	0
T3	2057	1656	0	0
T4	24722	20703	0	0
T5	8493	8083	0	0
T6	422	21	0	0
T7	15140	14708	0	0
T13	507	106	0	0
T14	507	106	0	0
T15	501	100	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	333	0	0
T8	1043	0	0	0
T9	933	0	0	0
T21	492	0	0	0
T22	495	0	0	0
T25	686	0	0	0
T26	618	0	0	0
T27	5516	27	0	0
T43	644	0	0	0
T47	523	0	0	0
T48	761	0	0	0
T73	0	13	0	0
T74	0	19	0	0
T75	0	27	0	0
T97	0	14	0	0
T98	0	4	0	0
T99	0	4	0	0
T265	0	26	0	0
T266	0	8	0	0
T283	0	6	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	70167	0	0
T7	15140	249	0	0
T8	1043	0	0	0
T9	933	0	0	0
T11	0	294	0	0
T21	492	0	0	0
T25	686	0	0	0
T26	618	0	0	0
T27	5516	0	0	0
T39	0	483	0	0
T40	0	831	0	0
T42	0	1351	0	0
T43	644	0	0	0
T47	523	0	0	0
T48	761	0	0	0
T73	0	9	0	0
T117	0	1127	0	0
T118	0	1044	0	0
T127	0	4218	0	0
T267	0	526	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	918	0	0
T7	15140	6	0	0
T8	1043	0	0	0
T9	933	0	0	0
T11	0	2	0	0
T21	492	0	0	0
T25	686	0	0	0
T26	618	0	0	0
T27	5516	0	0	0
T39	0	9	0	0
T40	0	14	0	0
T42	0	13	0	0
T43	644	0	0	0
T47	523	0	0	0
T48	761	0	0	0
T73	0	9	0	0
T117	0	19	0	0
T118	0	16	0	0
T127	0	24	0	0
T267	0	10	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	8334806	0	0
T1	26361	25911	0	0
T2	13744	13317	0	0
T3	2057	1656	0	0
T4	24722	20703	0	0
T5	8493	8083	0	0
T6	422	21	0	0
T7	15140	9992	0	0
T13	507	106	0	0
T14	507	106	0	0
T15	501	100	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	8337050	0	0
T1	26361	25920	0	0
T2	13744	13321	0	0
T3	2057	1657	0	0
T4	24722	20721	0	0
T5	8493	8086	0	0
T6	422	22	0	0
T7	15140	9994	0	0
T13	507	107	0	0
T14	507	107	0	0
T15	501	101	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	1514	0	0
T7	15140	6	0	0
T8	1043	0	0	0
T9	933	0	0	0
T11	0	2	0	0
T21	492	0	0	0
T25	686	0	0	0
T26	618	0	0	0
T27	5516	27	0	0
T39	0	9	0	0
T40	0	14	0	0
T41	0	18	0	0
T42	0	13	0	0
T43	644	0	0	0
T47	523	0	0	0
T48	761	0	0	0
T73	0	22	0	0
T74	0	27	0	0
T75	0	27	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	1503	0	0
T7	15140	6	0	0
T8	1043	0	0	0
T9	933	0	0	0
T11	0	2	0	0
T21	492	0	0	0
T25	686	0	0	0
T26	618	0	0	0
T27	5516	27	0	0
T39	0	9	0	0
T40	0	14	0	0
T41	0	18	0	0
T42	0	13	0	0
T43	644	0	0	0
T47	523	0	0	0
T48	761	0	0	0
T73	0	22	0	0
T74	0	27	0	0
T75	0	27	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	918	0	0
T7	15140	6	0	0
T8	1043	0	0	0
T9	933	0	0	0
T11	0	2	0	0
T21	492	0	0	0
T25	686	0	0	0
T26	618	0	0	0
T27	5516	0	0	0
T39	0	9	0	0
T40	0	14	0	0
T42	0	13	0	0
T43	644	0	0	0
T47	523	0	0	0
T48	761	0	0	0
T73	0	9	0	0
T117	0	19	0	0
T118	0	16	0	0
T127	0	24	0	0
T267	0	10	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	918	0	0
T7	15140	6	0	0
T8	1043	0	0	0
T9	933	0	0	0
T11	0	2	0	0
T21	492	0	0	0
T25	686	0	0	0
T26	618	0	0	0
T27	5516	0	0	0
T39	0	9	0	0
T40	0	14	0	0
T42	0	13	0	0
T43	644	0	0	0
T47	523	0	0	0
T48	761	0	0	0
T73	0	9	0	0
T117	0	19	0	0
T118	0	16	0	0
T127	0	24	0	0
T267	0	10	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	69164	0	0
T7	15140	242	0	0
T8	1043	0	0	0
T9	933	0	0	0
T11	0	291	0	0
T21	492	0	0	0
T25	686	0	0	0
T26	618	0	0	0
T27	5516	0	0	0
T39	0	473	0	0
T40	0	816	0	0
T42	0	1338	0	0
T43	644	0	0	0
T47	523	0	0	0
T48	761	0	0	0
T117	0	1107	0	0
T118	0	1026	0	0
T127	0	4189	0	0
T262	0	1222	0	0
T267	0	516	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	8792903	0	0
T1	26361	25920	0	0
T2	13744	13321	0	0
T3	2057	1657	0	0
T4	24722	20721	0	0
T5	8493	8086	0	0
T6	422	22	0	0
T7	15140	14724	0	0
T13	507	107	0	0
T14	507	107	0	0
T15	501	101	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	8792903	0	0
T1	26361	25920	0	0
T2	13744	13321	0	0
T3	2057	1657	0	0
T4	24722	20721	0	0
T5	8493	8086	0	0
T6	422	22	0	0
T7	15140	14724	0	0
T13	507	107	0	0
T14	507	107	0	0
T15	501	101	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	833	0	0
T7	15140	5	0	0
T8	1043	0	0	0
T9	933	0	0	0
T11	0	1	0	0
T21	492	0	0	0
T25	686	0	0	0
T26	618	0	0	0
T27	5516	0	0	0
T39	0	8	0	0
T40	0	13	0	0
T42	0	13	0	0
T43	644	0	0	0
T47	523	0	0	0
T48	761	0	0	0
T73	0	9	0	0
T117	0	18	0	0
T118	0	14	0	0
T127	0	19	0	0
T267	0	10	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T2,T4

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T1,T2,T4

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T2,T4

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T2,T4

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T268,T269,T190
1	0	Covered	T83,T50

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T2,T4
1	0	Covered	T84

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T4
1	-	Covered	T1,T2,T4

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T4
DetectSt	168	Covered	T1,T2,T4
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T1,T2,T4

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T4
DebounceSt->IdleSt	163	Covered	T39,T284,T285
DetectSt->IdleSt	186	Covered	T55,T268,T269
DetectSt->StableSt	191	Covered	T1,T2,T4
IdleSt->DebounceSt	148	Covered	T1,T2,T4
StableSt->IdleSt	206	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T4
0	1	Covered	T1,T2,T4
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T4
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T83,T50
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T4
DebounceSt	-	0	1	0	-	-	-	Covered	T39,T284,T285
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T4
DetectSt	-	-	-	-	1	-	-	Covered	T268,T269,T190
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T4
DetectSt	-	-	-	-	0	0	-	Covered	T1,T2,T4
StableSt	-	-	-	-	-	-	1	Covered	T1,T2,T4
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T4
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9452567	891	0	0
CntIncr_A	9452567	49814	0	0
CntNoWrap_A	9452567	8789585	0	0
DetectStDropOut_A	9452567	33	0	0
DetectedOut_A	9452567	18593	0	0
DetectedPulseOut_A	9452567	391	0	0
DisabledIdleSt_A	9452567	8391789	0	0
DisabledNoDetection_A	9452567	8393514	0	0
EnterDebounceSt_A	9452567	464	0	0
EnterDetectSt_A	9452567	428	0	0
EnterStableSt_A	9452567	391	0	0
PulseIsPulse_A	9452567	391	0	0
StayInStableSt	9452567	18176	0	0
gen_high_level_sva.HighLevelEvent_A	9452567	8792903	0	0
gen_not_sticky_sva.StableStDropOut_A	9452567	361	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	891	0	0
T1	26361	2	0	0
T2	13744	2	0	0
T3	2057	0	0	0
T4	24722	4	0	0
T5	8493	0	0	0
T6	422	0	0	0
T7	15140	2	0	0
T10	0	12	0	0
T12	0	6	0	0
T13	507	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T39	0	1	0	0
T42	0	4	0	0
T52	0	6	0	0
T95	0	22	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	49814	0	0
T1	26361	322	0	0
T2	13744	139	0	0
T3	2057	0	0	0
T4	24722	184	0	0
T5	8493	0	0	0
T6	422	0	0	0
T7	15140	86	0	0
T10	0	650	0	0
T12	0	291	0	0
T13	507	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T39	0	50	0	0
T42	0	120	0	0
T52	0	510	0	0
T95	0	1914	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	8789585	0	0
T1	26361	25909	0	0
T2	13744	13315	0	0
T3	2057	1656	0	0
T4	24722	20699	0	0
T5	8493	8083	0	0
T6	422	21	0	0
T7	15140	14718	0	0
T13	507	106	0	0
T14	507	106	0	0
T15	501	100	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	33	0	0
T83	0	1	0	0
T87	835	0	0	0
T133	0	1	0	0
T151	0	6	0	0
T190	0	6	0	0
T236	10870	0	0	0
T237	489	0	0	0
T238	666	0	0	0
T239	434	0	0	0
T240	441	0	0	0
T241	409	0	0	0
T268	27998	1	0	0
T269	0	3	0	0
T273	0	2	0	0
T277	0	2	0	0
T279	0	5	0	0
T286	0	6	0	0
T287	754	0	0	0
T288	426	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	18593	0	0
T1	26361	15	0	0
T2	13744	54	0	0
T3	2057	0	0	0
T4	24722	150	0	0
T5	8493	0	0	0
T6	422	0	0	0
T7	15140	67	0	0
T10	0	326	0	0
T12	0	96	0	0
T13	507	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T40	0	86	0	0
T42	0	115	0	0
T52	0	13	0	0
T95	0	80	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	391	0	0
T1	26361	1	0	0
T2	13744	1	0	0
T3	2057	0	0	0
T4	24722	2	0	0
T5	8493	0	0	0
T6	422	0	0	0
T7	15140	1	0	0
T10	0	6	0	0
T12	0	3	0	0
T13	507	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T40	0	2	0	0
T42	0	2	0	0
T52	0	3	0	0
T95	0	11	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	8391789	0	0
T1	26361	18130	0	0
T2	13744	8058	0	0
T3	2057	1656	0	0
T4	24722	17786	0	0
T5	8493	8083	0	0
T6	422	21	0	0
T7	15140	14472	0	0
T13	507	106	0	0
T14	507	106	0	0
T15	501	100	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	8393514	0	0
T1	26361	18130	0	0
T2	13744	8058	0	0
T3	2057	1657	0	0
T4	24722	17797	0	0
T5	8493	8086	0	0
T6	422	22	0	0
T7	15140	14475	0	0
T13	507	107	0	0
T14	507	107	0	0
T15	501	101	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	464	0	0
T1	26361	1	0	0
T2	13744	1	0	0
T3	2057	0	0	0
T4	24722	2	0	0
T5	8493	0	0	0
T6	422	0	0	0
T7	15140	1	0	0
T10	0	6	0	0
T12	0	3	0	0
T13	507	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T39	0	1	0	0
T42	0	2	0	0
T52	0	3	0	0
T95	0	11	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	428	0	0
T1	26361	1	0	0
T2	13744	1	0	0
T3	2057	0	0	0
T4	24722	2	0	0
T5	8493	0	0	0
T6	422	0	0	0
T7	15140	1	0	0
T10	0	6	0	0
T12	0	3	0	0
T13	507	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T40	0	2	0	0
T42	0	2	0	0
T52	0	3	0	0
T95	0	11	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	391	0	0
T1	26361	1	0	0
T2	13744	1	0	0
T3	2057	0	0	0
T4	24722	2	0	0
T5	8493	0	0	0
T6	422	0	0	0
T7	15140	1	0	0
T10	0	6	0	0
T12	0	3	0	0
T13	507	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T40	0	2	0	0
T42	0	2	0	0
T52	0	3	0	0
T95	0	11	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	391	0	0
T1	26361	1	0	0
T2	13744	1	0	0
T3	2057	0	0	0
T4	24722	2	0	0
T5	8493	0	0	0
T6	422	0	0	0
T7	15140	1	0	0
T10	0	6	0	0
T12	0	3	0	0
T13	507	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T40	0	2	0	0
T42	0	2	0	0
T52	0	3	0	0
T95	0	11	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	18176	0	0
T1	26361	14	0	0
T2	13744	53	0	0
T3	2057	0	0	0
T4	24722	148	0	0
T5	8493	0	0	0
T6	422	0	0	0
T7	15140	65	0	0
T10	0	320	0	0
T12	0	93	0	0
T13	507	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T40	0	84	0	0
T42	0	113	0	0
T52	0	10	0	0
T95	0	69	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	8792903	0	0
T1	26361	25920	0	0
T2	13744	13321	0	0
T3	2057	1657	0	0
T4	24722	20721	0	0
T5	8493	8086	0	0
T6	422	22	0	0
T7	15140	14724	0	0
T13	507	107	0	0
T14	507	107	0	0
T15	501	101	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9452567	361	0	0
T1	26361	1	0	0
T2	13744	1	0	0
T3	2057	0	0	0
T4	24722	2	0	0
T5	8493	0	0	0
T6	422	0	0	0
T7	15140	0	0	0
T10	0	6	0	0
T12	0	3	0	0
T13	507	0	0	0
T14	507	0	0	0
T15	501	0	0	0
T32	0	3	0	0
T40	0	2	0	0
T42	0	2	0	0
T52	0	3	0	0
T95	0	11	0	0