Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1299919929	13573	0	0
auto_block_debounce_ctl_rd_A	1299919929	1643	0	0
auto_block_out_ctl_rd_A	1299919929	2306	0	0
com_det_ctl_0_rd_A	1299919929	3705	0	0
com_det_ctl_1_rd_A	1299919929	3840	0	0
com_det_ctl_2_rd_A	1299919929	3779	0	0
com_det_ctl_3_rd_A	1299919929	3742	0	0
com_out_ctl_0_rd_A	1299919929	4305	0	0
com_out_ctl_1_rd_A	1299919929	4302	0	0
com_out_ctl_2_rd_A	1299919929	4389	0	0
com_out_ctl_3_rd_A	1299919929	4077	0	0
com_pre_det_ctl_0_rd_A	1299919929	1182	0	0
com_pre_det_ctl_1_rd_A	1299919929	1195	0	0
com_pre_det_ctl_2_rd_A	1299919929	1333	0	0
com_pre_det_ctl_3_rd_A	1299919929	1203	0	0
com_pre_sel_ctl_0_rd_A	1299919929	4491	0	0
com_pre_sel_ctl_1_rd_A	1299919929	4377	0	0
com_pre_sel_ctl_2_rd_A	1299919929	4510	0	0
com_pre_sel_ctl_3_rd_A	1299919929	4710	0	0
com_sel_ctl_0_rd_A	1299919929	4557	0	0
com_sel_ctl_1_rd_A	1299919929	4513	0	0
com_sel_ctl_2_rd_A	1299919929	4506	0	0
com_sel_ctl_3_rd_A	1299919929	4671	0	0
ec_rst_ctl_rd_A	1299919929	2259	0	0
intr_enable_rd_A	1299919929	1891	0	0
key_intr_ctl_rd_A	1299919929	3444	0	0
key_intr_debounce_ctl_rd_A	1299919929	1131	0	0
key_invert_ctl_rd_A	1299919929	4734	0	0
pin_allowed_ctl_rd_A	1299919929	6763	0	0
pin_out_ctl_rd_A	1299919929	5181	0	0
pin_out_value_rd_A	1299919929	5049	0	0
regwen_rd_A	1299919929	1185	0	0
ulp_ac_debounce_ctl_rd_A	1299919929	1400	0	0
ulp_ctl_rd_A	1299919929	1297	0	0
ulp_lid_debounce_ctl_rd_A	1299919929	1330	0	0
ulp_pwrb_debounce_ctl_rd_A	1299919929	1256	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	13573	0	0
T4	593346	5	0	0
T7	719203	0	0	0
T8	500783	0	0	0
T14	48200	0	0	0
T15	251000	0	0	0
T20	0	6	0	0
T25	85827	0	0	0
T26	74233	0	0	0
T27	273041	0	0	0
T32	0	6	0	0
T46	0	5	0	0
T47	122818	0	0	0
T48	190233	0	0	0
T55	0	16	0	0
T78	0	24	0	0
T85	0	9	0	0
T86	0	11	0	0
T154	0	4	0	0
T307	0	10	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1643	0	0
T4	593346	12	0	0
T7	719203	0	0	0
T8	500783	0	0	0
T14	48200	0	0	0
T15	251000	0	0	0
T25	85827	0	0	0
T26	74233	0	0	0
T27	273041	0	0	0
T32	0	11	0	0
T44	0	7	0	0
T46	0	27	0	0
T47	122818	0	0	0
T48	190233	0	0	0
T154	0	8	0	0
T268	0	14	0	0
T287	0	7	0	0
T307	0	19	0	0
T308	0	5	0	0
T309	0	16	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	2306	0	0
T4	593346	8	0	0
T7	719203	0	0	0
T8	500783	0	0	0
T14	48200	0	0	0
T15	251000	0	0	0
T25	85827	0	0	0
T26	74233	0	0	0
T27	273041	0	0	0
T32	0	12	0	0
T44	0	3	0	0
T46	0	33	0	0
T47	122818	0	0	0
T48	190233	0	0	0
T268	0	8	0	0
T287	0	6	0	0
T307	0	16	0	0
T308	0	18	0	0
T309	0	14	0	0
T310	0	5	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	3705	0	0
T4	593346	37	0	0
T7	719203	0	0	0
T8	500783	0	0	0
T14	48200	0	0	0
T15	251000	0	0	0
T25	85827	0	0	0
T26	74233	0	0	0
T27	273041	0	0	0
T32	0	61	0	0
T46	0	20	0	0
T47	122818	0	0	0
T48	190233	0	0	0
T52	0	67	0	0
T95	0	52	0	0
T98	0	30	0	0
T118	0	80	0	0
T130	0	49	0	0
T261	0	21	0	0
T285	0	55	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	3840	0	0
T4	593346	33	0	0
T7	719203	0	0	0
T8	500783	0	0	0
T14	48200	0	0	0
T15	251000	0	0	0
T25	85827	0	0	0
T26	74233	0	0	0
T27	273041	0	0	0
T32	0	45	0	0
T46	0	17	0	0
T47	122818	0	0	0
T48	190233	0	0	0
T52	0	65	0	0
T95	0	66	0	0
T98	0	24	0	0
T118	0	57	0	0
T130	0	43	0	0
T261	0	25	0	0
T285	0	84	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	3779	0	0
T4	593346	26	0	0
T7	719203	0	0	0
T8	500783	0	0	0
T14	48200	0	0	0
T15	251000	0	0	0
T25	85827	0	0	0
T26	74233	0	0	0
T27	273041	0	0	0
T32	0	59	0	0
T46	0	20	0	0
T47	122818	0	0	0
T48	190233	0	0	0
T52	0	79	0	0
T95	0	63	0	0
T98	0	32	0	0
T118	0	85	0	0
T130	0	36	0	0
T261	0	28	0	0
T285	0	64	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	3742	0	0
T4	593346	24	0	0
T7	719203	0	0	0
T8	500783	0	0	0
T14	48200	0	0	0
T15	251000	0	0	0
T25	85827	0	0	0
T26	74233	0	0	0
T27	273041	0	0	0
T32	0	65	0	0
T46	0	12	0	0
T47	122818	0	0	0
T48	190233	0	0	0
T52	0	42	0	0
T95	0	85	0	0
T98	0	35	0	0
T118	0	57	0	0
T130	0	53	0	0
T261	0	41	0	0
T285	0	70	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	4305	0	0
T4	593346	53	0	0
T7	719203	0	0	0
T8	500783	0	0	0
T14	48200	0	0	0
T15	251000	0	0	0
T25	85827	0	0	0
T26	74233	0	0	0
T27	273041	0	0	0
T32	0	76	0	0
T46	0	24	0	0
T47	122818	0	0	0
T48	190233	0	0	0
T52	0	68	0	0
T95	0	48	0	0
T98	0	51	0	0
T118	0	58	0	0
T130	0	69	0	0
T261	0	51	0	0
T285	0	57	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	4302	0	0
T4	593346	33	0	0
T7	719203	0	0	0
T8	500783	0	0	0
T14	48200	0	0	0
T15	251000	0	0	0
T25	85827	0	0	0
T26	74233	0	0	0
T27	273041	0	0	0
T32	0	55	0	0
T46	0	24	0	0
T47	122818	0	0	0
T48	190233	0	0	0
T52	0	63	0	0
T95	0	61	0	0
T98	0	31	0	0
T118	0	48	0	0
T130	0	27	0	0
T261	0	43	0	0
T285	0	72	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	4389	0	0
T4	593346	26	0	0
T7	719203	0	0	0
T8	500783	0	0	0
T14	48200	0	0	0
T15	251000	0	0	0
T25	85827	0	0	0
T26	74233	0	0	0
T27	273041	0	0	0
T32	0	88	0	0
T46	0	18	0	0
T47	122818	0	0	0
T48	190233	0	0	0
T52	0	68	0	0
T95	0	80	0	0
T98	0	33	0	0
T118	0	56	0	0
T130	0	59	0	0
T261	0	36	0	0
T285	0	90	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	4077	0	0
T4	593346	25	0	0
T7	719203	0	0	0
T8	500783	0	0	0
T14	48200	0	0	0
T15	251000	0	0	0
T25	85827	0	0	0
T26	74233	0	0	0
T27	273041	0	0	0
T32	0	72	0	0
T46	0	24	0	0
T47	122818	0	0	0
T48	190233	0	0	0
T52	0	66	0	0
T95	0	55	0	0
T98	0	32	0	0
T118	0	62	0	0
T130	0	41	0	0
T261	0	32	0	0
T285	0	67	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1182	0	0
T4	593346	11	0	0
T7	719203	0	0	0
T8	500783	0	0	0
T14	48200	0	0	0
T15	251000	0	0	0
T25	85827	0	0	0
T26	74233	0	0	0
T27	273041	0	0	0
T32	0	7	0	0
T46	0	24	0	0
T47	122818	0	0	0
T48	190233	0	0	0
T90	0	31	0	0
T91	0	3	0	0
T94	0	5	0	0
T133	0	21	0	0
T154	0	26	0	0
T192	0	18	0	0
T307	0	19	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1195	0	0
T4	593346	4	0	0
T7	719203	0	0	0
T8	500783	0	0	0
T14	48200	0	0	0
T15	251000	0	0	0
T25	85827	0	0	0
T26	74233	0	0	0
T27	273041	0	0	0
T32	0	3	0	0
T46	0	16	0	0
T47	122818	0	0	0
T48	190233	0	0	0
T90	0	17	0	0
T91	0	11	0	0
T94	0	5	0	0
T133	0	17	0	0
T154	0	10	0	0
T192	0	8	0	0
T307	0	14	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1333	0	0
T4	593346	9	0	0
T7	719203	0	0	0
T8	500783	0	0	0
T14	48200	0	0	0
T15	251000	0	0	0
T25	85827	0	0	0
T26	74233	0	0	0
T27	273041	0	0	0
T32	0	5	0	0
T46	0	17	0	0
T47	122818	0	0	0
T48	190233	0	0	0
T90	0	25	0	0
T91	0	27	0	0
T94	0	15	0	0
T133	0	8	0	0
T154	0	10	0	0
T192	0	11	0	0
T307	0	27	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1203	0	0
T4	593346	4	0	0
T7	719203	0	0	0
T8	500783	0	0	0
T14	48200	0	0	0
T15	251000	0	0	0
T25	85827	0	0	0
T26	74233	0	0	0
T27	273041	0	0	0
T32	0	2	0	0
T46	0	18	0	0
T47	122818	0	0	0
T48	190233	0	0	0
T90	0	29	0	0
T91	0	8	0	0
T94	0	12	0	0
T133	0	11	0	0
T154	0	17	0	0
T192	0	17	0	0
T307	0	21	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	4491	0	0
T4	593346	35	0	0
T7	719203	0	0	0
T8	500783	0	0	0
T14	48200	0	0	0
T15	251000	0	0	0
T25	85827	0	0	0
T26	74233	0	0	0
T27	273041	0	0	0
T32	0	52	0	0
T46	0	22	0	0
T47	122818	0	0	0
T48	190233	0	0	0
T52	0	59	0	0
T95	0	79	0	0
T98	0	36	0	0
T118	0	62	0	0
T130	0	33	0	0
T261	0	55	0	0
T285	0	67	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	4377	0	0
T4	593346	32	0	0
T7	719203	0	0	0
T8	500783	0	0	0
T14	48200	0	0	0
T15	251000	0	0	0
T25	85827	0	0	0
T26	74233	0	0	0
T27	273041	0	0	0
T32	0	69	0	0
T46	0	13	0	0
T47	122818	0	0	0
T48	190233	0	0	0
T52	0	70	0	0
T95	0	62	0	0
T98	0	27	0	0
T118	0	67	0	0
T130	0	48	0	0
T261	0	36	0	0
T285	0	51	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	4510	0	0
T4	593346	44	0	0
T7	719203	0	0	0
T8	500783	0	0	0
T14	48200	0	0	0
T15	251000	0	0	0
T25	85827	0	0	0
T26	74233	0	0	0
T27	273041	0	0	0
T32	0	63	0	0
T46	0	20	0	0
T47	122818	0	0	0
T48	190233	0	0	0
T52	0	84	0	0
T95	0	63	0	0
T98	0	53	0	0
T118	0	43	0	0
T130	0	44	0	0
T261	0	46	0	0
T285	0	68	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	4710	0	0
T4	593346	42	0	0
T7	719203	0	0	0
T8	500783	0	0	0
T14	48200	0	0	0
T15	251000	0	0	0
T25	85827	0	0	0
T26	74233	0	0	0
T27	273041	0	0	0
T32	0	75	0	0
T46	0	14	0	0
T47	122818	0	0	0
T48	190233	0	0	0
T52	0	73	0	0
T95	0	75	0	0
T98	0	17	0	0
T118	0	57	0	0
T130	0	54	0	0
T261	0	40	0	0
T285	0	68	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	4557	0	0
T4	593346	36	0	0
T7	719203	0	0	0
T8	500783	0	0	0
T14	48200	0	0	0
T15	251000	0	0	0
T25	85827	0	0	0
T26	74233	0	0	0
T27	273041	0	0	0
T32	0	62	0	0
T46	0	24	0	0
T47	122818	0	0	0
T48	190233	0	0	0
T52	0	55	0	0
T95	0	106	0	0
T98	0	28	0	0
T118	0	82	0	0
T130	0	26	0	0
T261	0	47	0	0
T285	0	79	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	4513	0	0
T4	593346	26	0	0
T7	719203	0	0	0
T8	500783	0	0	0
T14	48200	0	0	0
T15	251000	0	0	0
T25	85827	0	0	0
T26	74233	0	0	0
T27	273041	0	0	0
T32	0	80	0	0
T46	0	15	0	0
T47	122818	0	0	0
T48	190233	0	0	0
T52	0	69	0	0
T95	0	69	0	0
T98	0	42	0	0
T118	0	76	0	0
T130	0	52	0	0
T261	0	67	0	0
T285	0	60	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	4506	0	0
T4	593346	28	0	0
T7	719203	0	0	0
T8	500783	0	0	0
T14	48200	0	0	0
T15	251000	0	0	0
T25	85827	0	0	0
T26	74233	0	0	0
T27	273041	0	0	0
T32	0	81	0	0
T46	0	21	0	0
T47	122818	0	0	0
T48	190233	0	0	0
T52	0	81	0	0
T95	0	68	0	0
T98	0	48	0	0
T118	0	67	0	0
T130	0	40	0	0
T261	0	33	0	0
T285	0	76	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	4671	0	0
T4	593346	34	0	0
T7	719203	0	0	0
T8	500783	0	0	0
T14	48200	0	0	0
T15	251000	0	0	0
T25	85827	0	0	0
T26	74233	0	0	0
T27	273041	0	0	0
T32	0	61	0	0
T46	0	17	0	0
T47	122818	0	0	0
T48	190233	0	0	0
T52	0	86	0	0
T95	0	83	0	0
T98	0	29	0	0
T118	0	82	0	0
T130	0	28	0	0
T261	0	44	0	0
T285	0	60	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	2259	0	0
T4	593346	27	0	0
T7	719203	0	0	0
T8	500783	0	0	0
T14	48200	0	0	0
T15	251000	0	0	0
T25	85827	0	0	0
T26	74233	0	0	0
T27	273041	0	0	0
T32	0	38	0	0
T46	0	19	0	0
T47	122818	0	0	0
T48	190233	3	0	0
T52	0	25	0	0
T95	0	24	0	0
T118	0	19	0	0
T119	0	5	0	0
T311	0	1	0	0
T312	0	1	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1891	0	0
T4	593346	17	0	0
T7	719203	0	0	0
T8	500783	0	0	0
T14	48200	0	0	0
T15	251000	0	0	0
T25	85827	0	0	0
T26	74233	0	0	0
T27	273041	0	0	0
T32	0	39	0	0
T46	0	52	0	0
T47	122818	0	0	0
T48	190233	0	0	0
T90	0	26	0	0
T91	0	10	0	0
T94	0	10	0	0
T154	0	34	0	0
T191	0	17	0	0
T192	0	110	0	0
T307	0	36	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	3444	0	0
T4	593346	8	0	0
T7	719203	0	0	0
T8	500783	0	0	0
T14	48200	0	0	0
T15	251000	0	0	0
T25	85827	0	0	0
T26	74233	0	0	0
T27	273041	0	0	0
T32	0	10	0	0
T46	0	30	0	0
T47	122818	0	0	0
T48	190233	0	0	0
T90	0	34	0	0
T91	0	26	0	0
T153	0	6	0	0
T154	0	27	0	0
T157	0	3	0	0
T191	0	3	0	0
T307	0	18	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1131	0	0
T4	593346	4	0	0
T7	719203	0	0	0
T8	500783	0	0	0
T14	48200	0	0	0
T15	251000	0	0	0
T25	85827	0	0	0
T26	74233	0	0	0
T27	273041	0	0	0
T32	0	10	0	0
T46	0	20	0	0
T47	122818	0	0	0
T48	190233	0	0	0
T90	0	23	0	0
T91	0	6	0	0
T94	0	5	0	0
T133	0	18	0	0
T154	0	16	0	0
T192	0	12	0	0
T307	0	22	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	4734	0	0
T9	448095	0	0	0
T10	116790	0	0	0
T11	397094	0	0	0
T21	125625	62	0	0
T22	64387	0	0	0
T32	0	2	0	0
T46	0	23	0	0
T49	361013	0	0	0
T65	255969	0	0	0
T66	55893	0	0	0
T67	53311	0	0	0
T68	65763	0	0	0
T90	0	20	0	0
T91	0	12	0	0
T154	0	304	0	0
T268	0	74	0	0
T307	0	25	0	0
T313	0	43	0	0
T314	0	72	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	6763	0	0
T4	593346	59	0	0
T7	719203	0	0	0
T8	500783	0	0	0
T14	48200	61	0	0
T15	251000	0	0	0
T25	85827	0	0	0
T26	74233	0	0	0
T27	273041	0	0	0
T32	0	253	0	0
T46	0	36	0	0
T47	122818	0	0	0
T48	190233	0	0	0
T201	0	21	0	0
T248	0	50	0	0
T307	0	29	0	0
T315	0	67	0	0
T316	0	77	0	0
T317	0	61	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	5181	0	0
T4	593346	25	0	0
T7	719203	0	0	0
T8	500783	0	0	0
T14	48200	66	0	0
T15	251000	0	0	0
T25	85827	0	0	0
T26	74233	0	0	0
T27	273041	0	0	0
T32	0	184	0	0
T46	0	30	0	0
T47	122818	0	0	0
T48	190233	0	0	0
T201	0	41	0	0
T248	0	41	0	0
T307	0	19	0	0
T315	0	70	0	0
T316	0	84	0	0
T317	0	33	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	5049	0	0
T4	593346	28	0	0
T7	719203	0	0	0
T8	500783	0	0	0
T14	48200	75	0	0
T15	251000	0	0	0
T25	85827	0	0	0
T26	74233	0	0	0
T27	273041	0	0	0
T32	0	185	0	0
T46	0	21	0	0
T47	122818	0	0	0
T48	190233	0	0	0
T201	0	37	0	0
T248	0	27	0	0
T307	0	18	0	0
T315	0	62	0	0
T316	0	68	0	0
T317	0	34	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1185	0	0
T4	593346	4	0	0
T7	719203	0	0	0
T8	500783	0	0	0
T14	48200	0	0	0
T15	251000	0	0	0
T25	85827	0	0	0
T26	74233	0	0	0
T27	273041	0	0	0
T32	0	11	0	0
T46	0	29	0	0
T47	122818	0	0	0
T48	190233	0	0	0
T90	0	18	0	0
T91	0	12	0	0
T94	0	5	0	0
T133	0	15	0	0
T154	0	8	0	0
T192	0	10	0	0
T307	0	24	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1400	0	0
T4	593346	6	0	0
T7	719203	0	0	0
T8	500783	0	0	0
T14	48200	0	0	0
T15	251000	0	0	0
T19	0	9	0	0
T25	85827	0	0	0
T26	74233	0	0	0
T27	273041	0	0	0
T31	0	2	0	0
T32	0	30	0	0
T46	0	18	0	0
T47	122818	0	0	0
T48	190233	0	0	0
T77	0	1	0	0
T79	0	6	0	0
T154	0	18	0	0
T307	0	14	0	0
T308	0	7	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1297	0	0
T4	593346	9	0	0
T7	719203	0	0	0
T8	500783	0	0	0
T14	48200	0	0	0
T15	251000	0	0	0
T19	0	5	0	0
T25	85827	0	0	0
T26	74233	0	0	0
T27	273041	0	0	0
T31	0	1	0	0
T32	0	15	0	0
T46	0	16	0	0
T47	122818	0	0	0
T48	190233	0	0	0
T77	0	3	0	0
T79	0	9	0	0
T154	0	25	0	0
T307	0	36	0	0
T308	0	1	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1330	0	0
T4	593346	10	0	0
T7	719203	0	0	0
T8	500783	0	0	0
T14	48200	0	0	0
T15	251000	0	0	0
T19	0	14	0	0
T25	85827	0	0	0
T26	74233	0	0	0
T27	273041	0	0	0
T31	0	3	0	0
T32	0	13	0	0
T46	0	12	0	0
T47	122818	0	0	0
T48	190233	0	0	0
T79	0	3	0	0
T154	0	20	0	0
T307	0	27	0	0
T308	0	2	0	0
T318	0	8	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1256	0	0
T4	593346	10	0	0
T7	719203	0	0	0
T8	500783	0	0	0
T14	48200	0	0	0
T15	251000	0	0	0
T19	0	10	0	0
T25	85827	0	0	0
T26	74233	0	0	0
T27	273041	0	0	0
T32	0	15	0	0
T46	0	19	0	0
T47	122818	0	0	0
T48	190233	0	0	0
T77	0	3	0	0
T79	0	1	0	0
T90	0	21	0	0
T154	0	20	0	0
T307	0	12	0	0
T308	0	6	0	0