Unified Coverage Report :: Module :: prim_reg_cdc

Module : prim_reg_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.30	100.00	89.20			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_wkup_status_cdc	96.88	100.00	87.50			100.00	100.00
tb.dut.u_reg.u_ec_rst_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_key_invert_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_pin_allowed_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_pin_out_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_pin_out_value_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_key_intr_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_auto_block_out_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_ulp_ctl_cdc	98.08	100.00	92.31			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_wkup_status_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	100.00	87.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.79	96.99	84.93			93.22	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	92.06	95.92	81.63			90.70	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_pin_out_value_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ulp_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	92.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Module : prim_reg_cdc ( parameter DataWidth=16,ResetVal,BitMask=65535,DstWrReq=0,TxnWidth=3 + DataWidth=12,ResetVal=0,BitMask=4095,DstWrReq=0,TxnWidth=3 + DataWidth=8,ResetVal,BitMask=255,DstWrReq=0,TxnWidth=3 + DataWidth=14,ResetVal=0,BitMask=16383,DstWrReq=0,TxnWidth=3 + DataWidth=17,ResetVal=2000,BitMask=131071,DstWrReq=0,TxnWidth=3 + DataWidth=7,ResetVal=0,BitMask=119,DstWrReq=0,TxnWidth=3 + DataWidth=5,ResetVal=0,BitMask=31,DstWrReq=0,TxnWidth=3 + DataWidth=32,ResetVal=0,BitMask=-1,DstWrReq=0,TxnWidth=3 + DataWidth=4,ResetVal=0,BitMask=15,DstWrReq=0,TxnWidth=3 )
Cond Coverage for Module self-instances :

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_ec_rst_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_pin_allowed_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_key_invert_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_pin_out_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_pin_out_value_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_key_intr_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_auto_block_out_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_sel_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_sel_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_sel_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_sel_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_det_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_det_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_det_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_det_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_out_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_out_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_out_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_out_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T5,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T5,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Cond Coverage for Module : prim_reg_cdc ( parameter DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=0,TxnWidth=3 + DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=1,TxnWidth=3 )
Cond Coverage for Module self-instances :

SCORE	COND
98.08	92.31

tb.dut.u_reg.u_ulp_ctl_cdc

SCORE	COND
96.88	87.50

tb.dut.u_reg.u_wkup_status_cdc

	Total	Covered	Percent
Conditions	16	14	87.50
Logical	16	14	87.50
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T3,T19,T20
1	-	Covered	T1,T2,T3

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Module : prim_reg_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	114198962	0	0
DstReqKnown_A	330282188	300965994	0	0
SrcAckBusyChk_A	2147483647	119758	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	114198962	0	0
T1	2398799	14669	0	0
T2	2233582	12076	0	0
T3	3123497	0	0	0
T4	8900190	53754	0	0
T5	1325077	10293	0	0
T6	2360852	0	0	0
T7	16541669	54872	0	0
T8	5508613	0	0	0
T9	4032855	0	0	0
T10	0	123360	0	0
T11	0	41147	0	0
T12	0	151983	0	0
T13	626353	0	0	0
T14	723000	0	0	0
T15	3765000	0	0	0
T20	0	6952	0	0
T21	1130625	0	0	0
T22	64387	0	0	0
T25	858270	2859	0	0
T26	742330	2630	0	0
T27	2730410	13187	0	0
T32	0	926	0	0
T36	0	3178	0	0
T39	0	21764	0	0
T41	0	358	0	0
T42	0	4151	0	0
T43	1276218	5713	0	0
T44	0	11436	0	0
T45	0	5331	0	0
T46	0	3100	0	0
T47	1228180	0	0	0
T48	1902330	0	0	0
T49	361013	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	330282188	300965994	0	0
T1	896274	881280	0	0
T2	467296	452914	0	0
T3	69938	56338	0	0
T4	840548	704514	0	0
T5	288762	274924	0	0
T6	14348	748	0	0
T7	514760	500616	0	0
T13	17238	3638	0	0
T14	17238	3638	0	0
T15	17034	3434	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	119758	0	0
T1	2398799	72	0	0
T2	2233582	32	0	0
T3	3123497	0	0	0
T4	8900190	65	0	0
T5	1325077	24	0	0
T6	2360852	0	0	0
T7	16541669	36	0	0
T8	5508613	0	0	0
T9	4032855	0	0	0
T10	0	144	0	0
T11	0	117	0	0
T12	0	96	0	0
T13	626353	0	0	0
T14	723000	0	0	0
T15	3765000	0	0	0
T20	0	8	0	0
T21	1130625	0	0	0
T22	64387	0	0	0
T25	858270	7	0	0
T26	742330	6	0	0
T27	2730410	9	0	0
T32	0	8	0	0
T36	0	8	0	0
T39	0	12	0	0
T41	0	1	0	0
T42	0	9	0	0
T43	1276218	7	0	0
T44	0	7	0	0
T45	0	6	0	0
T46	0	2	0	0
T47	1228180	0	0	0
T48	1902330	0	0	0
T49	361013	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	6273782	6263854	0	0
T2	5841676	5831646	0	0
T3	8169146	8166596	0	0
T4	20173764	20110218	0	0
T5	3465586	3462526	0	0
T6	6174536	6171306	0	0
T7	24452902	24426824	0	0
T13	1638154	1635944	0	0
T14	1638800	1636964	0	0
T15	8534000	8531518	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Total	Covered	Percent
Conditions	16	14	87.50
Logical	16	14	87.50
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T50,T16,T51
1	-	Covered	T1,T2,T3

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1299919929	1199050	0	0
DstReqKnown_A	9714182	8851941	0	0
SrcAckBusyChk_A	1299919929	1172	0	0
SrcBusyKnown_A	1299919929	1298056549	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1199050	0	0
T1	184523	391	0	0
T2	171814	1192	0	0
T3	240269	2839	0	0
T4	593346	7922	0	0
T5	101929	0	0	0
T6	181604	0	0	0
T7	719203	3317	0	0
T10	0	18303	0	0
T11	0	1479	0	0
T12	0	5232	0	0
T13	48181	0	0	0
T14	48200	0	0	0
T15	251000	0	0	0
T19	0	1603	0	0
T52	0	1176	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9714182	8851941	0	0
T1	26361	25920	0	0
T2	13744	13321	0	0
T3	2057	1657	0	0
T4	24722	20721	0	0
T5	8493	8086	0	0
T6	422	22	0	0
T7	15140	14724	0	0
T13	507	107	0	0
T14	507	107	0	0
T15	501	101	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1172	0	0
T1	184523	2	0	0
T2	171814	3	0	0
T3	240269	2	0	0
T4	593346	9	0	0
T5	101929	0	0	0
T6	181604	0	0	0
T7	719203	2	0	0
T10	0	21	0	0
T11	0	4	0	0
T12	0	3	0	0
T13	48181	0	0	0
T14	48200	0	0	0
T15	251000	0	0	0
T19	0	2	0	0
T52	0	10	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1298056549	0	0
T1	184523	184231	0	0
T2	171814	171519	0	0
T3	240269	240194	0	0
T4	593346	591477	0	0
T5	101929	101839	0	0
T6	181604	181509	0	0
T7	719203	718436	0	0
T13	48181	48116	0	0
T14	48200	48146	0	0
T15	251000	250927	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T5,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T5,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1299919929	1911476	0	0
DstReqKnown_A	9714182	8851941	0	0
SrcAckBusyChk_A	1299919929	2018	0	0
SrcBusyKnown_A	1299919929	1298056549	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1911476	0	0
T1	184523	2005	0	0
T2	171814	1396	0	0
T3	240269	0	0	0
T4	593346	6153	0	0
T5	101929	1204	0	0
T6	181604	0	0	0
T7	719203	6016	0	0
T10	0	15258	0	0
T11	0	4824	0	0
T13	48181	0	0	0
T14	48200	0	0	0
T15	251000	0	0	0
T27	0	1445	0	0
T48	0	974	0	0
T49	0	1913	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9714182	8851941	0	0
T1	26361	25920	0	0
T2	13744	13321	0	0
T3	2057	1657	0	0
T4	24722	20721	0	0
T5	8493	8086	0	0
T6	422	22	0	0
T7	15140	14724	0	0
T13	507	107	0	0
T14	507	107	0	0
T15	501	101	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	2018	0	0
T1	184523	9	0	0
T2	171814	4	0	0
T3	240269	0	0	0
T4	593346	8	0	0
T5	101929	3	0	0
T6	181604	0	0	0
T7	719203	4	0	0
T10	0	18	0	0
T11	0	13	0	0
T13	48181	0	0	0
T14	48200	0	0	0
T15	251000	0	0	0
T27	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1298056549	0	0
T1	184523	184231	0	0
T2	171814	171519	0	0
T3	240269	240194	0	0
T4	593346	591477	0	0
T5	101929	101839	0	0
T6	181604	181509	0	0
T7	719203	718436	0	0
T13	48181	48116	0	0
T14	48200	48146	0	0
T15	251000	250927	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T3,T31,T19

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T3,T31,T19
1	1	Covered	T3,T31,T19

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T3,T31,T19

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T31,T19
1	1	Covered	T3,T31,T19

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T3,T31,T19
0	0	1	Covered	T3,T31,T19
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T3,T31,T19
0	0	1	Covered	T3,T31,T19
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1299919929	1010991	0	0
DstReqKnown_A	9714182	8851941	0	0
SrcAckBusyChk_A	1299919929	1022	0	0
SrcBusyKnown_A	1299919929	1298056549	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1010991	0	0
T3	240269	2882	0	0
T4	593346	0	0	0
T7	719203	0	0	0
T14	48200	0	0	0
T15	251000	0	0	0
T19	0	2639	0	0
T20	0	979	0	0
T25	85827	0	0	0
T26	74233	0	0	0
T27	273041	0	0	0
T31	0	321	0	0
T32	0	360	0	0
T47	122818	0	0	0
T48	190233	0	0	0
T53	0	729	0	0
T54	0	735	0	0
T55	0	1157	0	0
T56	0	158	0	0
T57	0	284	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9714182	8851941	0	0
T1	26361	25920	0	0
T2	13744	13321	0	0
T3	2057	1657	0	0
T4	24722	20721	0	0
T5	8493	8086	0	0
T6	422	22	0	0
T7	15140	14724	0	0
T13	507	107	0	0
T14	507	107	0	0
T15	501	101	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1022	0	0
T3	240269	2	0	0
T4	593346	0	0	0
T7	719203	0	0	0
T14	48200	0	0	0
T15	251000	0	0	0
T19	0	3	0	0
T20	0	1	0	0
T25	85827	0	0	0
T26	74233	0	0	0
T27	273041	0	0	0
T31	0	1	0	0
T32	0	3	0	0
T47	122818	0	0	0
T48	190233	0	0	0
T53	0	2	0	0
T54	0	2	0	0
T55	0	3	0	0
T56	0	1	0	0
T57	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1298056549	0	0
T1	184523	184231	0	0
T2	171814	171519	0	0
T3	240269	240194	0	0
T4	593346	591477	0	0
T5	101929	101839	0	0
T6	181604	181509	0	0
T7	719203	718436	0	0
T13	48181	48116	0	0
T14	48200	48146	0	0
T15	251000	250927	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T3,T31,T19

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T3,T31,T19
1	1	Covered	T3,T31,T19

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T3,T31,T19

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T31,T19
1	1	Covered	T3,T31,T19

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T3,T31,T19
0	0	1	Covered	T3,T31,T19
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T3,T31,T19
0	0	1	Covered	T3,T31,T19
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1299919929	1002373	0	0
DstReqKnown_A	9714182	8851941	0	0
SrcAckBusyChk_A	1299919929	1031	0	0
SrcBusyKnown_A	1299919929	1298056549	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1002373	0	0
T3	240269	2862	0	0
T4	593346	0	0	0
T7	719203	0	0	0
T14	48200	0	0	0
T15	251000	0	0	0
T19	0	2602	0	0
T20	0	975	0	0
T25	85827	0	0	0
T26	74233	0	0	0
T27	273041	0	0	0
T31	0	307	0	0
T32	0	324	0	0
T47	122818	0	0	0
T48	190233	0	0	0
T53	0	725	0	0
T54	0	731	0	0
T55	0	1137	0	0
T56	0	156	0	0
T57	0	282	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9714182	8851941	0	0
T1	26361	25920	0	0
T2	13744	13321	0	0
T3	2057	1657	0	0
T4	24722	20721	0	0
T5	8493	8086	0	0
T6	422	22	0	0
T7	15140	14724	0	0
T13	507	107	0	0
T14	507	107	0	0
T15	501	101	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1031	0	0
T3	240269	2	0	0
T4	593346	0	0	0
T7	719203	0	0	0
T14	48200	0	0	0
T15	251000	0	0	0
T19	0	3	0	0
T20	0	1	0	0
T25	85827	0	0	0
T26	74233	0	0	0
T27	273041	0	0	0
T31	0	1	0	0
T32	0	3	0	0
T47	122818	0	0	0
T48	190233	0	0	0
T53	0	2	0	0
T54	0	2	0	0
T55	0	3	0	0
T56	0	1	0	0
T57	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1298056549	0	0
T1	184523	184231	0	0
T2	171814	171519	0	0
T3	240269	240194	0	0
T4	593346	591477	0	0
T5	101929	101839	0	0
T6	181604	181509	0	0
T7	719203	718436	0	0
T13	48181	48116	0	0
T14	48200	48146	0	0
T15	251000	250927	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T3,T31,T19

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T3,T31,T19
1	1	Covered	T3,T31,T19

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T3,T31,T19

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T31,T19
1	1	Covered	T3,T31,T19

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T3,T31,T19
0	0	1	Covered	T3,T31,T19
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T3,T31,T19
0	0	1	Covered	T3,T31,T19
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1299919929	977665	0	0
DstReqKnown_A	9714182	8851941	0	0
SrcAckBusyChk_A	1299919929	996	0	0
SrcBusyKnown_A	1299919929	1298056549	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	977665	0	0
T3	240269	2853	0	0
T4	593346	0	0	0
T7	719203	0	0	0
T14	48200	0	0	0
T15	251000	0	0	0
T19	0	2580	0	0
T20	0	969	0	0
T25	85827	0	0	0
T26	74233	0	0	0
T27	273041	0	0	0
T31	0	292	0	0
T32	0	332	0	0
T47	122818	0	0	0
T48	190233	0	0	0
T53	0	721	0	0
T54	0	727	0	0
T55	0	1115	0	0
T56	0	146	0	0
T57	0	280	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9714182	8851941	0	0
T1	26361	25920	0	0
T2	13744	13321	0	0
T3	2057	1657	0	0
T4	24722	20721	0	0
T5	8493	8086	0	0
T6	422	22	0	0
T7	15140	14724	0	0
T13	507	107	0	0
T14	507	107	0	0
T15	501	101	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	996	0	0
T3	240269	2	0	0
T4	593346	0	0	0
T7	719203	0	0	0
T14	48200	0	0	0
T15	251000	0	0	0
T19	0	3	0	0
T20	0	1	0	0
T25	85827	0	0	0
T26	74233	0	0	0
T27	273041	0	0	0
T31	0	1	0	0
T32	0	3	0	0
T47	122818	0	0	0
T48	190233	0	0	0
T53	0	2	0	0
T54	0	2	0	0
T55	0	3	0	0
T56	0	1	0	0
T57	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1298056549	0	0
T1	184523	184231	0	0
T2	171814	171519	0	0
T3	240269	240194	0	0
T4	593346	591477	0	0
T5	101929	101839	0	0
T6	181604	181509	0	0
T7	719203	718436	0	0
T13	48181	48116	0	0
T14	48200	48146	0	0
T15	251000	250927	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T21,T22,T23

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T21,T22,T23
1	1	Covered	T21,T22,T23

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T21,T22,T23

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T21,T22,T23
1	1	Covered	T21,T22,T23

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T21,T22,T23
0	0	1	Covered	T21,T22,T23
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T21,T22,T23
0	0	1	Covered	T21,T22,T23
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1299919929	2590790	0	0
DstReqKnown_A	9714182	8851941	0	0
SrcAckBusyChk_A	1299919929	2998	0	0
SrcBusyKnown_A	1299919929	1298056549	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	2590790	0	0
T9	448095	0	0	0
T10	116790	0	0	0
T11	397094	0	0	0
T21	125625	17487	0	0
T22	64387	9102	0	0
T23	0	16784	0	0
T49	361013	0	0	0
T58	0	32327	0	0
T59	0	8031	0	0
T60	0	37006	0	0
T61	0	8752	0	0
T62	0	34684	0	0
T63	0	31676	0	0
T64	0	8894	0	0
T65	255969	0	0	0
T66	55893	0	0	0
T67	53311	0	0	0
T68	65763	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9714182	8851941	0	0
T1	26361	25920	0	0
T2	13744	13321	0	0
T3	2057	1657	0	0
T4	24722	20721	0	0
T5	8493	8086	0	0
T6	422	22	0	0
T7	15140	14724	0	0
T13	507	107	0	0
T14	507	107	0	0
T15	501	101	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	2998	0	0
T9	448095	0	0	0
T10	116790	0	0	0
T11	397094	0	0	0
T21	125625	20	0	0
T22	64387	20	0	0
T23	0	20	0	0
T49	361013	0	0	0
T58	0	20	0	0
T59	0	20	0	0
T60	0	20	0	0
T61	0	20	0	0
T62	0	20	0	0
T63	0	20	0	0
T64	0	20	0	0
T65	255969	0	0	0
T66	55893	0	0	0
T67	53311	0	0	0
T68	65763	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1298056549	0	0
T1	184523	184231	0	0
T2	171814	171519	0	0
T3	240269	240194	0	0
T4	593346	591477	0	0
T5	101929	101839	0	0
T6	181604	181509	0	0
T7	719203	718436	0	0
T13	48181	48116	0	0
T14	48200	48146	0	0
T15	251000	250927	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T13,T4,T14

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T13,T4,T14
1	1	Covered	T13,T4,T14

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T13,T4,T14

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T13,T4,T14
1	1	Covered	T13,T4,T14

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T13,T4,T14
0	0	1	Covered	T13,T4,T14
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T13,T4,T14
0	0	1	Covered	T13,T4,T14
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1299919929	5310131	0	0
DstReqKnown_A	9714182	8851941	0	0
SrcAckBusyChk_A	1299919929	6664	0	0
SrcBusyKnown_A	1299919929	1298056549	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	5310131	0	0
T3	240269	0	0	0
T4	593346	17306	0	0
T7	719203	0	0	0
T10	0	17325	0	0
T13	48181	6481	0	0
T14	48200	6531	0	0
T15	251000	36432	0	0
T21	0	751	0	0
T22	0	384	0	0
T25	85827	0	0	0
T27	273041	0	0	0
T47	122818	16143	0	0
T48	190233	0	0	0
T65	0	33245	0	0
T68	0	8375	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9714182	8851941	0	0
T1	26361	25920	0	0
T2	13744	13321	0	0
T3	2057	1657	0	0
T4	24722	20721	0	0
T5	8493	8086	0	0
T6	422	22	0	0
T7	15140	14724	0	0
T13	507	107	0	0
T14	507	107	0	0
T15	501	101	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	6664	0	0
T3	240269	0	0	0
T4	593346	20	0	0
T7	719203	0	0	0
T10	0	20	0	0
T13	48181	20	0	0
T14	48200	20	0	0
T15	251000	20	0	0
T21	0	1	0	0
T22	0	1	0	0
T25	85827	0	0	0
T27	273041	0	0	0
T47	122818	20	0	0
T48	190233	0	0	0
T65	0	20	0	0
T68	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1298056549	0	0
T1	184523	184231	0	0
T2	171814	171519	0	0
T3	240269	240194	0	0
T4	593346	591477	0	0
T5	101929	101839	0	0
T6	181604	181509	0	0
T7	719203	718436	0	0
T13	48181	48116	0	0
T14	48200	48146	0	0
T15	251000	250927	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T5,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T5,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1299919929	6516556	0	0
DstReqKnown_A	9714182	8851941	0	0
SrcAckBusyChk_A	1299919929	7863	0	0
SrcBusyKnown_A	1299919929	1298056549	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	6516556	0	0
T1	184523	1978	0	0
T2	171814	1704	0	0
T3	240269	0	0	0
T4	593346	25897	0	0
T5	101929	1393	0	0
T6	181604	0	0	0
T7	719203	6162	0	0
T13	48181	6757	0	0
T14	48200	6939	0	0
T15	251000	36512	0	0
T27	0	1481	0	0
T47	0	16223	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9714182	8851941	0	0
T1	26361	25920	0	0
T2	13744	13321	0	0
T3	2057	1657	0	0
T4	24722	20721	0	0
T5	8493	8086	0	0
T6	422	22	0	0
T7	15140	14724	0	0
T13	507	107	0	0
T14	507	107	0	0
T15	501	101	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	7863	0	0
T1	184523	9	0	0
T2	171814	4	0	0
T3	240269	0	0	0
T4	593346	30	0	0
T5	101929	3	0	0
T6	181604	0	0	0
T7	719203	4	0	0
T13	48181	20	0	0
T14	48200	20	0	0
T15	251000	20	0	0
T27	0	1	0	0
T47	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1298056549	0	0
T1	184523	184231	0	0
T2	171814	171519	0	0
T3	240269	240194	0	0
T4	593346	591477	0	0
T5	101929	101839	0	0
T6	181604	181509	0	0
T7	719203	718436	0	0
T13	48181	48116	0	0
T14	48200	48146	0	0
T15	251000	250927	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T13,T4,T14

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T13,T4,T14
1	1	Covered	T13,T4,T14

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T13,T4,T14

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T13,T4,T14
1	1	Covered	T13,T4,T14

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T13,T4,T14
0	0	1	Covered	T13,T4,T14
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T13,T4,T14
0	0	1	Covered	T13,T4,T14
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1299919929	5262886	0	0
DstReqKnown_A	9714182	8851941	0	0
SrcAckBusyChk_A	1299919929	6553	0	0
SrcBusyKnown_A	1299919929	1298056549	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	5262886	0	0
T3	240269	0	0	0
T4	593346	17483	0	0
T7	719203	0	0	0
T10	0	17365	0	0
T13	48181	6627	0	0
T14	48200	6713	0	0
T15	251000	36472	0	0
T25	85827	0	0	0
T27	273041	0	0	0
T47	122818	16183	0	0
T48	190233	0	0	0
T65	0	33285	0	0
T68	0	8524	0	0
T69	0	3499	0	0
T70	0	7840	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9714182	8851941	0	0
T1	26361	25920	0	0
T2	13744	13321	0	0
T3	2057	1657	0	0
T4	24722	20721	0	0
T5	8493	8086	0	0
T6	422	22	0	0
T7	15140	14724	0	0
T13	507	107	0	0
T14	507	107	0	0
T15	501	101	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	6553	0	0
T3	240269	0	0	0
T4	593346	20	0	0
T7	719203	0	0	0
T10	0	20	0	0
T13	48181	20	0	0
T14	48200	20	0	0
T15	251000	20	0	0
T25	85827	0	0	0
T27	273041	0	0	0
T47	122818	20	0	0
T48	190233	0	0	0
T65	0	20	0	0
T68	0	20	0	0
T69	0	20	0	0
T70	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1298056549	0	0
T1	184523	184231	0	0
T2	171814	171519	0	0
T3	240269	240194	0	0
T4	593346	591477	0	0
T5	101929	101839	0	0
T6	181604	181509	0	0
T7	719203	718436	0	0
T13	48181	48116	0	0
T14	48200	48146	0	0
T15	251000	250927	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T8,T9,T24

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T8,T9,T24
1	1	Covered	T8,T9,T24

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T8,T9,T24

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T8,T9,T24
1	1	Covered	T8,T9,T24

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T8,T9,T24
0	0	1	Covered	T8,T9,T24
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T8,T9,T24
0	0	1	Covered	T8,T9,T24
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1299919929	971828	0	0
DstReqKnown_A	9714182	8851941	0	0
SrcAckBusyChk_A	1299919929	1022	0	0
SrcBusyKnown_A	1299919929	1298056549	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	971828	0	0
T8	500783	1904	0	0
T9	448095	1426	0	0
T10	116790	0	0	0
T21	125625	0	0	0
T22	64387	0	0	0
T24	0	280	0	0
T32	0	454	0	0
T33	0	497	0	0
T36	0	440	0	0
T37	0	1000	0	0
T38	0	610	0	0
T43	141802	0	0	0
T49	361013	0	0	0
T65	255969	0	0	0
T66	55893	0	0	0
T67	53311	0	0	0
T71	0	2000	0	0
T72	0	492	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9714182	8851941	0	0
T1	26361	25920	0	0
T2	13744	13321	0	0
T3	2057	1657	0	0
T4	24722	20721	0	0
T5	8493	8086	0	0
T6	422	22	0	0
T7	15140	14724	0	0
T13	507	107	0	0
T14	507	107	0	0
T15	501	101	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1022	0	0
T8	500783	1	0	0
T9	448095	1	0	0
T10	116790	0	0	0
T21	125625	0	0	0
T22	64387	0	0	0
T24	0	1	0	0
T32	0	4	0	0
T33	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T43	141802	0	0	0
T49	361013	0	0	0
T65	255969	0	0	0
T66	55893	0	0	0
T67	53311	0	0	0
T71	0	1	0	0
T72	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1298056549	0	0
T1	184523	184231	0	0
T2	171814	171519	0	0
T3	240269	240194	0	0
T4	593346	591477	0	0
T5	101929	101839	0	0
T6	181604	181509	0	0
T7	719203	718436	0	0
T13	48181	48116	0	0
T14	48200	48146	0	0
T15	251000	250927	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T5,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T5,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1299919929	1871810	0	0
DstReqKnown_A	9714182	8851941	0	0
SrcAckBusyChk_A	1299919929	1997	0	0
SrcBusyKnown_A	1299919929	1298056549	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1871810	0	0
T1	184523	1947	0	0
T2	171814	1359	0	0
T3	240269	0	0	0
T4	593346	5398	0	0
T5	101929	1171	0	0
T6	181604	0	0	0
T7	719203	6008	0	0
T8	0	1898	0	0
T9	0	1418	0	0
T10	0	15222	0	0
T11	0	4736	0	0
T13	48181	0	0	0
T14	48200	0	0	0
T15	251000	0	0	0
T27	0	1443	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9714182	8851941	0	0
T1	26361	25920	0	0
T2	13744	13321	0	0
T3	2057	1657	0	0
T4	24722	20721	0	0
T5	8493	8086	0	0
T6	422	22	0	0
T7	15140	14724	0	0
T13	507	107	0	0
T14	507	107	0	0
T15	501	101	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1997	0	0
T1	184523	9	0	0
T2	171814	4	0	0
T3	240269	0	0	0
T4	593346	7	0	0
T5	101929	3	0	0
T6	181604	0	0	0
T7	719203	4	0	0
T8	0	1	0	0
T9	0	1	0	0
T10	0	18	0	0
T11	0	13	0	0
T13	48181	0	0	0
T14	48200	0	0	0
T15	251000	0	0	0
T27	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1298056549	0	0
T1	184523	184231	0	0
T2	171814	171519	0	0
T3	240269	240194	0	0
T4	593346	591477	0	0
T5	101929	101839	0	0
T6	181604	181509	0	0
T7	719203	718436	0	0
T13	48181	48116	0	0
T14	48200	48146	0	0
T15	251000	250927	0	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T4,T25,T26

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T4,T25,T26
1	1	Covered	T4,T25,T26

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T4,T25,T26

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T25,T26
1	1	Covered	T4,T25,T26

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T4,T25,T26
0	0	1	Covered	T4,T25,T26
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T4,T25,T26
0	0	1	Covered	T4,T25,T26
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1299919929	1321237	0	0
DstReqKnown_A	9714182	8851941	0	0
SrcAckBusyChk_A	1299919929	1347	0	0
SrcBusyKnown_A	1299919929	1298056549	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1321237	0	0
T4	593346	5242	0	0
T7	719203	0	0	0
T8	500783	0	0	0
T14	48200	0	0	0
T15	251000	0	0	0
T20	0	4477	0	0
T25	85827	1620	0	0
T26	74233	1318	0	0
T27	273041	0	0	0
T32	0	592	0	0
T36	0	1977	0	0
T43	0	3300	0	0
T44	0	6471	0	0
T45	0	2677	0	0
T46	0	1554	0	0
T47	122818	0	0	0
T48	190233	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9714182	8851941	0	0
T1	26361	25920	0	0
T2	13744	13321	0	0
T3	2057	1657	0	0
T4	24722	20721	0	0
T5	8493	8086	0	0
T6	422	22	0	0
T7	15140	14724	0	0
T13	507	107	0	0
T14	507	107	0	0
T15	501	101	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1347	0	0
T4	593346	6	0	0
T7	719203	0	0	0
T8	500783	0	0	0
T14	48200	0	0	0
T15	251000	0	0	0
T20	0	5	0	0
T25	85827	4	0	0
T26	74233	3	0	0
T27	273041	0	0	0
T32	0	5	0	0
T36	0	5	0	0
T43	0	4	0	0
T44	0	4	0	0
T45	0	3	0	0
T46	0	1	0	0
T47	122818	0	0	0
T48	190233	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1298056549	0	0
T1	184523	184231	0	0
T2	171814	171519	0	0
T3	240269	240194	0	0
T4	593346	591477	0	0
T5	101929	101839	0	0
T6	181604	181509	0	0
T7	719203	718436	0	0
T13	48181	48116	0	0
T14	48200	48146	0	0
T15	251000	250927	0	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T4,T25,T26

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T4,T25,T26
1	1	Covered	T4,T25,T26

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T4,T25,T26

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T25,T26
1	1	Covered	T4,T25,T26

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T4,T25,T26
0	0	1	Covered	T4,T25,T26
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T4,T25,T26
0	0	1	Covered	T4,T25,T26
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1299919929	1182954	0	0
DstReqKnown_A	9714182	8851941	0	0
SrcAckBusyChk_A	1299919929	1198	0	0
SrcBusyKnown_A	1299919929	1298056549	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1182954	0	0
T4	593346	2611	0	0
T7	719203	0	0	0
T8	500783	0	0	0
T14	48200	0	0	0
T15	251000	0	0	0
T20	0	2475	0	0
T25	85827	1239	0	0
T26	74233	1312	0	0
T27	273041	0	0	0
T32	0	334	0	0
T36	0	1201	0	0
T43	0	2413	0	0
T44	0	4965	0	0
T45	0	2654	0	0
T46	0	1546	0	0
T47	122818	0	0	0
T48	190233	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9714182	8851941	0	0
T1	26361	25920	0	0
T2	13744	13321	0	0
T3	2057	1657	0	0
T4	24722	20721	0	0
T5	8493	8086	0	0
T6	422	22	0	0
T7	15140	14724	0	0
T13	507	107	0	0
T14	507	107	0	0
T15	501	101	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1198	0	0
T4	593346	3	0	0
T7	719203	0	0	0
T8	500783	0	0	0
T14	48200	0	0	0
T15	251000	0	0	0
T20	0	3	0	0
T25	85827	3	0	0
T26	74233	3	0	0
T27	273041	0	0	0
T32	0	3	0	0
T36	0	3	0	0
T43	0	3	0	0
T44	0	3	0	0
T45	0	3	0	0
T46	0	1	0	0
T47	122818	0	0	0
T48	190233	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1298056549	0	0
T1	184523	184231	0	0
T2	171814	171519	0	0
T3	240269	240194	0	0
T4	593346	591477	0	0
T5	101929	101839	0	0
T6	181604	181509	0	0
T7	719203	718436	0	0
T13	48181	48116	0	0
T14	48200	48146	0	0
T15	251000	250927	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T7,T27,T11

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T7,T27,T11
1	1	Covered	T7,T27,T11

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T7,T27,T11

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T27,T11
1	1	Covered	T7,T27,T11

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T7,T27,T11
0	0	1	Covered	T7,T27,T11
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T7,T27,T11
0	0	1	Covered	T7,T27,T11
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1299919929	7535840	0	0
DstReqKnown_A	9714182	8851941	0	0
SrcAckBusyChk_A	1299919929	7491	0	0
SrcBusyKnown_A	1299919929	1298056549	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	7535840	0	0
T7	719203	112432	0	0
T8	500783	0	0	0
T9	448095	0	0	0
T11	0	28697	0	0
T21	125625	0	0	0
T25	85827	0	0	0
T26	74233	0	0	0
T27	273041	88035	0	0
T39	0	124562	0	0
T40	0	75036	0	0
T41	0	35673	0	0
T42	0	26391	0	0
T43	141802	0	0	0
T47	122818	0	0	0
T48	190233	0	0	0
T73	0	87982	0	0
T74	0	25869	0	0
T75	0	86163	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9714182	8851941	0	0
T1	26361	25920	0	0
T2	13744	13321	0	0
T3	2057	1657	0	0
T4	24722	20721	0	0
T5	8493	8086	0	0
T6	422	22	0	0
T7	15140	14724	0	0
T13	507	107	0	0
T14	507	107	0	0
T15	501	101	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	7491	0	0
T7	719203	70	0	0
T8	500783	0	0	0
T9	448095	0	0	0
T11	0	71	0	0
T21	125625	0	0	0
T25	85827	0	0	0
T26	74233	0	0	0
T27	273041	51	0	0
T39	0	74	0	0
T40	0	80	0	0
T41	0	84	0	0
T42	0	64	0	0
T43	141802	0	0	0
T47	122818	0	0	0
T48	190233	0	0	0
T73	0	51	0	0
T74	0	66	0	0
T75	0	51	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1298056549	0	0
T1	184523	184231	0	0
T2	171814	171519	0	0
T3	240269	240194	0	0
T4	593346	591477	0	0
T5	101929	101839	0	0
T6	181604	181509	0	0
T7	719203	718436	0	0
T13	48181	48116	0	0
T14	48200	48146	0	0
T15	251000	250927	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T7,T27,T11

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T7,T27,T11
1	1	Covered	T7,T27,T11

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T7,T27,T11

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T27,T11
1	1	Covered	T7,T27,T11

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T7,T27,T11
0	0	1	Covered	T7,T27,T11
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T7,T27,T11
0	0	1	Covered	T7,T27,T11
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1299919929	7674399	0	0
DstReqKnown_A	9714182	8851941	0	0
SrcAckBusyChk_A	1299919929	7565	0	0
SrcBusyKnown_A	1299919929	1298056549	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	7674399	0	0
T7	719203	99826	0	0
T8	500783	0	0	0
T9	448095	0	0	0
T11	0	29478	0	0
T21	125625	0	0	0
T25	85827	0	0	0
T26	74233	0	0	0
T27	273041	87825	0	0
T39	0	143034	0	0
T40	0	57573	0	0
T41	0	25023	0	0
T42	0	26129	0	0
T43	141802	0	0	0
T47	122818	0	0	0
T48	190233	0	0	0
T73	0	87242	0	0
T74	0	24767	0	0
T75	0	85953	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9714182	8851941	0	0
T1	26361	25920	0	0
T2	13744	13321	0	0
T3	2057	1657	0	0
T4	24722	20721	0	0
T5	8493	8086	0	0
T6	422	22	0	0
T7	15140	14724	0	0
T13	507	107	0	0
T14	507	107	0	0
T15	501	101	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	7565	0	0
T7	719203	62	0	0
T8	500783	0	0	0
T9	448095	0	0	0
T11	0	75	0	0
T21	125625	0	0	0
T25	85827	0	0	0
T26	74233	0	0	0
T27	273041	51	0	0
T39	0	85	0	0
T40	0	62	0	0
T41	0	60	0	0
T42	0	64	0	0
T43	141802	0	0	0
T47	122818	0	0	0
T48	190233	0	0	0
T73	0	51	0	0
T74	0	66	0	0
T75	0	51	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1298056549	0	0
T1	184523	184231	0	0
T2	171814	171519	0	0
T3	240269	240194	0	0
T4	593346	591477	0	0
T5	101929	101839	0	0
T6	181604	181509	0	0
T7	719203	718436	0	0
T13	48181	48116	0	0
T14	48200	48146	0	0
T15	251000	250927	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T7,T27,T11

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T7,T27,T11
1	1	Covered	T7,T27,T11

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T7,T27,T11

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T27,T11
1	1	Covered	T7,T27,T11

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T7,T27,T11
0	0	1	Covered	T7,T27,T11
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T7,T27,T11
0	0	1	Covered	T7,T27,T11
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1299919929	7532164	0	0
DstReqKnown_A	9714182	8851941	0	0
SrcAckBusyChk_A	1299919929	7518	0	0
SrcBusyKnown_A	1299919929	1298056549	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	7532164	0	0
T7	719203	96749	0	0
T8	500783	0	0	0
T9	448095	0	0	0
T11	0	28074	0	0
T21	125625	0	0	0
T25	85827	0	0	0
T26	74233	0	0	0
T27	273041	87615	0	0
T39	0	126870	0	0
T40	0	65821	0	0
T41	0	27578	0	0
T42	0	25867	0	0
T43	141802	0	0	0
T47	122818	0	0	0
T48	190233	0	0	0
T73	0	86543	0	0
T74	0	20712	0	0
T75	0	85743	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9714182	8851941	0	0
T1	26361	25920	0	0
T2	13744	13321	0	0
T3	2057	1657	0	0
T4	24722	20721	0	0
T5	8493	8086	0	0
T6	422	22	0	0
T7	15140	14724	0	0
T13	507	107	0	0
T14	507	107	0	0
T15	501	101	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	7518	0	0
T7	719203	60	0	0
T8	500783	0	0	0
T9	448095	0	0	0
T11	0	75	0	0
T21	125625	0	0	0
T25	85827	0	0	0
T26	74233	0	0	0
T27	273041	51	0	0
T39	0	75	0	0
T40	0	71	0	0
T41	0	66	0	0
T42	0	64	0	0
T43	141802	0	0	0
T47	122818	0	0	0
T48	190233	0	0	0
T73	0	51	0	0
T74	0	58	0	0
T75	0	51	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1298056549	0	0
T1	184523	184231	0	0
T2	171814	171519	0	0
T3	240269	240194	0	0
T4	593346	591477	0	0
T5	101929	101839	0	0
T6	181604	181509	0	0
T7	719203	718436	0	0
T13	48181	48116	0	0
T14	48200	48146	0	0
T15	251000	250927	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T7,T27,T11

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T7,T27,T11
1	1	Covered	T7,T27,T11

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T7,T27,T11

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T27,T11
1	1	Covered	T7,T27,T11

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T7,T27,T11
0	0	1	Covered	T7,T27,T11
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T7,T27,T11
0	0	1	Covered	T7,T27,T11
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1299919929	7394894	0	0
DstReqKnown_A	9714182	8851941	0	0
SrcAckBusyChk_A	1299919929	7546	0	0
SrcBusyKnown_A	1299919929	1298056549	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	7394894	0	0
T7	719203	102621	0	0
T8	500783	0	0	0
T9	448095	0	0	0
T11	0	29354	0	0
T21	125625	0	0	0
T25	85827	0	0	0
T26	74233	0	0	0
T27	273041	87405	0	0
T39	0	147766	0	0
T40	0	70274	0	0
T41	0	34853	0	0
T42	0	20502	0	0
T43	141802	0	0	0
T47	122818	0	0	0
T48	190233	0	0	0
T73	0	85794	0	0
T74	0	23223	0	0
T75	0	85533	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9714182	8851941	0	0
T1	26361	25920	0	0
T2	13744	13321	0	0
T3	2057	1657	0	0
T4	24722	20721	0	0
T5	8493	8086	0	0
T6	422	22	0	0
T7	15140	14724	0	0
T13	507	107	0	0
T14	507	107	0	0
T15	501	101	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	7546	0	0
T7	719203	64	0	0
T8	500783	0	0	0
T9	448095	0	0	0
T11	0	79	0	0
T21	125625	0	0	0
T25	85827	0	0	0
T26	74233	0	0	0
T27	273041	51	0	0
T39	0	88	0	0
T40	0	76	0	0
T41	0	84	0	0
T42	0	51	0	0
T43	141802	0	0	0
T47	122818	0	0	0
T48	190233	0	0	0
T73	0	51	0	0
T74	0	66	0	0
T75	0	51	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1298056549	0	0
T1	184523	184231	0	0
T2	171814	171519	0	0
T3	240269	240194	0	0
T4	593346	591477	0	0
T5	101929	101839	0	0
T6	181604	181509	0	0
T7	719203	718436	0	0
T13	48181	48116	0	0
T14	48200	48146	0	0
T15	251000	250927	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T7,T27,T11

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T7,T27,T11
1	1	Covered	T7,T27,T11

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T7,T27,T11

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T27,T11
1	1	Covered	T7,T27,T11

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T7,T27,T11
0	0	1	Covered	T7,T27,T11
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T7,T27,T11
0	0	1	Covered	T7,T27,T11
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1299919929	1255550	0	0
DstReqKnown_A	9714182	8851941	0	0
SrcAckBusyChk_A	1299919929	1283	0	0
SrcBusyKnown_A	1299919929	1298056549	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1255550	0	0
T7	719203	6168	0	0
T8	500783	0	0	0
T9	448095	0	0	0
T11	0	4994	0	0
T21	125625	0	0	0
T25	85827	0	0	0
T26	74233	0	0	0
T27	273041	1483	0	0
T39	0	21764	0	0
T40	0	2645	0	0
T41	0	358	0	0
T42	0	479	0	0
T43	141802	0	0	0
T47	122818	0	0	0
T48	190233	0	0	0
T73	0	1962	0	0
T74	0	3010	0	0
T75	0	1959	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9714182	8851941	0	0
T1	26361	25920	0	0
T2	13744	13321	0	0
T3	2057	1657	0	0
T4	24722	20721	0	0
T5	8493	8086	0	0
T6	422	22	0	0
T7	15140	14724	0	0
T13	507	107	0	0
T14	507	107	0	0
T15	501	101	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1283	0	0
T7	719203	4	0	0
T8	500783	0	0	0
T9	448095	0	0	0
T11	0	13	0	0
T21	125625	0	0	0
T25	85827	0	0	0
T26	74233	0	0	0
T27	273041	1	0	0
T39	0	12	0	0
T40	0	3	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	141802	0	0	0
T47	122818	0	0	0
T48	190233	0	0	0
T73	0	1	0	0
T74	0	8	0	0
T75	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1298056549	0	0
T1	184523	184231	0	0
T2	171814	171519	0	0
T3	240269	240194	0	0
T4	593346	591477	0	0
T5	101929	101839	0	0
T6	181604	181509	0	0
T7	719203	718436	0	0
T13	48181	48116	0	0
T14	48200	48146	0	0
T15	251000	250927	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T7,T27,T11

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T7,T27,T11
1	1	Covered	T7,T27,T11

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T7,T27,T11

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T27,T11
1	1	Covered	T7,T27,T11

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T7,T27,T11
0	0	1	Covered	T7,T27,T11
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T7,T27,T11
0	0	1	Covered	T7,T27,T11
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1299919929	1195730	0	0
DstReqKnown_A	9714182	8851941	0	0
SrcAckBusyChk_A	1299919929	1231	0	0
SrcBusyKnown_A	1299919929	1298056549	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1195730	0	0
T7	719203	6128	0	0
T8	500783	0	0	0
T9	448095	0	0	0
T11	0	4546	0	0
T21	125625	0	0	0
T25	85827	0	0	0
T26	74233	0	0	0
T27	273041	1473	0	0
T39	0	21644	0	0
T40	0	2615	0	0
T41	0	348	0	0
T42	0	469	0	0
T43	141802	0	0	0
T47	122818	0	0	0
T48	190233	0	0	0
T73	0	1925	0	0
T74	0	2730	0	0
T75	0	1949	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9714182	8851941	0	0
T1	26361	25920	0	0
T2	13744	13321	0	0
T3	2057	1657	0	0
T4	24722	20721	0	0
T5	8493	8086	0	0
T6	422	22	0	0
T7	15140	14724	0	0
T13	507	107	0	0
T14	507	107	0	0
T15	501	101	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1231	0	0
T7	719203	4	0	0
T8	500783	0	0	0
T9	448095	0	0	0
T11	0	13	0	0
T21	125625	0	0	0
T25	85827	0	0	0
T26	74233	0	0	0
T27	273041	1	0	0
T39	0	12	0	0
T40	0	3	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	141802	0	0	0
T47	122818	0	0	0
T48	190233	0	0	0
T73	0	1	0	0
T74	0	8	0	0
T75	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1298056549	0	0
T1	184523	184231	0	0
T2	171814	171519	0	0
T3	240269	240194	0	0
T4	593346	591477	0	0
T5	101929	101839	0	0
T6	181604	181509	0	0
T7	719203	718436	0	0
T13	48181	48116	0	0
T14	48200	48146	0	0
T15	251000	250927	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T7,T27,T11

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T7,T27,T11
1	1	Covered	T7,T27,T11

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T7,T27,T11

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T27,T11
1	1	Covered	T7,T27,T11

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T7,T27,T11
0	0	1	Covered	T7,T27,T11
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T7,T27,T11
0	0	1	Covered	T7,T27,T11
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1299919929	1202557	0	0
DstReqKnown_A	9714182	8851941	0	0
SrcAckBusyChk_A	1299919929	1251	0	0
SrcBusyKnown_A	1299919929	1298056549	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1202557	0	0
T7	719203	6088	0	0
T8	500783	0	0	0
T9	448095	0	0	0
T11	0	4081	0	0
T21	125625	0	0	0
T25	85827	0	0	0
T26	74233	0	0	0
T27	273041	1463	0	0
T39	0	21524	0	0
T40	0	2585	0	0
T41	0	338	0	0
T42	0	459	0	0
T43	141802	0	0	0
T47	122818	0	0	0
T48	190233	0	0	0
T73	0	1902	0	0
T74	0	2458	0	0
T75	0	1939	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9714182	8851941	0	0
T1	26361	25920	0	0
T2	13744	13321	0	0
T3	2057	1657	0	0
T4	24722	20721	0	0
T5	8493	8086	0	0
T6	422	22	0	0
T7	15140	14724	0	0
T13	507	107	0	0
T14	507	107	0	0
T15	501	101	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1251	0	0
T7	719203	4	0	0
T8	500783	0	0	0
T9	448095	0	0	0
T11	0	13	0	0
T21	125625	0	0	0
T25	85827	0	0	0
T26	74233	0	0	0
T27	273041	1	0	0
T39	0	12	0	0
T40	0	3	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	141802	0	0	0
T47	122818	0	0	0
T48	190233	0	0	0
T73	0	1	0	0
T74	0	8	0	0
T75	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1298056549	0	0
T1	184523	184231	0	0
T2	171814	171519	0	0
T3	240269	240194	0	0
T4	593346	591477	0	0
T5	101929	101839	0	0
T6	181604	181509	0	0
T7	719203	718436	0	0
T13	48181	48116	0	0
T14	48200	48146	0	0
T15	251000	250927	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T7,T27,T11

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T7,T27,T11
1	1	Covered	T7,T27,T11

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T7,T27,T11

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T27,T11
1	1	Covered	T7,T27,T11

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T7,T27,T11
0	0	1	Covered	T7,T27,T11
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T7,T27,T11
0	0	1	Covered	T7,T27,T11
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1299919929	1188861	0	0
DstReqKnown_A	9714182	8851941	0	0
SrcAckBusyChk_A	1299919929	1238	0	0
SrcBusyKnown_A	1299919929	1298056549	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1188861	0	0
T7	719203	6048	0	0
T8	500783	0	0	0
T9	448095	0	0	0
T11	0	4200	0	0
T21	125625	0	0	0
T25	85827	0	0	0
T26	74233	0	0	0
T27	273041	1453	0	0
T39	0	21404	0	0
T40	0	2555	0	0
T41	0	328	0	0
T42	0	449	0	0
T43	141802	0	0	0
T47	122818	0	0	0
T48	190233	0	0	0
T73	0	1862	0	0
T74	0	2756	0	0
T75	0	1929	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9714182	8851941	0	0
T1	26361	25920	0	0
T2	13744	13321	0	0
T3	2057	1657	0	0
T4	24722	20721	0	0
T5	8493	8086	0	0
T6	422	22	0	0
T7	15140	14724	0	0
T13	507	107	0	0
T14	507	107	0	0
T15	501	101	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1238	0	0
T7	719203	4	0	0
T8	500783	0	0	0
T9	448095	0	0	0
T11	0	13	0	0
T21	125625	0	0	0
T25	85827	0	0	0
T26	74233	0	0	0
T27	273041	1	0	0
T39	0	12	0	0
T40	0	3	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	141802	0	0	0
T47	122818	0	0	0
T48	190233	0	0	0
T73	0	1	0	0
T74	0	8	0	0
T75	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1298056549	0	0
T1	184523	184231	0	0
T2	171814	171519	0	0
T3	240269	240194	0	0
T4	593346	591477	0	0
T5	101929	101839	0	0
T6	181604	181509	0	0
T7	719203	718436	0	0
T13	48181	48116	0	0
T14	48200	48146	0	0
T15	251000	250927	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T5,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T5,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1299919929	8188171	0	0
DstReqKnown_A	9714182	8851941	0	0
SrcAckBusyChk_A	1299919929	8149	0	0
SrcBusyKnown_A	1299919929	1298056549	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	8188171	0	0
T1	184523	2139	0	0
T2	171814	1729	0	0
T3	240269	0	0	0
T4	593346	6215	0	0
T5	101929	1433	0	0
T6	181604	0	0	0
T7	719203	112548	0	0
T10	0	15690	0	0
T11	0	28901	0	0
T12	0	19626	0	0
T13	48181	0	0	0
T14	48200	0	0	0
T15	251000	0	0	0
T27	0	88131	0	0
T42	0	26513	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9714182	8851941	0	0
T1	26361	25920	0	0
T2	13744	13321	0	0
T3	2057	1657	0	0
T4	24722	20721	0	0
T5	8493	8086	0	0
T6	422	22	0	0
T7	15140	14724	0	0
T13	507	107	0	0
T14	507	107	0	0
T15	501	101	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	8149	0	0
T1	184523	9	0	0
T2	171814	4	0	0
T3	240269	0	0	0
T4	593346	7	0	0
T5	101929	3	0	0
T6	181604	0	0	0
T7	719203	70	0	0
T10	0	18	0	0
T11	0	71	0	0
T12	0	12	0	0
T13	48181	0	0	0
T14	48200	0	0	0
T15	251000	0	0	0
T27	0	51	0	0
T42	0	64	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1298056549	0	0
T1	184523	184231	0	0
T2	171814	171519	0	0
T3	240269	240194	0	0
T4	593346	591477	0	0
T5	101929	101839	0	0
T6	181604	181509	0	0
T7	719203	718436	0	0
T13	48181	48116	0	0
T14	48200	48146	0	0
T15	251000	250927	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T5,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T5,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1299919929	8303557	0	0
DstReqKnown_A	9714182	8851941	0	0
SrcAckBusyChk_A	1299919929	8175	0	0
SrcBusyKnown_A	1299919929	1298056549	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	8303557	0	0
T1	184523	2074	0	0
T2	171814	1694	0	0
T3	240269	0	0	0
T4	593346	6140	0	0
T5	101929	1420	0	0
T6	181604	0	0	0
T7	719203	99926	0	0
T10	0	15654	0	0
T11	0	29752	0	0
T12	0	19544	0	0
T13	48181	0	0	0
T14	48200	0	0	0
T15	251000	0	0	0
T27	0	87921	0	0
T42	0	26251	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9714182	8851941	0	0
T1	26361	25920	0	0
T2	13744	13321	0	0
T3	2057	1657	0	0
T4	24722	20721	0	0
T5	8493	8086	0	0
T6	422	22	0	0
T7	15140	14724	0	0
T13	507	107	0	0
T14	507	107	0	0
T15	501	101	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	8175	0	0
T1	184523	9	0	0
T2	171814	4	0	0
T3	240269	0	0	0
T4	593346	7	0	0
T5	101929	3	0	0
T6	181604	0	0	0
T7	719203	62	0	0
T10	0	18	0	0
T11	0	75	0	0
T12	0	12	0	0
T13	48181	0	0	0
T14	48200	0	0	0
T15	251000	0	0	0
T27	0	51	0	0
T42	0	64	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1298056549	0	0
T1	184523	184231	0	0
T2	171814	171519	0	0
T3	240269	240194	0	0
T4	593346	591477	0	0
T5	101929	101839	0	0
T6	181604	181509	0	0
T7	719203	718436	0	0
T13	48181	48116	0	0
T14	48200	48146	0	0
T15	251000	250927	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T5,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T5,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1299919929	8114679	0	0
DstReqKnown_A	9714182	8851941	0	0
SrcAckBusyChk_A	1299919929	8122	0	0
SrcBusyKnown_A	1299919929	1298056549	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	8114679	0	0
T1	184523	2017	0	0
T2	171814	1659	0	0
T3	240269	0	0	0
T4	593346	6081	0	0
T5	101929	1401	0	0
T6	181604	0	0	0
T7	719203	96845	0	0
T10	0	15618	0	0
T11	0	28271	0	0
T12	0	19464	0	0
T13	48181	0	0	0
T14	48200	0	0	0
T15	251000	0	0	0
T27	0	87711	0	0
T42	0	25989	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9714182	8851941	0	0
T1	26361	25920	0	0
T2	13744	13321	0	0
T3	2057	1657	0	0
T4	24722	20721	0	0
T5	8493	8086	0	0
T6	422	22	0	0
T7	15140	14724	0	0
T13	507	107	0	0
T14	507	107	0	0
T15	501	101	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	8122	0	0
T1	184523	9	0	0
T2	171814	4	0	0
T3	240269	0	0	0
T4	593346	7	0	0
T5	101929	3	0	0
T6	181604	0	0	0
T7	719203	60	0	0
T10	0	18	0	0
T11	0	75	0	0
T12	0	12	0	0
T13	48181	0	0	0
T14	48200	0	0	0
T15	251000	0	0	0
T27	0	51	0	0
T42	0	64	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1298056549	0	0
T1	184523	184231	0	0
T2	171814	171519	0	0
T3	240269	240194	0	0
T4	593346	591477	0	0
T5	101929	101839	0	0
T6	181604	181509	0	0
T7	719203	718436	0	0
T13	48181	48116	0	0
T14	48200	48146	0	0
T15	251000	250927	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T5,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T5,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1299919929	8040496	0	0
DstReqKnown_A	9714182	8851941	0	0
SrcAckBusyChk_A	1299919929	8182	0	0
SrcBusyKnown_A	1299919929	1298056549	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	8040496	0	0
T1	184523	1946	0	0
T2	171814	1631	0	0
T3	240269	0	0	0
T4	593346	6013	0	0
T5	101929	1381	0	0
T6	181604	0	0	0
T7	719203	102725	0	0
T10	0	15582	0	0
T11	0	29935	0	0
T12	0	19382	0	0
T13	48181	0	0	0
T14	48200	0	0	0
T15	251000	0	0	0
T27	0	87501	0	0
T42	0	20598	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9714182	8851941	0	0
T1	26361	25920	0	0
T2	13744	13321	0	0
T3	2057	1657	0	0
T4	24722	20721	0	0
T5	8493	8086	0	0
T6	422	22	0	0
T7	15140	14724	0	0
T13	507	107	0	0
T14	507	107	0	0
T15	501	101	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	8182	0	0
T1	184523	9	0	0
T2	171814	4	0	0
T3	240269	0	0	0
T4	593346	7	0	0
T5	101929	3	0	0
T6	181604	0	0	0
T7	719203	64	0	0
T10	0	18	0	0
T11	0	79	0	0
T12	0	12	0	0
T13	48181	0	0	0
T14	48200	0	0	0
T15	251000	0	0	0
T27	0	51	0	0
T42	0	51	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1298056549	0	0
T1	184523	184231	0	0
T2	171814	171519	0	0
T3	240269	240194	0	0
T4	593346	591477	0	0
T5	101929	101839	0	0
T6	181604	181509	0	0
T7	719203	718436	0	0
T13	48181	48116	0	0
T14	48200	48146	0	0
T15	251000	250927	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T5,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T5,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1299919929	1841220	0	0
DstReqKnown_A	9714182	8851941	0	0
SrcAckBusyChk_A	1299919929	1913	0	0
SrcBusyKnown_A	1299919929	1298056549	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1841220	0	0
T1	184523	1894	0	0
T2	171814	1604	0	0
T3	240269	0	0	0
T4	593346	5961	0	0
T5	101929	1358	0	0
T6	181604	0	0	0
T7	719203	6152	0	0
T10	0	15546	0	0
T11	0	4784	0	0
T12	0	19293	0	0
T13	48181	0	0	0
T14	48200	0	0	0
T15	251000	0	0	0
T27	0	1479	0	0
T42	0	475	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9714182	8851941	0	0
T1	26361	25920	0	0
T2	13744	13321	0	0
T3	2057	1657	0	0
T4	24722	20721	0	0
T5	8493	8086	0	0
T6	422	22	0	0
T7	15140	14724	0	0
T13	507	107	0	0
T14	507	107	0	0
T15	501	101	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1913	0	0
T1	184523	9	0	0
T2	171814	4	0	0
T3	240269	0	0	0
T4	593346	7	0	0
T5	101929	3	0	0
T6	181604	0	0	0
T7	719203	4	0	0
T10	0	18	0	0
T11	0	13	0	0
T12	0	12	0	0
T13	48181	0	0	0
T14	48200	0	0	0
T15	251000	0	0	0
T27	0	1	0	0
T42	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1298056549	0	0
T1	184523	184231	0	0
T2	171814	171519	0	0
T3	240269	240194	0	0
T4	593346	591477	0	0
T5	101929	101839	0	0
T6	181604	181509	0	0
T7	719203	718436	0	0
T13	48181	48116	0	0
T14	48200	48146	0	0
T15	251000	250927	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T5,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T5,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1299919929	1846003	0	0
DstReqKnown_A	9714182	8851941	0	0
SrcAckBusyChk_A	1299919929	1897	0	0
SrcBusyKnown_A	1299919929	1298056549	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1846003	0	0
T1	184523	1827	0	0
T2	171814	1580	0	0
T3	240269	0	0	0
T4	593346	5905	0	0
T5	101929	1334	0	0
T6	181604	0	0	0
T7	719203	6112	0	0
T10	0	15510	0	0
T11	0	4337	0	0
T12	0	19216	0	0
T13	48181	0	0	0
T14	48200	0	0	0
T15	251000	0	0	0
T27	0	1469	0	0
T42	0	465	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9714182	8851941	0	0
T1	26361	25920	0	0
T2	13744	13321	0	0
T3	2057	1657	0	0
T4	24722	20721	0	0
T5	8493	8086	0	0
T6	422	22	0	0
T7	15140	14724	0	0
T13	507	107	0	0
T14	507	107	0	0
T15	501	101	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1897	0	0
T1	184523	9	0	0
T2	171814	4	0	0
T3	240269	0	0	0
T4	593346	7	0	0
T5	101929	3	0	0
T6	181604	0	0	0
T7	719203	4	0	0
T10	0	18	0	0
T11	0	13	0	0
T12	0	12	0	0
T13	48181	0	0	0
T14	48200	0	0	0
T15	251000	0	0	0
T27	0	1	0	0
T42	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1298056549	0	0
T1	184523	184231	0	0
T2	171814	171519	0	0
T3	240269	240194	0	0
T4	593346	591477	0	0
T5	101929	101839	0	0
T6	181604	181509	0	0
T7	719203	718436	0	0
T13	48181	48116	0	0
T14	48200	48146	0	0
T15	251000	250927	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T5,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T5,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1299919929	1798578	0	0
DstReqKnown_A	9714182	8851941	0	0
SrcAckBusyChk_A	1299919929	1865	0	0
SrcBusyKnown_A	1299919929	1298056549	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1798578	0	0
T1	184523	1778	0	0
T2	171814	1551	0	0
T3	240269	0	0	0
T4	593346	5828	0	0
T5	101929	1319	0	0
T6	181604	0	0	0
T7	719203	6072	0	0
T10	0	15474	0	0
T11	0	4129	0	0
T12	0	19147	0	0
T13	48181	0	0	0
T14	48200	0	0	0
T15	251000	0	0	0
T27	0	1459	0	0
T42	0	455	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9714182	8851941	0	0
T1	26361	25920	0	0
T2	13744	13321	0	0
T3	2057	1657	0	0
T4	24722	20721	0	0
T5	8493	8086	0	0
T6	422	22	0	0
T7	15140	14724	0	0
T13	507	107	0	0
T14	507	107	0	0
T15	501	101	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1865	0	0
T1	184523	9	0	0
T2	171814	4	0	0
T3	240269	0	0	0
T4	593346	7	0	0
T5	101929	3	0	0
T6	181604	0	0	0
T7	719203	4	0	0
T10	0	18	0	0
T11	0	13	0	0
T12	0	12	0	0
T13	48181	0	0	0
T14	48200	0	0	0
T15	251000	0	0	0
T27	0	1	0	0
T42	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1298056549	0	0
T1	184523	184231	0	0
T2	171814	171519	0	0
T3	240269	240194	0	0
T4	593346	591477	0	0
T5	101929	101839	0	0
T6	181604	181509	0	0
T7	719203	718436	0	0
T13	48181	48116	0	0
T14	48200	48146	0	0
T15	251000	250927	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T5,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T5,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1299919929	1814847	0	0
DstReqKnown_A	9714182	8851941	0	0
SrcAckBusyChk_A	1299919929	1894	0	0
SrcBusyKnown_A	1299919929	1298056549	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1814847	0	0
T1	184523	1717	0	0
T2	171814	1524	0	0
T3	240269	0	0	0
T4	593346	5770	0	0
T5	101929	1294	0	0
T6	181604	0	0	0
T7	719203	6032	0	0
T10	0	15438	0	0
T11	0	4868	0	0
T12	0	19060	0	0
T13	48181	0	0	0
T14	48200	0	0	0
T15	251000	0	0	0
T27	0	1449	0	0
T42	0	445	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9714182	8851941	0	0
T1	26361	25920	0	0
T2	13744	13321	0	0
T3	2057	1657	0	0
T4	24722	20721	0	0
T5	8493	8086	0	0
T6	422	22	0	0
T7	15140	14724	0	0
T13	507	107	0	0
T14	507	107	0	0
T15	501	101	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1894	0	0
T1	184523	9	0	0
T2	171814	4	0	0
T3	240269	0	0	0
T4	593346	7	0	0
T5	101929	3	0	0
T6	181604	0	0	0
T7	719203	4	0	0
T10	0	18	0	0
T11	0	13	0	0
T12	0	12	0	0
T13	48181	0	0	0
T14	48200	0	0	0
T15	251000	0	0	0
T27	0	1	0	0
T42	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1298056549	0	0
T1	184523	184231	0	0
T2	171814	171519	0	0
T3	240269	240194	0	0
T4	593346	591477	0	0
T5	101929	101839	0	0
T6	181604	181509	0	0
T7	719203	718436	0	0
T13	48181	48116	0	0
T14	48200	48146	0	0
T15	251000	250927	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T5,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T5,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1299919929	1820820	0	0
DstReqKnown_A	9714182	8851941	0	0
SrcAckBusyChk_A	1299919929	1928	0	0
SrcBusyKnown_A	1299919929	1298056549	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1820820	0	0
T1	184523	1661	0	0
T2	171814	1490	0	0
T3	240269	0	0	0
T4	593346	5695	0	0
T5	101929	1271	0	0
T6	181604	0	0	0
T7	719203	6144	0	0
T10	0	15402	0	0
T11	0	4697	0	0
T12	0	18958	0	0
T13	48181	0	0	0
T14	48200	0	0	0
T15	251000	0	0	0
T27	0	1477	0	0
T42	0	473	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9714182	8851941	0	0
T1	26361	25920	0	0
T2	13744	13321	0	0
T3	2057	1657	0	0
T4	24722	20721	0	0
T5	8493	8086	0	0
T6	422	22	0	0
T7	15140	14724	0	0
T13	507	107	0	0
T14	507	107	0	0
T15	501	101	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1928	0	0
T1	184523	9	0	0
T2	171814	4	0	0
T3	240269	0	0	0
T4	593346	7	0	0
T5	101929	3	0	0
T6	181604	0	0	0
T7	719203	4	0	0
T10	0	18	0	0
T11	0	13	0	0
T12	0	12	0	0
T13	48181	0	0	0
T14	48200	0	0	0
T15	251000	0	0	0
T27	0	1	0	0
T42	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1298056549	0	0
T1	184523	184231	0	0
T2	171814	171519	0	0
T3	240269	240194	0	0
T4	593346	591477	0	0
T5	101929	101839	0	0
T6	181604	181509	0	0
T7	719203	718436	0	0
T13	48181	48116	0	0
T14	48200	48146	0	0
T15	251000	250927	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T5,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T5,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1299919929	1807310	0	0
DstReqKnown_A	9714182	8851941	0	0
SrcAckBusyChk_A	1299919929	1881	0	0
SrcBusyKnown_A	1299919929	1298056549	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1807310	0	0
T1	184523	1887	0	0
T2	171814	1463	0	0
T3	240269	0	0	0
T4	593346	5634	0	0
T5	101929	1261	0	0
T6	181604	0	0	0
T7	719203	6104	0	0
T10	0	15366	0	0
T11	0	4262	0	0
T12	0	18861	0	0
T13	48181	0	0	0
T14	48200	0	0	0
T15	251000	0	0	0
T27	0	1467	0	0
T42	0	463	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9714182	8851941	0	0
T1	26361	25920	0	0
T2	13744	13321	0	0
T3	2057	1657	0	0
T4	24722	20721	0	0
T5	8493	8086	0	0
T6	422	22	0	0
T7	15140	14724	0	0
T13	507	107	0	0
T14	507	107	0	0
T15	501	101	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1881	0	0
T1	184523	9	0	0
T2	171814	4	0	0
T3	240269	0	0	0
T4	593346	7	0	0
T5	101929	3	0	0
T6	181604	0	0	0
T7	719203	4	0	0
T10	0	18	0	0
T11	0	13	0	0
T12	0	12	0	0
T13	48181	0	0	0
T14	48200	0	0	0
T15	251000	0	0	0
T27	0	1	0	0
T42	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1298056549	0	0
T1	184523	184231	0	0
T2	171814	171519	0	0
T3	240269	240194	0	0
T4	593346	591477	0	0
T5	101929	101839	0	0
T6	181604	181509	0	0
T7	719203	718436	0	0
T13	48181	48116	0	0
T14	48200	48146	0	0
T15	251000	250927	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T5,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T5,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1299919929	1774728	0	0
DstReqKnown_A	9714182	8851941	0	0
SrcAckBusyChk_A	1299919929	1888	0	0
SrcBusyKnown_A	1299919929	1298056549	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1774728	0	0
T1	184523	1958	0	0
T2	171814	1445	0	0
T3	240269	0	0	0
T4	593346	5580	0	0
T5	101929	1232	0	0
T6	181604	0	0	0
T7	719203	6064	0	0
T10	0	15330	0	0
T11	0	4161	0	0
T12	0	18767	0	0
T13	48181	0	0	0
T14	48200	0	0	0
T15	251000	0	0	0
T27	0	1457	0	0
T42	0	453	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9714182	8851941	0	0
T1	26361	25920	0	0
T2	13744	13321	0	0
T3	2057	1657	0	0
T4	24722	20721	0	0
T5	8493	8086	0	0
T6	422	22	0	0
T7	15140	14724	0	0
T13	507	107	0	0
T14	507	107	0	0
T15	501	101	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1888	0	0
T1	184523	9	0	0
T2	171814	4	0	0
T3	240269	0	0	0
T4	593346	7	0	0
T5	101929	3	0	0
T6	181604	0	0	0
T7	719203	4	0	0
T10	0	18	0	0
T11	0	13	0	0
T12	0	12	0	0
T13	48181	0	0	0
T14	48200	0	0	0
T15	251000	0	0	0
T27	0	1	0	0
T42	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1298056549	0	0
T1	184523	184231	0	0
T2	171814	171519	0	0
T3	240269	240194	0	0
T4	593346	591477	0	0
T5	101929	101839	0	0
T6	181604	181509	0	0
T7	719203	718436	0	0
T13	48181	48116	0	0
T14	48200	48146	0	0
T15	251000	250927	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T5,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T5,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1299919929	1757389	0	0
DstReqKnown_A	9714182	8851941	0	0
SrcAckBusyChk_A	1299919929	1854	0	0
SrcBusyKnown_A	1299919929	1298056549	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1757389	0	0
T1	184523	1947	0	0
T2	171814	1419	0	0
T3	240269	0	0	0
T4	593346	5528	0	0
T5	101929	1224	0	0
T6	181604	0	0	0
T7	719203	6024	0	0
T10	0	15294	0	0
T11	0	4915	0	0
T12	0	18681	0	0
T13	48181	0	0	0
T14	48200	0	0	0
T15	251000	0	0	0
T27	0	1447	0	0
T42	0	443	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9714182	8851941	0	0
T1	26361	25920	0	0
T2	13744	13321	0	0
T3	2057	1657	0	0
T4	24722	20721	0	0
T5	8493	8086	0	0
T6	422	22	0	0
T7	15140	14724	0	0
T13	507	107	0	0
T14	507	107	0	0
T15	501	101	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1854	0	0
T1	184523	9	0	0
T2	171814	4	0	0
T3	240269	0	0	0
T4	593346	7	0	0
T5	101929	3	0	0
T6	181604	0	0	0
T7	719203	4	0	0
T10	0	18	0	0
T11	0	13	0	0
T12	0	12	0	0
T13	48181	0	0	0
T14	48200	0	0	0
T15	251000	0	0	0
T27	0	1	0	0
T42	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1298056549	0	0
T1	184523	184231	0	0
T2	171814	171519	0	0
T3	240269	240194	0	0
T4	593346	591477	0	0
T5	101929	101839	0	0
T6	181604	181509	0	0
T7	719203	718436	0	0
T13	48181	48116	0	0
T14	48200	48146	0	0
T15	251000	250927	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T3,T19,T20

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T3,T19,T20
1	1	Covered	T3,T19,T20

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T3,T19,T20
1	-	Covered	T3,T19,T20

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T3,T19,T20

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T19,T20
1	1	Covered	T3,T19,T20

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T3,T19,T20
0	0	1	Covered	T3,T19,T20
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T3,T19,T20
0	0	1	Covered	T3,T19,T20
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1299919929	981422	0	0
DstReqKnown_A	9714182	8851941	0	0
SrcAckBusyChk_A	1299919929	1006	0	0
SrcBusyKnown_A	1299919929	1298056549	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	981422	0	0
T3	240269	6718	0	0
T4	593346	0	0	0
T7	719203	0	0	0
T14	48200	0	0	0
T15	251000	0	0	0
T19	0	3574	0	0
T20	0	1716	0	0
T25	85827	0	0	0
T26	74233	0	0	0
T27	273041	0	0	0
T47	122818	0	0	0
T48	190233	0	0	0
T76	0	1103	0	0
T77	0	2807	0	0
T78	0	2406	0	0
T79	0	3877	0	0
T80	0	1890	0	0
T81	0	843	0	0
T82	0	743	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9714182	8851941	0	0
T1	26361	25920	0	0
T2	13744	13321	0	0
T3	2057	1657	0	0
T4	24722	20721	0	0
T5	8493	8086	0	0
T6	422	22	0	0
T7	15140	14724	0	0
T13	507	107	0	0
T14	507	107	0	0
T15	501	101	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1006	0	0
T3	240269	4	0	0
T4	593346	0	0	0
T7	719203	0	0	0
T14	48200	0	0	0
T15	251000	0	0	0
T19	0	4	0	0
T20	0	2	0	0
T25	85827	0	0	0
T26	74233	0	0	0
T27	273041	0	0	0
T47	122818	0	0	0
T48	190233	0	0	0
T76	0	2	0	0
T77	0	2	0	0
T78	0	2	0	0
T79	0	2	0	0
T80	0	2	0	0
T81	0	2	0	0
T82	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1299919929	1298056549	0	0
T1	184523	184231	0	0
T2	171814	171519	0	0
T3	240269	240194	0	0
T4	593346	591477	0	0
T5	101929	101839	0	0
T6	181604	181509	0	0
T7	719203	718436	0	0
T13	48181	48116	0	0
T14	48200	48146	0	0
T15	251000	250927	0	0