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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.10 99.44 96.81 100.00 98.08 98.93 99.71 93.70


Total test records in report: 915
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html

T437 /workspace/coverage/default/17.sysrst_ctrl_alert_test.1983923842 Mar 26 02:41:56 PM PDT 24 Mar 26 02:41:59 PM PDT 24 2024940484 ps
T438 /workspace/coverage/default/20.sysrst_ctrl_smoke.3029900380 Mar 26 02:42:00 PM PDT 24 Mar 26 02:42:02 PM PDT 24 2136241325 ps
T439 /workspace/coverage/default/29.sysrst_ctrl_pin_access_test.3771032916 Mar 26 02:42:27 PM PDT 24 Mar 26 02:42:30 PM PDT 24 2247417704 ps
T363 /workspace/coverage/default/2.sysrst_ctrl_combo_detect_with_pre_cond.1693586469 Mar 26 02:41:17 PM PDT 24 Mar 26 02:43:03 PM PDT 24 83391315010 ps
T440 /workspace/coverage/default/6.sysrst_ctrl_pin_access_test.3852883299 Mar 26 02:41:33 PM PDT 24 Mar 26 02:41:39 PM PDT 24 2050311999 ps
T269 /workspace/coverage/default/34.sysrst_ctrl_combo_detect.590009697 Mar 26 02:42:46 PM PDT 24 Mar 26 02:43:59 PM PDT 24 108571425207 ps
T441 /workspace/coverage/default/43.sysrst_ctrl_smoke.923526124 Mar 26 02:43:11 PM PDT 24 Mar 26 02:43:15 PM PDT 24 2119299253 ps
T442 /workspace/coverage/default/13.sysrst_ctrl_pin_access_test.3813870756 Mar 26 02:41:45 PM PDT 24 Mar 26 02:41:50 PM PDT 24 2202449894 ps
T443 /workspace/coverage/default/8.sysrst_ctrl_smoke.3485341550 Mar 26 02:41:44 PM PDT 24 Mar 26 02:41:47 PM PDT 24 2130292261 ps
T154 /workspace/coverage/default/26.sysrst_ctrl_stress_all_with_rand_reset.460409416 Mar 26 02:42:28 PM PDT 24 Mar 26 02:43:15 PM PDT 24 69276566185 ps
T182 /workspace/coverage/default/11.sysrst_ctrl_pin_override_test.2129345764 Mar 26 02:41:44 PM PDT 24 Mar 26 02:41:49 PM PDT 24 2516179195 ps
T183 /workspace/coverage/default/1.sysrst_ctrl_in_out_inverted.1214062153 Mar 26 02:41:16 PM PDT 24 Mar 26 02:41:24 PM PDT 24 2459642602 ps
T184 /workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.3247732995 Mar 26 02:43:07 PM PDT 24 Mar 26 02:43:15 PM PDT 24 2466140430 ps
T185 /workspace/coverage/default/17.sysrst_ctrl_smoke.796935747 Mar 26 02:42:03 PM PDT 24 Mar 26 02:42:05 PM PDT 24 2126353628 ps
T186 /workspace/coverage/default/13.sysrst_ctrl_alert_test.3528766495 Mar 26 02:41:49 PM PDT 24 Mar 26 02:41:51 PM PDT 24 2038554968 ps
T187 /workspace/coverage/default/35.sysrst_ctrl_pin_override_test.570280622 Mar 26 02:42:48 PM PDT 24 Mar 26 02:42:55 PM PDT 24 2515715820 ps
T188 /workspace/coverage/default/14.sysrst_ctrl_ec_pwr_on_rst.2893243245 Mar 26 02:41:51 PM PDT 24 Mar 26 02:41:56 PM PDT 24 2642268884 ps
T189 /workspace/coverage/default/9.sysrst_ctrl_pin_access_test.2875401755 Mar 26 02:41:43 PM PDT 24 Mar 26 02:41:49 PM PDT 24 2024432134 ps
T190 /workspace/coverage/default/14.sysrst_ctrl_combo_detect.3028075881 Mar 26 02:41:41 PM PDT 24 Mar 26 02:42:34 PM PDT 24 62723448547 ps
T444 /workspace/coverage/default/18.sysrst_ctrl_alert_test.3781644663 Mar 26 02:42:01 PM PDT 24 Mar 26 02:42:04 PM PDT 24 2018607727 ps
T445 /workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.1467340101 Mar 26 02:43:39 PM PDT 24 Mar 26 02:43:42 PM PDT 24 2631881615 ps
T318 /workspace/coverage/default/25.sysrst_ctrl_ultra_low_pwr.1263334786 Mar 26 02:42:21 PM PDT 24 Mar 26 02:43:21 PM PDT 24 2815768647359 ps
T446 /workspace/coverage/default/28.sysrst_ctrl_pin_access_test.2094441648 Mar 26 02:42:28 PM PDT 24 Mar 26 02:42:29 PM PDT 24 2088312252 ps
T447 /workspace/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.465211422 Mar 26 02:43:58 PM PDT 24 Mar 26 02:44:56 PM PDT 24 54993921441 ps
T448 /workspace/coverage/default/10.sysrst_ctrl_in_out_inverted.1495673242 Mar 26 02:41:43 PM PDT 24 Mar 26 02:41:45 PM PDT 24 2475930388 ps
T449 /workspace/coverage/default/39.sysrst_ctrl_ec_pwr_on_rst.1255606380 Mar 26 02:42:57 PM PDT 24 Mar 26 02:43:03 PM PDT 24 4059889260 ps
T90 /workspace/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.4214110890 Mar 26 02:42:36 PM PDT 24 Mar 26 02:46:45 PM PDT 24 1469154782774 ps
T145 /workspace/coverage/default/46.sysrst_ctrl_combo_detect.3961324549 Mar 26 02:43:37 PM PDT 24 Mar 26 02:46:54 PM PDT 24 134460039918 ps
T146 /workspace/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.1459469609 Mar 26 02:41:21 PM PDT 24 Mar 26 02:41:45 PM PDT 24 33645491408 ps
T91 /workspace/coverage/default/28.sysrst_ctrl_stress_all_with_rand_reset.1583566116 Mar 26 02:42:28 PM PDT 24 Mar 26 02:44:00 PM PDT 24 41191714953 ps
T147 /workspace/coverage/default/19.sysrst_ctrl_smoke.3237230613 Mar 26 02:42:00 PM PDT 24 Mar 26 02:42:01 PM PDT 24 2217745614 ps
T148 /workspace/coverage/default/31.sysrst_ctrl_edge_detect.514846837 Mar 26 02:42:38 PM PDT 24 Mar 26 02:42:40 PM PDT 24 3089541993 ps
T149 /workspace/coverage/default/19.sysrst_ctrl_pin_access_test.2348285297 Mar 26 02:42:03 PM PDT 24 Mar 26 02:42:06 PM PDT 24 2228316366 ps
T150 /workspace/coverage/default/35.sysrst_ctrl_alert_test.3886268403 Mar 26 02:42:47 PM PDT 24 Mar 26 02:42:53 PM PDT 24 2010963173 ps
T151 /workspace/coverage/default/36.sysrst_ctrl_combo_detect.1572896041 Mar 26 02:42:44 PM PDT 24 Mar 26 02:48:20 PM PDT 24 129966473123 ps
T152 /workspace/coverage/default/35.sysrst_ctrl_in_out_inverted.882104645 Mar 26 02:42:45 PM PDT 24 Mar 26 02:42:53 PM PDT 24 2473017042 ps
T270 /workspace/coverage/default/7.sysrst_ctrl_stress_all.3097857925 Mar 26 02:41:43 PM PDT 24 Mar 26 02:42:29 PM PDT 24 34547993188 ps
T450 /workspace/coverage/default/33.sysrst_ctrl_ec_pwr_on_rst.1805343034 Mar 26 02:42:34 PM PDT 24 Mar 26 02:42:49 PM PDT 24 5462153379 ps
T343 /workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.2168474973 Mar 26 02:43:54 PM PDT 24 Mar 26 02:44:47 PM PDT 24 92589032969 ps
T451 /workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.157502941 Mar 26 02:41:12 PM PDT 24 Mar 26 02:41:15 PM PDT 24 2380325856 ps
T271 /workspace/coverage/default/44.sysrst_ctrl_combo_detect.1188263243 Mar 26 02:43:22 PM PDT 24 Mar 26 02:49:48 PM PDT 24 149469346485 ps
T452 /workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.2248255937 Mar 26 02:43:35 PM PDT 24 Mar 26 02:43:39 PM PDT 24 3155597841 ps
T453 /workspace/coverage/default/32.sysrst_ctrl_ec_pwr_on_rst.1692797541 Mar 26 02:42:34 PM PDT 24 Mar 26 02:42:45 PM PDT 24 3716586624 ps
T365 /workspace/coverage/default/47.sysrst_ctrl_combo_detect.451715115 Mar 26 02:43:36 PM PDT 24 Mar 26 02:44:10 PM PDT 24 123082551687 ps
T179 /workspace/coverage/default/38.sysrst_ctrl_stress_all_with_rand_reset.1056532844 Mar 26 02:42:57 PM PDT 24 Mar 26 02:43:03 PM PDT 24 36367068956 ps
T454 /workspace/coverage/default/25.sysrst_ctrl_in_out_inverted.256685244 Mar 26 02:42:18 PM PDT 24 Mar 26 02:42:21 PM PDT 24 2474547457 ps
T455 /workspace/coverage/default/27.sysrst_ctrl_ec_pwr_on_rst.3020527272 Mar 26 02:42:27 PM PDT 24 Mar 26 02:44:46 PM PDT 24 872388636065 ps
T456 /workspace/coverage/default/20.sysrst_ctrl_pin_override_test.2067630108 Mar 26 02:42:02 PM PDT 24 Mar 26 02:42:09 PM PDT 24 2509659364 ps
T457 /workspace/coverage/default/7.sysrst_ctrl_pin_access_test.1363748457 Mar 26 02:41:33 PM PDT 24 Mar 26 02:41:35 PM PDT 24 2054391046 ps
T458 /workspace/coverage/default/30.sysrst_ctrl_flash_wr_prot_out.3342501282 Mar 26 02:42:35 PM PDT 24 Mar 26 02:42:43 PM PDT 24 2610817497 ps
T121 /workspace/coverage/default/31.sysrst_ctrl_ultra_low_pwr.2599416406 Mar 26 02:42:36 PM PDT 24 Mar 26 02:42:43 PM PDT 24 5660555862 ps
T459 /workspace/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.16289339 Mar 26 02:42:46 PM PDT 24 Mar 26 02:42:55 PM PDT 24 26133130002 ps
T460 /workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1615358309 Mar 26 02:41:23 PM PDT 24 Mar 26 02:41:26 PM PDT 24 2348547827 ps
T383 /workspace/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.929717651 Mar 26 02:41:22 PM PDT 24 Mar 26 02:43:07 PM PDT 24 79064888701 ps
T461 /workspace/coverage/default/22.sysrst_ctrl_flash_wr_prot_out.3322365020 Mar 26 02:42:12 PM PDT 24 Mar 26 02:42:17 PM PDT 24 2611030419 ps
T462 /workspace/coverage/default/18.sysrst_ctrl_ec_pwr_on_rst.714656805 Mar 26 02:42:00 PM PDT 24 Mar 26 02:42:10 PM PDT 24 3449145340 ps
T463 /workspace/coverage/default/34.sysrst_ctrl_smoke.3749733253 Mar 26 02:42:38 PM PDT 24 Mar 26 02:42:40 PM PDT 24 2127438364 ps
T464 /workspace/coverage/default/30.sysrst_ctrl_smoke.3638385326 Mar 26 02:42:37 PM PDT 24 Mar 26 02:42:39 PM PDT 24 2121430196 ps
T94 /workspace/coverage/default/36.sysrst_ctrl_stress_all_with_rand_reset.1445454542 Mar 26 02:42:47 PM PDT 24 Mar 26 02:43:50 PM PDT 24 191026912019 ps
T348 /workspace/coverage/default/18.sysrst_ctrl_stress_all.352035189 Mar 26 02:42:05 PM PDT 24 Mar 26 02:43:10 PM PDT 24 49859766338 ps
T93 /workspace/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.1463820940 Mar 26 02:43:11 PM PDT 24 Mar 26 02:43:41 PM PDT 24 51888013701 ps
T465 /workspace/coverage/default/30.sysrst_ctrl_combo_detect_with_pre_cond.3014425015 Mar 26 02:42:34 PM PDT 24 Mar 26 02:43:00 PM PDT 24 58657524484 ps
T134 /workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.838556526 Mar 26 02:43:35 PM PDT 24 Mar 26 02:43:40 PM PDT 24 4206354451 ps
T466 /workspace/coverage/default/36.sysrst_ctrl_pin_access_test.4159030705 Mar 26 02:42:45 PM PDT 24 Mar 26 02:42:46 PM PDT 24 2071549343 ps
T467 /workspace/coverage/default/10.sysrst_ctrl_stress_all_with_rand_reset.1001700638 Mar 26 02:41:44 PM PDT 24 Mar 26 02:42:37 PM PDT 24 30732671093 ps
T122 /workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.2763796448 Mar 26 02:43:20 PM PDT 24 Mar 26 02:43:28 PM PDT 24 11594697322 ps
T468 /workspace/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.3845483769 Mar 26 02:43:51 PM PDT 24 Mar 26 02:44:55 PM PDT 24 48144123228 ps
T469 /workspace/coverage/default/49.sysrst_ctrl_pin_override_test.3349964038 Mar 26 02:43:46 PM PDT 24 Mar 26 02:43:51 PM PDT 24 2516495370 ps
T470 /workspace/coverage/default/39.sysrst_ctrl_pin_access_test.2293541178 Mar 26 02:43:07 PM PDT 24 Mar 26 02:43:08 PM PDT 24 2180376731 ps
T471 /workspace/coverage/default/22.sysrst_ctrl_ec_pwr_on_rst.1047096425 Mar 26 02:42:15 PM PDT 24 Mar 26 02:42:22 PM PDT 24 3157609099 ps
T472 /workspace/coverage/default/18.sysrst_ctrl_combo_detect.2221435127 Mar 26 02:42:01 PM PDT 24 Mar 26 02:43:15 PM PDT 24 120606720786 ps
T473 /workspace/coverage/default/16.sysrst_ctrl_flash_wr_prot_out.2018512106 Mar 26 02:41:56 PM PDT 24 Mar 26 02:41:59 PM PDT 24 2639052332 ps
T474 /workspace/coverage/default/12.sysrst_ctrl_flash_wr_prot_out.585240653 Mar 26 02:41:44 PM PDT 24 Mar 26 02:41:46 PM PDT 24 2704120618 ps
T475 /workspace/coverage/default/9.sysrst_ctrl_alert_test.222071523 Mar 26 02:41:43 PM PDT 24 Mar 26 02:41:50 PM PDT 24 2008759976 ps
T158 /workspace/coverage/default/4.sysrst_ctrl_edge_detect.469703133 Mar 26 02:41:25 PM PDT 24 Mar 26 02:41:33 PM PDT 24 2957817212 ps
T476 /workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.2829268361 Mar 26 02:43:49 PM PDT 24 Mar 26 02:43:56 PM PDT 24 2457477252 ps
T192 /workspace/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.2170519506 Mar 26 02:42:33 PM PDT 24 Mar 26 02:43:46 PM PDT 24 116880226188 ps
T477 /workspace/coverage/default/29.sysrst_ctrl_smoke.2808225827 Mar 26 02:42:24 PM PDT 24 Mar 26 02:42:29 PM PDT 24 2121932745 ps
T478 /workspace/coverage/default/21.sysrst_ctrl_pin_override_test.965953069 Mar 26 02:42:15 PM PDT 24 Mar 26 02:42:23 PM PDT 24 2511159170 ps
T159 /workspace/coverage/default/46.sysrst_ctrl_edge_detect.909752369 Mar 26 02:43:34 PM PDT 24 Mar 26 02:43:42 PM PDT 24 4089502354 ps
T375 /workspace/coverage/default/35.sysrst_ctrl_combo_detect.2461066405 Mar 26 02:42:45 PM PDT 24 Mar 26 02:44:26 PM PDT 24 38451279814 ps
T211 /workspace/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.3547143233 Mar 26 02:43:22 PM PDT 24 Mar 26 02:43:56 PM PDT 24 59392071121 ps
T479 /workspace/coverage/default/32.sysrst_ctrl_auto_blk_key_output.3576896027 Mar 26 02:42:40 PM PDT 24 Mar 26 02:42:43 PM PDT 24 3559056263 ps
T480 /workspace/coverage/default/36.sysrst_ctrl_in_out_inverted.1162360490 Mar 26 02:42:44 PM PDT 24 Mar 26 02:42:48 PM PDT 24 2479860184 ps
T367 /workspace/coverage/default/8.sysrst_ctrl_stress_all.779890617 Mar 26 02:41:43 PM PDT 24 Mar 26 02:46:47 PM PDT 24 156702286487 ps
T481 /workspace/coverage/default/16.sysrst_ctrl_in_out_inverted.1894052737 Mar 26 02:41:55 PM PDT 24 Mar 26 02:41:59 PM PDT 24 2471433399 ps
T482 /workspace/coverage/default/22.sysrst_ctrl_smoke.3033070815 Mar 26 02:42:08 PM PDT 24 Mar 26 02:42:14 PM PDT 24 2111379119 ps
T483 /workspace/coverage/default/9.sysrst_ctrl_pin_override_test.2257633974 Mar 26 02:41:43 PM PDT 24 Mar 26 02:41:51 PM PDT 24 2512360370 ps
T484 /workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.3693480475 Mar 26 02:43:21 PM PDT 24 Mar 26 02:43:29 PM PDT 24 2622163823 ps
T485 /workspace/coverage/default/27.sysrst_ctrl_auto_blk_key_output.2666005030 Mar 26 02:42:28 PM PDT 24 Mar 26 02:42:30 PM PDT 24 3904521034 ps
T486 /workspace/coverage/default/28.sysrst_ctrl_ultra_low_pwr.1970198579 Mar 26 02:42:30 PM PDT 24 Mar 26 02:42:37 PM PDT 24 7125177933 ps
T487 /workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.114911853 Mar 26 02:43:21 PM PDT 24 Mar 26 02:43:24 PM PDT 24 2718049046 ps
T488 /workspace/coverage/default/11.sysrst_ctrl_smoke.1233368819 Mar 26 02:41:52 PM PDT 24 Mar 26 02:41:59 PM PDT 24 2109468375 ps
T489 /workspace/coverage/default/33.sysrst_ctrl_pin_override_test.581608368 Mar 26 02:42:34 PM PDT 24 Mar 26 02:42:41 PM PDT 24 2511365389 ps
T490 /workspace/coverage/default/24.sysrst_ctrl_flash_wr_prot_out.3246636529 Mar 26 02:42:19 PM PDT 24 Mar 26 02:42:21 PM PDT 24 2632657157 ps
T491 /workspace/coverage/default/10.sysrst_ctrl_smoke.3234103949 Mar 26 02:41:43 PM PDT 24 Mar 26 02:41:48 PM PDT 24 2114427378 ps
T247 /workspace/coverage/default/24.sysrst_ctrl_edge_detect.1738993625 Mar 26 02:42:18 PM PDT 24 Mar 26 02:42:22 PM PDT 24 2940521931 ps
T101 /workspace/coverage/default/20.sysrst_ctrl_stress_all.1774220286 Mar 26 02:42:08 PM PDT 24 Mar 26 02:48:45 PM PDT 24 149350055986 ps
T347 /workspace/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.1620190037 Mar 26 02:43:59 PM PDT 24 Mar 26 02:45:03 PM PDT 24 49894085906 ps
T492 /workspace/coverage/default/18.sysrst_ctrl_auto_blk_key_output.3921891221 Mar 26 02:42:02 PM PDT 24 Mar 26 02:42:05 PM PDT 24 3372384930 ps
T493 /workspace/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.3655636664 Mar 26 02:43:08 PM PDT 24 Mar 26 02:43:10 PM PDT 24 2624511572 ps
T494 /workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.3094118651 Mar 26 02:43:40 PM PDT 24 Mar 26 02:43:45 PM PDT 24 2457347388 ps
T495 /workspace/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.488493568 Mar 26 02:44:11 PM PDT 24 Mar 26 02:46:24 PM PDT 24 53018018196 ps
T496 /workspace/coverage/default/6.sysrst_ctrl_alert_test.823677400 Mar 26 02:41:32 PM PDT 24 Mar 26 02:41:35 PM PDT 24 2016812498 ps
T360 /workspace/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.715120229 Mar 26 02:41:34 PM PDT 24 Mar 26 02:46:40 PM PDT 24 110700073082 ps
T497 /workspace/coverage/default/37.sysrst_ctrl_ec_pwr_on_rst.3091469165 Mar 26 02:42:54 PM PDT 24 Mar 26 02:42:59 PM PDT 24 2900629210 ps
T498 /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1761704858 Mar 26 02:41:18 PM PDT 24 Mar 26 02:41:20 PM PDT 24 2361628549 ps
T92 /workspace/coverage/default/29.sysrst_ctrl_ultra_low_pwr.2633775262 Mar 26 02:42:30 PM PDT 24 Mar 26 02:54:13 PM PDT 24 3135292635500 ps
T499 /workspace/coverage/default/44.sysrst_ctrl_pin_access_test.2055538757 Mar 26 02:43:08 PM PDT 24 Mar 26 02:43:15 PM PDT 24 2063966238 ps
T500 /workspace/coverage/default/25.sysrst_ctrl_smoke.158405246 Mar 26 02:42:17 PM PDT 24 Mar 26 02:42:22 PM PDT 24 2112371266 ps
T501 /workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.2669504051 Mar 26 02:43:40 PM PDT 24 Mar 26 02:43:50 PM PDT 24 3738971989 ps
T502 /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2023536672 Mar 26 02:41:19 PM PDT 24 Mar 26 02:41:21 PM PDT 24 2596300880 ps
T503 /workspace/coverage/default/1.sysrst_ctrl_auto_blk_key_output.2568301868 Mar 26 02:41:18 PM PDT 24 Mar 26 02:41:20 PM PDT 24 3687006325 ps
T133 /workspace/coverage/default/37.sysrst_ctrl_stress_all_with_rand_reset.3716925203 Mar 26 02:42:46 PM PDT 24 Mar 26 02:43:34 PM PDT 24 1737805208902 ps
T504 /workspace/coverage/default/40.sysrst_ctrl_in_out_inverted.2202559258 Mar 26 02:43:07 PM PDT 24 Mar 26 02:43:15 PM PDT 24 2468900911 ps
T123 /workspace/coverage/default/36.sysrst_ctrl_ultra_low_pwr.3868709286 Mar 26 02:42:47 PM PDT 24 Mar 26 02:42:55 PM PDT 24 5967854271 ps
T505 /workspace/coverage/default/33.sysrst_ctrl_pin_access_test.2717376816 Mar 26 02:42:37 PM PDT 24 Mar 26 02:42:38 PM PDT 24 2279513125 ps
T506 /workspace/coverage/default/28.sysrst_ctrl_smoke.233698200 Mar 26 02:42:30 PM PDT 24 Mar 26 02:42:31 PM PDT 24 2180355979 ps
T507 /workspace/coverage/default/45.sysrst_ctrl_pin_override_test.2123453775 Mar 26 02:43:25 PM PDT 24 Mar 26 02:43:31 PM PDT 24 2513588418 ps
T508 /workspace/coverage/default/24.sysrst_ctrl_alert_test.1085756871 Mar 26 02:42:24 PM PDT 24 Mar 26 02:42:31 PM PDT 24 2013026149 ps
T509 /workspace/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.534664362 Mar 26 02:42:59 PM PDT 24 Mar 26 02:43:02 PM PDT 24 2625815877 ps
T180 /workspace/coverage/default/12.sysrst_ctrl_edge_detect.413268570 Mar 26 02:41:52 PM PDT 24 Mar 26 02:41:57 PM PDT 24 5025423683 ps
T510 /workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.1483107974 Mar 26 02:41:47 PM PDT 24 Mar 26 02:41:49 PM PDT 24 3792280056 ps
T511 /workspace/coverage/default/37.sysrst_ctrl_edge_detect.3665463004 Mar 26 02:42:47 PM PDT 24 Mar 26 02:42:50 PM PDT 24 4786877428 ps
T512 /workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.4118810616 Mar 26 02:41:33 PM PDT 24 Mar 26 02:41:37 PM PDT 24 2612785951 ps
T160 /workspace/coverage/default/2.sysrst_ctrl_edge_detect.2896291179 Mar 26 02:41:17 PM PDT 24 Mar 26 02:41:26 PM PDT 24 3117458283 ps
T170 /workspace/coverage/default/11.sysrst_ctrl_in_out_inverted.2601512517 Mar 26 02:41:48 PM PDT 24 Mar 26 02:41:50 PM PDT 24 2491546920 ps
T171 /workspace/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.2427965156 Mar 26 02:43:06 PM PDT 24 Mar 26 02:44:22 PM PDT 24 64234629004 ps
T172 /workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.2013872968 Mar 26 02:43:20 PM PDT 24 Mar 26 02:43:25 PM PDT 24 2612992567 ps
T173 /workspace/coverage/default/34.sysrst_ctrl_auto_blk_key_output.464370269 Mar 26 02:42:46 PM PDT 24 Mar 26 02:42:57 PM PDT 24 3886635629 ps
T174 /workspace/coverage/default/36.sysrst_ctrl_auto_blk_key_output.305835025 Mar 26 02:42:44 PM PDT 24 Mar 26 02:42:49 PM PDT 24 3233268171 ps
T175 /workspace/coverage/default/17.sysrst_ctrl_combo_detect_with_pre_cond.3661639872 Mar 26 02:42:03 PM PDT 24 Mar 26 02:42:35 PM PDT 24 24587614824 ps
T88 /workspace/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.3507602829 Mar 26 02:43:08 PM PDT 24 Mar 26 02:47:00 PM PDT 24 93689734802 ps
T176 /workspace/coverage/default/32.sysrst_ctrl_alert_test.2834940901 Mar 26 02:42:39 PM PDT 24 Mar 26 02:42:41 PM PDT 24 2021313961 ps
T177 /workspace/coverage/default/13.sysrst_ctrl_flash_wr_prot_out.3196545435 Mar 26 02:41:50 PM PDT 24 Mar 26 02:41:58 PM PDT 24 2613563337 ps
T178 /workspace/coverage/default/40.sysrst_ctrl_edge_detect.3770944018 Mar 26 02:42:58 PM PDT 24 Mar 26 02:42:59 PM PDT 24 5148361114 ps
T513 /workspace/coverage/default/41.sysrst_ctrl_stress_all.2008391498 Mar 26 02:43:07 PM PDT 24 Mar 26 02:43:13 PM PDT 24 7386110321 ps
T277 /workspace/coverage/default/12.sysrst_ctrl_stress_all.897039964 Mar 26 02:41:46 PM PDT 24 Mar 26 02:43:12 PM PDT 24 63960595105 ps
T514 /workspace/coverage/default/24.sysrst_ctrl_auto_blk_key_output.3257484990 Mar 26 02:42:23 PM PDT 24 Mar 26 02:42:27 PM PDT 24 3384828413 ps
T515 /workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.1226929543 Mar 26 02:43:46 PM PDT 24 Mar 26 02:43:50 PM PDT 24 2617901533 ps
T161 /workspace/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.2610559007 Mar 26 02:41:52 PM PDT 24 Mar 26 02:43:46 PM PDT 24 1596143248498 ps
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T384 /workspace/coverage/default/19.sysrst_ctrl_ultra_low_pwr.1101802050 Mar 26 02:42:06 PM PDT 24 Mar 26 02:42:54 PM PDT 24 1077355353713 ps
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T574 /workspace/coverage/default/39.sysrst_ctrl_flash_wr_prot_out.4060534333 Mar 26 02:42:57 PM PDT 24 Mar 26 02:43:05 PM PDT 24 2608471899 ps
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T581 /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.3144661045 Mar 26 02:41:08 PM PDT 24 Mar 26 02:41:15 PM PDT 24 2254525120 ps
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T585 /workspace/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.479792123 Mar 26 02:43:59 PM PDT 24 Mar 26 02:44:38 PM PDT 24 53488127294 ps
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T587 /workspace/coverage/default/38.sysrst_ctrl_auto_blk_key_output.3659890194 Mar 26 02:42:57 PM PDT 24 Mar 26 02:43:09 PM PDT 24 3860117926 ps
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T595 /workspace/coverage/default/34.sysrst_ctrl_stress_all_with_rand_reset.1074534559 Mar 26 02:42:46 PM PDT 24 Mar 26 02:43:05 PM PDT 24 34409265467 ps
T596 /workspace/coverage/default/18.sysrst_ctrl_pin_override_test.3295504342 Mar 26 02:42:03 PM PDT 24 Mar 26 02:42:11 PM PDT 24 2512567760 ps
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T598 /workspace/coverage/default/23.sysrst_ctrl_in_out_inverted.3880734739 Mar 26 02:42:15 PM PDT 24 Mar 26 02:42:22 PM PDT 24 2455333347 ps
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T600 /workspace/coverage/default/21.sysrst_ctrl_flash_wr_prot_out.3494397751 Mar 26 02:42:08 PM PDT 24 Mar 26 02:42:16 PM PDT 24 2608044382 ps
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T378 /workspace/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.2082513337 Mar 26 02:43:11 PM PDT 24 Mar 26 02:45:34 PM PDT 24 51120704101 ps
T602 /workspace/coverage/default/7.sysrst_ctrl_alert_test.1865979904 Mar 26 02:41:41 PM PDT 24 Mar 26 02:41:43 PM PDT 24 2076938139 ps
T603 /workspace/coverage/default/27.sysrst_ctrl_ultra_low_pwr.1635431029 Mar 26 02:42:28 PM PDT 24 Mar 26 02:42:31 PM PDT 24 6953074784 ps
T604 /workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.3705020872 Mar 26 02:43:22 PM PDT 24 Mar 26 02:43:24 PM PDT 24 2467375047 ps
T605 /workspace/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.786332340 Mar 26 02:42:57 PM PDT 24 Mar 26 02:42:59 PM PDT 24 3837857604 ps
T606 /workspace/coverage/default/36.sysrst_ctrl_combo_detect_with_pre_cond.4262748607 Mar 26 02:42:48 PM PDT 24 Mar 26 02:43:22 PM PDT 24 64024787471 ps
T607 /workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.370397271 Mar 26 02:43:10 PM PDT 24 Mar 26 02:43:21 PM PDT 24 3694602454 ps
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T609 /workspace/coverage/default/48.sysrst_ctrl_stress_all.3966310509 Mar 26 02:43:40 PM PDT 24 Mar 26 02:43:47 PM PDT 24 8859803784 ps
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