SYSRST_CTRL Simulation Results

Tuesday March 26 2024 19:03:00 UTC

GitHub Revision: `b111fbcef3`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 29002153775573720681496722306495080473944791482258036550176866636887326742880

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sysrst_ctrl_smoke	6.550s	2.112ms	50	50	100.00
V1	input_output_inverted	sysrst_ctrl_in_out_inverted	8.150s	2.475ms	50	50	100.00
V1	combo_detect_ec_rst	sysrst_ctrl_combo_detect_ec_rst	6.840s	2.415ms	4	5	80.00
V1	combo_detect_ec_rst_with_pre_cond	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	2.110s	2.349ms	5	5	100.00
V1	csr_hw_reset	sysrst_ctrl_csr_hw_reset	16.930s	6.039ms	5	5	100.00
V1	csr_rw	sysrst_ctrl_csr_rw	6.740s	2.041ms	20	20	100.00
V1	csr_bit_bash	sysrst_ctrl_csr_bit_bash	3.457m	38.975ms	5	5	100.00
V1	csr_aliasing	sysrst_ctrl_csr_aliasing	12.100s	3.337ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sysrst_ctrl_csr_mem_rw_with_rand_reset	6.950s	2.136ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sysrst_ctrl_csr_rw	6.740s	2.041ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	12.100s	3.337ms	5	5	100.00
V1		TOTAL			164	165	99.39
V2	combo_detect	sysrst_ctrl_combo_detect	8.725m	194.154ms	50	50	100.00
V2	combo_detect_with_pre_cond	sysrst_ctrl_combo_detect_with_pre_cond	7.889m	170.015ms	98	100	98.00
V2	auto_block_key_outputs	sysrst_ctrl_auto_blk_key_output	8.365m	188.633ms	50	50	100.00
V2	keyboard_input_triggered_interrupt	sysrst_ctrl_edge_detect	8.746m	1.181s	50	50	100.00
V2	pin_output_keyboard_inversion_control	sysrst_ctrl_pin_override_test	7.970s	2.512ms	50	50	100.00
V2	pin_input_value_accessibility	sysrst_ctrl_pin_access_test	6.780s	2.237ms	50	50	100.00
V2	ec_power_on_reset	sysrst_ctrl_ec_pwr_on_rst	50.706m	1.123s	49	50	98.00
V2	flash_write_protect_output	sysrst_ctrl_flash_wr_prot_out	8.200s	2.611ms	50	50	100.00
V2	ultra_low_power_test	sysrst_ctrl_ultra_low_pwr	11.716m	3.135s	45	50	90.00
V2	sysrst_ctrl_feature_disable	sysrst_ctrl_feature_disable	26.280s	39.716ms	2	2	100.00
V2	stress_all	sysrst_ctrl_stress_all	9.521m	226.150ms	50	50	100.00
V2	alert_test	sysrst_ctrl_alert_test	6.110s	2.011ms	50	50	100.00
V2	intr_test	sysrst_ctrl_intr_test	6.270s	2.013ms	50	50	100.00
V2	tl_d_oob_addr_access	sysrst_ctrl_tl_errors	8.240s	2.146ms	20	20	100.00
V2	tl_d_illegal_access	sysrst_ctrl_tl_errors	8.240s	2.146ms	20	20	100.00
V2	tl_d_outstanding_access	sysrst_ctrl_csr_hw_reset	16.930s	6.039ms	5	5	100.00
		sysrst_ctrl_csr_rw	6.740s	2.041ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	12.100s	3.337ms	5	5	100.00
		sysrst_ctrl_same_csr_outstanding	47.630s	10.984ms	20	20	100.00
V2	tl_d_partial_access	sysrst_ctrl_csr_hw_reset	16.930s	6.039ms	5	5	100.00
		sysrst_ctrl_csr_rw	6.740s	2.041ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	12.100s	3.337ms	5	5	100.00
		sysrst_ctrl_same_csr_outstanding	47.630s	10.984ms	20	20	100.00
V2		TOTAL			684	692	98.84
V2S	tl_intg_err	sysrst_ctrl_sec_cm	1.894m	42.012ms	5	5	100.00
		sysrst_ctrl_tl_intg_err	1.993m	42.407ms	20	20	100.00
V2S	sec_cm_bus_integrity	sysrst_ctrl_tl_intg_err	1.993m	42.407ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	sysrst_ctrl_stress_all_with_rand_reset	4.396m	1.419s	42	50	84.00
V3		TOTAL			42	50	84.00
		TOTAL			915	932	98.18

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	8	88.89
V2	15	15	12	80.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.10	99.44	96.81	100.00	98.08	98.93	99.71	93.70

Failure Buckets

UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) has 7 failures:

Test sysrst_ctrl_ultra_low_pwr has 5 failures.

2.sysrst_ctrl_ultra_low_pwr.90644471697245321972907608728562357728454159074617033560918174454706247881590
Line 558, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_ultra_low_pwr/latest/run.log

  UVM_ERROR @ 3992620244 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_INFO @ 4005120244 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:81) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a H2L transition on pwrb_in_i
  UVM_INFO @ 8335120244 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:81) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a H2L transition on pwrb_in_i
  UVM_INFO @ 11480120244 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
  UVM_INFO @ 11514414540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

7.sysrst_ctrl_ultra_low_pwr.82784241712838298795005748305774476368524400975386868790184446572993518567053
Line 558, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_ultra_low_pwr/latest/run.log

  UVM_ERROR @ 2498926576 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_ERROR @ 3636426576 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 3636426576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Test sysrst_ctrl_stress_all_with_rand_reset has 2 failures.

20.sysrst_ctrl_stress_all_with_rand_reset.101994306044424585378257204478744906458717115906010331264599573390845830511373
Line 624, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 23482824160 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_INFO @ 23575324160 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:66) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a HIGH level on ac_present_i
  UVM_INFO @ 25120324160 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
  UVM_INFO @ 25126940319 ps: (sysrst_ctrl_stress_all_vseq.sv:52) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_stress_all_vseq] body: executing sequence sysrst_ctrl_pin_override_vseq
  UVM_INFO @ 27125344914 ps: (sysrst_ctrl_pin_override_vseq.sv:53) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_pin_override_vseq] Starting the body from pin_override_vseq

21.sysrst_ctrl_stress_all_with_rand_reset.62683302414677056223418073544782241419464860502592663100846460212353570612752
Line 599, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 20989994298 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_INFO @ 21097494298 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:66) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a HIGH level on ac_present_i
  UVM_INFO @ 23262494298 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
  UVM_INFO @ 23267033826 ps: (sysrst_ctrl_stress_all_vseq.sv:52) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_stress_all_vseq] body: executing sequence sysrst_ctrl_common_vseq
  UVM_INFO @ 25262514346 ps: (cip_base_vseq.sv:442) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] Running intr test iteration 1/6

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sysrst_ctrl_reg_block.combo_intr_status reset value: * has 2 failures:

Test sysrst_ctrl_combo_detect_ec_rst has 1 failures.

3.sysrst_ctrl_combo_detect_ec_rst.86082139566686438897531089709816264865202780429037976401941594338088079302474
Line 559, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_combo_detect_ec_rst/latest/run.log

  UVM_ERROR @ 2182697138 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sysrst_ctrl_reg_block.combo_intr_status reset value: 0x0
  UVM_INFO @ 2420810114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---