Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
93.90	93.90	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	93.90	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.90	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	5	57	91.94

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	5	26	83.87	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1829

1

T12

16

T5

10

T8

1

auto[1]

611

1

T5

14

T7

9

T8

2

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1734

1

T12

16

T5

18

T7

9

auto[1]

706

1

T5

6

T8

3

T37

11

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1961

1

T12

16

T5

24

T7

5

auto[1]

479

1

T7

4

T8

2

T37

11

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1845

1

T12

16

T5

23

T7

9

auto[1]

595

1

T5

1

T8

1

T37

2

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2245

1

T12

16

T5

23

T7

9

auto[1]

195

1

T5

1

T37

6

T30

4

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2276

1

T12

16

T5

21

T7

9

auto[1]

164

1

T5

3

T30

1

T69

1

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2289

1

T12

16

T5

14

T7

9

auto[1]

151

1

T5

10

T37

10

T30

1

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2218

1

T12

12

T5

24

T7

9

auto[1]

222

1

T12

4

T37

11

T30

6

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2238

1

T12

16

T5

19

T7

9

auto[1]

202

1

T5

5

T37

13

T30

3

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1776

1

T12

12

T5

20

T7

2

auto[1]

664

1

T12

4

T5

4

T7

7

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	5	26	83.87	5
Automatically Generated Cross Bins	31	5	26	83.87	5
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[1]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	1034	1			T7	7		T8	3		T27	10
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	50	1			T69	2		T118	1		T250	6
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	32	1			T5	5		T249	5		T333	1
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	19	1			T377	5		T378	9		T237	4
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	55	1			T12	4		T253	4		T134	5
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	15	1			T30	3		T249	4		T379	2
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	50	1			T37	6		T30	3		T249	3
auto[0]	auto[0]	auto[1]	auto[1]	auto[1]	17	1			T37	4		T380	5		T237	3
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	32	1			T5	6		T37	3		T130	4
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	18	1			T5	1		T249	4		T134	3
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	10	1			T381	5		T382	5		-	-
auto[0]	auto[1]	auto[0]	auto[1]	auto[1]	2	1			T37	2		-	-		-	-
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	20	1			T118	1		T250	5		T383	1
auto[0]	auto[1]	auto[1]	auto[0]	auto[1]	4	1			T384	2		T385	2		-	-
auto[0]	auto[1]	auto[1]	auto[1]	auto[0]	6	1			T386	6		-	-		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	53	1			T253	6		T264	4		T377	12
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	6	1			T250	2		T237	4		-	-
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	16	1			T360	2		T387	1		T371	4
auto[1]	auto[0]	auto[0]	auto[1]	auto[1]	8	1			T388	5		T378	3		-	-
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	7	1			T118	1		T386	2		T389	4
auto[1]	auto[0]	auto[1]	auto[1]	auto[0]	5	1			T390	3		T385	2		-	-
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	33	1			T5	3		T69	1		T88	7
auto[1]	auto[1]	auto[0]	auto[0]	auto[1]	1	1			T30	1		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[1]	auto[0]	4	1			T118	1		T391	3		-	-
auto[1]	auto[1]	auto[0]	auto[1]	auto[1]	2	1			T88	2		-	-		-	-
auto[1]	auto[1]	auto[1]	auto[0]	auto[0]	4	1			T386	2		T371	2		-	-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

121

1

T5

6

T67

9

T28

9

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

119

1

T12

4

T33

1

T249

4

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

75

1

T5

3

T7

5

T37

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

132

1

T37

2

T30

1

T87

9

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

29

1

T88

7

T118

1

T313

4

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

71

1

T33

1

T313

4

T167

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

41

1

T67

2

T269

3

T361

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

67

1

T89

13

T249

3

T392

10

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

54

1

T27

5

T87

2

T118

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

42

1

T265

5

T393

7

T394

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

27

1

T7

2

T55

1

T330

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

37

1

T313

5

T255

2

T360

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

21

1

T27

4

T120

2

T103

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

19

1

T87

1

T395

2

T83

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

15

1

T96

1

T233

8

T396

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

192

1

T120

8

T249

5

T250

6

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

74

1

T5

5

T118

1

T120

4

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

72

1

T30

3

T249

4

T361

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

27

1

T67

2

T362

4

T255

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

78

1

T28

5

T359

5

T393

8

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

15

1

T28

3

T57

1

T167

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

28

1

T5

1

T8

1

T55

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

10

1

T27

1

T359

1

T101

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

32

1

T37

4

T30

3

T164

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

23

1

T8

2

T37

6

T89

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

25

1

T254

3

T94

3

T393

5

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

11

1

T179

1

T267

6

T297

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

22

1

T118

1

T167

2

T100

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

6

1

T269

1

T164

1

T397

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

14

1

T69

2

T269

2

T130

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

4

1

T55

1

T191

1

T396

2

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded