Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.09	99.29	96.71	100.00	96.15	98.74	99.42	89.30

Total tests in report: 916

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
56.57	56.57	73.26	73.26	61.00	61.00	91.10	91.10	13.46	13.46	75.93	75.93	58.77	58.77	22.48	22.48	/workspace/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.4080375685
72.04	15.47	89.16	15.90	82.23	21.23	96.35	5.25	33.97	20.51	89.65	13.72	80.35	21.58	32.61	10.12	/workspace/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.2048105659
78.81	6.76	92.87	3.71	86.07	3.84	96.80	0.46	58.33	24.36	92.75	3.11	89.21	8.86	35.62	3.01	/workspace/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.2249995996
81.82	3.01	94.51	1.64	88.52	2.45	97.03	0.23	58.97	0.64	94.27	1.52	89.98	0.77	49.43	13.81	/workspace/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.3663675241
84.32	2.50	95.67	1.16	90.22	1.69	97.03	0.00	72.44	13.46	95.49	1.22	89.98	0.00	49.43	0.00	/workspace/coverage/default/0.sysrst_ctrl_feature_disable.2149303667
86.67	2.35	97.16	1.49	92.16	1.95	97.49	0.46	80.13	7.69	96.82	1.33	93.45	3.47	49.48	0.05	/workspace/coverage/default/11.sysrst_ctrl_ultra_low_pwr.868453119
88.50	1.83	97.26	0.09	92.34	0.18	97.49	0.00	81.41	1.28	97.01	0.18	93.83	0.39	60.18	10.70	/workspace/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.1396379863
89.81	1.31	97.33	0.07	93.60	1.26	98.17	0.68	81.41	0.00	97.12	0.11	93.83	0.00	67.19	7.01	/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.3853209809
90.90	1.09	97.44	0.11	93.68	0.08	98.17	0.00	82.69	1.28	97.26	0.15	94.22	0.39	72.79	5.61	/workspace/coverage/default/18.sysrst_ctrl_stress_all_with_rand_reset.2809033984
91.92	1.02	97.84	0.39	93.96	0.28	98.17	0.00	85.26	2.56	97.63	0.37	96.63	2.41	73.94	1.14	/workspace/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.3826930767
92.80	0.89	98.13	0.30	94.06	0.10	98.17	0.00	86.54	1.28	97.74	0.11	96.63	0.00	78.35	4.41	/workspace/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.500415350
93.22	0.42	98.19	0.06	94.14	0.08	98.17	0.00	87.18	0.64	97.78	0.04	96.63	0.00	80.48	2.13	/workspace/coverage/default/42.sysrst_ctrl_combo_detect.1302975943
93.63	0.41	98.43	0.24	94.31	0.18	98.17	0.00	89.10	1.92	97.89	0.11	97.01	0.39	80.48	0.00	/workspace/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.879829491
94.01	0.39	98.53	0.09	94.39	0.08	98.17	0.00	91.03	1.92	98.00	0.11	97.30	0.29	80.69	0.21	/workspace/coverage/default/27.sysrst_ctrl_stress_all.1607587774
94.32	0.31	98.62	0.09	94.51	0.13	98.17	0.00	92.31	1.28	98.11	0.11	97.69	0.39	80.84	0.16	/workspace/coverage/default/32.sysrst_ctrl_stress_all.265829094
94.61	0.28	98.62	0.00	94.54	0.03	99.77	1.60	92.31	0.00	98.11	0.00	97.78	0.10	81.10	0.26	/workspace/coverage/default/1.sysrst_ctrl_sec_cm.82815397
94.86	0.25	98.71	0.09	94.59	0.05	99.77	0.00	93.59	1.28	98.23	0.11	97.98	0.19	81.15	0.05	/workspace/coverage/default/25.sysrst_ctrl_stress_all_with_rand_reset.263773528
95.11	0.25	98.77	0.06	94.69	0.10	99.77	0.00	93.59	0.00	98.23	0.00	98.07	0.10	82.66	1.51	/workspace/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.1287586138
95.26	0.15	98.81	0.04	94.74	0.05	99.77	0.00	93.59	0.00	98.23	0.00	98.07	0.00	83.64	0.99	/workspace/coverage/default/20.sysrst_ctrl_combo_detect_with_pre_cond.3914926170
95.41	0.15	98.81	0.00	95.63	0.88	99.77	0.00	93.59	0.00	98.23	0.00	98.07	0.00	83.80	0.16	/workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.537655637
95.56	0.15	98.86	0.06	95.70	0.08	99.77	0.00	94.23	0.64	98.30	0.07	98.27	0.19	83.80	0.00	/workspace/coverage/default/1.sysrst_ctrl_edge_detect.4188150211
95.70	0.14	98.90	0.04	95.73	0.03	99.77	0.00	94.87	0.64	98.34	0.04	98.36	0.10	83.96	0.16	/workspace/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.4269762361
95.84	0.13	98.96	0.06	95.75	0.03	99.77	0.00	95.51	0.64	98.41	0.07	98.46	0.10	84.01	0.05	/workspace/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.1117628903
95.96	0.12	98.99	0.04	95.75	0.00	99.77	0.00	95.51	0.00	98.41	0.00	98.46	0.00	84.84	0.83	/workspace/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.2784689195
96.08	0.12	99.03	0.04	95.78	0.03	99.77	0.00	96.15	0.64	98.45	0.04	98.55	0.10	84.84	0.00	/workspace/coverage/default/40.sysrst_ctrl_edge_detect.3199571374
96.19	0.11	99.03	0.00	95.88	0.10	99.77	0.00	96.15	0.00	98.45	0.00	99.23	0.67	84.84	0.00	/workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.2062544555
96.28	0.09	99.07	0.04	95.90	0.03	99.77	0.00	96.15	0.00	98.45	0.00	99.33	0.10	85.31	0.47	/workspace/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.1749179746
96.37	0.09	99.07	0.00	95.90	0.00	99.77	0.00	96.15	0.00	98.45	0.00	99.33	0.00	85.93	0.62	/workspace/coverage/default/8.sysrst_ctrl_combo_detect.87336135
96.43	0.06	99.09	0.02	95.93	0.03	99.77	0.00	96.15	0.00	98.48	0.04	99.33	0.00	86.29	0.36	/workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.404468656
96.49	0.05	99.09	0.00	96.31	0.38	99.77	0.00	96.15	0.00	98.48	0.00	99.33	0.00	86.29	0.00	/workspace/coverage/default/1.sysrst_ctrl_feature_disable.33422560
96.54	0.05	99.09	0.00	96.31	0.00	99.77	0.00	96.15	0.00	98.48	0.00	99.33	0.00	86.66	0.36	/workspace/coverage/default/11.sysrst_ctrl_auto_blk_key_output.1966605438
96.59	0.05	99.14	0.06	96.39	0.08	100.00	0.23	96.15	0.00	98.48	0.00	99.33	0.00	86.66	0.00	/workspace/coverage/default/0.sysrst_ctrl_alert_test.1080130548
96.64	0.05	99.18	0.04	96.54	0.15	100.00	0.00	96.15	0.00	98.56	0.07	99.42	0.10	86.66	0.00	/workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.3924855863
96.69	0.04	99.18	0.00	96.54	0.00	100.00	0.00	96.15	0.00	98.56	0.00	99.42	0.00	86.97	0.31	/workspace/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.596348190
96.73	0.04	99.18	0.00	96.54	0.00	100.00	0.00	96.15	0.00	98.56	0.00	99.42	0.00	87.28	0.31	/workspace/coverage/default/4.sysrst_ctrl_stress_all.2019047777
96.76	0.03	99.18	0.00	96.54	0.00	100.00	0.00	96.15	0.00	98.56	0.00	99.42	0.00	87.49	0.21	/workspace/coverage/default/10.sysrst_ctrl_stress_all_with_rand_reset.2008163019
96.79	0.03	99.18	0.00	96.54	0.00	100.00	0.00	96.15	0.00	98.56	0.00	99.42	0.00	87.69	0.21	/workspace/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.2273214744
96.82	0.03	99.18	0.00	96.54	0.00	100.00	0.00	96.15	0.00	98.56	0.00	99.42	0.00	87.90	0.21	/workspace/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.3610030979
96.84	0.02	99.20	0.02	96.54	0.00	100.00	0.00	96.15	0.00	98.60	0.04	99.42	0.00	88.01	0.10	/workspace/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.525005425
96.87	0.02	99.20	0.00	96.54	0.00	100.00	0.00	96.15	0.00	98.60	0.00	99.42	0.00	88.16	0.16	/workspace/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.1954125708
96.89	0.02	99.20	0.00	96.54	0.00	100.00	0.00	96.15	0.00	98.60	0.00	99.42	0.00	88.32	0.16	/workspace/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.3296679304
96.91	0.02	99.20	0.00	96.66	0.13	100.00	0.00	96.15	0.00	98.60	0.00	99.42	0.00	88.32	0.00	/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.3244657823
96.92	0.01	99.20	0.00	96.66	0.00	100.00	0.00	96.15	0.00	98.60	0.00	99.42	0.00	88.42	0.10	/workspace/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.2403132461
96.94	0.01	99.20	0.00	96.66	0.00	100.00	0.00	96.15	0.00	98.60	0.00	99.42	0.00	88.53	0.10	/workspace/coverage/default/13.sysrst_ctrl_combo_detect.3829934275
96.95	0.01	99.20	0.00	96.66	0.00	100.00	0.00	96.15	0.00	98.60	0.00	99.42	0.00	88.63	0.10	/workspace/coverage/default/15.sysrst_ctrl_combo_detect_with_pre_cond.477672343
96.97	0.01	99.20	0.00	96.66	0.00	100.00	0.00	96.15	0.00	98.60	0.00	99.42	0.00	88.73	0.10	/workspace/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.2479282615
96.98	0.01	99.20	0.00	96.66	0.00	100.00	0.00	96.15	0.00	98.60	0.00	99.42	0.00	88.84	0.10	/workspace/coverage/default/25.sysrst_ctrl_in_out_inverted.3315845881
97.00	0.01	99.20	0.00	96.66	0.00	100.00	0.00	96.15	0.00	98.60	0.00	99.42	0.00	88.94	0.10	/workspace/coverage/default/7.sysrst_ctrl_combo_detect.4164510396
97.00	0.01	99.22	0.02	96.66	0.00	100.00	0.00	96.15	0.00	98.63	0.04	99.42	0.00	88.94	0.00	/workspace/coverage/default/2.sysrst_ctrl_edge_detect.1977210606
97.01	0.01	99.23	0.02	96.66	0.00	100.00	0.00	96.15	0.00	98.67	0.04	99.42	0.00	88.94	0.00	/workspace/coverage/default/3.sysrst_ctrl_edge_detect.1388484214
97.02	0.01	99.25	0.02	96.66	0.00	100.00	0.00	96.15	0.00	98.71	0.04	99.42	0.00	88.94	0.00	/workspace/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.3041664312
97.03	0.01	99.27	0.02	96.66	0.00	100.00	0.00	96.15	0.00	98.74	0.04	99.42	0.00	88.94	0.00	/workspace/coverage/default/34.sysrst_ctrl_stress_all.3946149419
97.04	0.01	99.27	0.00	96.66	0.00	100.00	0.00	96.15	0.00	98.74	0.00	99.42	0.00	88.99	0.05	/workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.384187974
97.04	0.01	99.27	0.00	96.66	0.00	100.00	0.00	96.15	0.00	98.74	0.00	99.42	0.00	89.04	0.05	/workspace/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.3352050076
97.05	0.01	99.27	0.00	96.66	0.00	100.00	0.00	96.15	0.00	98.74	0.00	99.42	0.00	89.10	0.05	/workspace/coverage/default/27.sysrst_ctrl_combo_detect_with_pre_cond.1328720244
97.06	0.01	99.27	0.00	96.66	0.00	100.00	0.00	96.15	0.00	98.74	0.00	99.42	0.00	89.15	0.05	/workspace/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.925500799
97.06	0.01	99.27	0.00	96.66	0.00	100.00	0.00	96.15	0.00	98.74	0.00	99.42	0.00	89.20	0.05	/workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.137873100
97.07	0.01	99.27	0.00	96.66	0.00	100.00	0.00	96.15	0.00	98.74	0.00	99.42	0.00	89.25	0.05	/workspace/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.108000444
97.08	0.01	99.27	0.00	96.66	0.00	100.00	0.00	96.15	0.00	98.74	0.00	99.42	0.00	89.30	0.05	/workspace/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.4105749992
97.08	0.01	99.27	0.00	96.69	0.03	100.00	0.00	96.15	0.00	98.74	0.00	99.42	0.00	89.30	0.00	/workspace/coverage/default/26.sysrst_ctrl_combo_detect_with_pre_cond.3720258731
97.09	0.01	99.29	0.02	96.69	0.00	100.00	0.00	96.15	0.00	98.74	0.00	99.42	0.00	89.30	0.00	/workspace/coverage/default/21.sysrst_ctrl_combo_detect_with_pre_cond.1794989845

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.1513152652
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.688514053
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.4101408700
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.672008985
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.3198286244
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.3638885520
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.587719309
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.2610335397
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.1541037469
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.572112546
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.3677776180
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.2523413338
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.3333866868
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.116461920
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.2913867213
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.3823379272
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.1446971962
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.1003724082
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.3419212907
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.4163840910
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.1425984966
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.435742261
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.479503759
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.3779387539
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.2854058331
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.2929598007
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.2777656556
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.1643186375
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.313387251
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.227876289
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.545440792
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.1561459310
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.3419583899
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.3287207928
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.4052155854
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.2647558207
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.3915975831
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.3822676925
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.355839071
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.3640496713
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.3466937989
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.1284830406
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.3431667876
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.2703893886
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.50893446
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.1871358468
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.597304715
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.2531020318
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.2770890023
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.746419934
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.661254140
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.1425637087
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.270460599
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.449201255
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.2763962248
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.379626889
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.1769914511
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.3050116158
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.957441410
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.878867840
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.3031812214
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.3840827443
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.2425405648
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.2182784588
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.557704771
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.47350162
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.3541815021
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/workspace/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.1282745665
/workspace/coverage/default/4.sysrst_ctrl_ultra_low_pwr.1270377388
/workspace/coverage/default/40.sysrst_ctrl_alert_test.2194113098
/workspace/coverage/default/40.sysrst_ctrl_auto_blk_key_output.3929682235
/workspace/coverage/default/40.sysrst_ctrl_combo_detect.3778317634
/workspace/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.2868006755
/workspace/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.2490339748
/workspace/coverage/default/40.sysrst_ctrl_in_out_inverted.2651033988
/workspace/coverage/default/40.sysrst_ctrl_pin_access_test.2044426884
/workspace/coverage/default/40.sysrst_ctrl_pin_override_test.3573638312
/workspace/coverage/default/40.sysrst_ctrl_smoke.2123318492
/workspace/coverage/default/40.sysrst_ctrl_stress_all.1645156885
/workspace/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.4091384432
/workspace/coverage/default/40.sysrst_ctrl_ultra_low_pwr.2380287593
/workspace/coverage/default/41.sysrst_ctrl_alert_test.3783661195
/workspace/coverage/default/41.sysrst_ctrl_auto_blk_key_output.3645489930
/workspace/coverage/default/41.sysrst_ctrl_combo_detect.2744385892
/workspace/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.504174045
/workspace/coverage/default/41.sysrst_ctrl_edge_detect.2712312552
/workspace/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.3489430167
/workspace/coverage/default/41.sysrst_ctrl_in_out_inverted.202914059
/workspace/coverage/default/41.sysrst_ctrl_pin_access_test.2256398164
/workspace/coverage/default/41.sysrst_ctrl_pin_override_test.2020140525
/workspace/coverage/default/41.sysrst_ctrl_smoke.1206069941
/workspace/coverage/default/41.sysrst_ctrl_stress_all.380648537
/workspace/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.2228588255
/workspace/coverage/default/41.sysrst_ctrl_ultra_low_pwr.4149212335
/workspace/coverage/default/42.sysrst_ctrl_alert_test.2393037018
/workspace/coverage/default/42.sysrst_ctrl_auto_blk_key_output.3258242609
/workspace/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.754277564
/workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.676210686
/workspace/coverage/default/42.sysrst_ctrl_edge_detect.943740472
/workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.3639373003
/workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.900288922
/workspace/coverage/default/42.sysrst_ctrl_pin_access_test.1800677636
/workspace/coverage/default/42.sysrst_ctrl_pin_override_test.329491755
/workspace/coverage/default/42.sysrst_ctrl_smoke.138727406
/workspace/coverage/default/42.sysrst_ctrl_stress_all.781983543
/workspace/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.3623749973
/workspace/coverage/default/42.sysrst_ctrl_ultra_low_pwr.1677773745
/workspace/coverage/default/43.sysrst_ctrl_alert_test.3465593688
/workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.1215845667
/workspace/coverage/default/43.sysrst_ctrl_combo_detect.4204375377
/workspace/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.3872442140
/workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.2287132940
/workspace/coverage/default/43.sysrst_ctrl_edge_detect.3167061332
/workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.135196494
/workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.156785436
/workspace/coverage/default/43.sysrst_ctrl_pin_access_test.1819378454
/workspace/coverage/default/43.sysrst_ctrl_pin_override_test.914737528
/workspace/coverage/default/43.sysrst_ctrl_smoke.4139626027
/workspace/coverage/default/43.sysrst_ctrl_stress_all.792206426
/workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.278364248
/workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.1470242369
/workspace/coverage/default/44.sysrst_ctrl_alert_test.2876591195
/workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.2058523443
/workspace/coverage/default/44.sysrst_ctrl_combo_detect.848866984
/workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.1719796698
/workspace/coverage/default/44.sysrst_ctrl_edge_detect.3801287398
/workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.3566029431
/workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.1658081352
/workspace/coverage/default/44.sysrst_ctrl_pin_access_test.2549706312
/workspace/coverage/default/44.sysrst_ctrl_pin_override_test.89311201
/workspace/coverage/default/44.sysrst_ctrl_smoke.4274228267
/workspace/coverage/default/44.sysrst_ctrl_stress_all.2778058588
/workspace/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.565132551
/workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.4100908800
/workspace/coverage/default/45.sysrst_ctrl_alert_test.2624818628
/workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.754542778
/workspace/coverage/default/45.sysrst_ctrl_combo_detect.2457188150
/workspace/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.3066089292
/workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.889203211
/workspace/coverage/default/45.sysrst_ctrl_edge_detect.3101349655
/workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.285589454
/workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.386852439
/workspace/coverage/default/45.sysrst_ctrl_pin_access_test.3493709334
/workspace/coverage/default/45.sysrst_ctrl_pin_override_test.71688326
/workspace/coverage/default/45.sysrst_ctrl_smoke.2884560439
/workspace/coverage/default/45.sysrst_ctrl_stress_all.424123814
/workspace/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.993719265
/workspace/coverage/default/45.sysrst_ctrl_ultra_low_pwr.72864877
/workspace/coverage/default/46.sysrst_ctrl_alert_test.3003863572
/workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.272448279
/workspace/coverage/default/46.sysrst_ctrl_combo_detect.2650045262
/workspace/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.631779347
/workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.2961748874
/workspace/coverage/default/46.sysrst_ctrl_edge_detect.4184783910
/workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.4212936734
/workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.3196263216
/workspace/coverage/default/46.sysrst_ctrl_pin_access_test.2076213240
/workspace/coverage/default/46.sysrst_ctrl_pin_override_test.3498367021
/workspace/coverage/default/46.sysrst_ctrl_smoke.878074514
/workspace/coverage/default/46.sysrst_ctrl_stress_all.1323610797
/workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.3426176801
/workspace/coverage/default/47.sysrst_ctrl_alert_test.2857218702
/workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.3288974723
/workspace/coverage/default/47.sysrst_ctrl_combo_detect.2424475525
/workspace/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.382598572
/workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.3579918896
/workspace/coverage/default/47.sysrst_ctrl_edge_detect.3995164440
/workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.2307428004
/workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.2550801596
/workspace/coverage/default/47.sysrst_ctrl_pin_access_test.3851215724
/workspace/coverage/default/47.sysrst_ctrl_pin_override_test.3320779443
/workspace/coverage/default/47.sysrst_ctrl_smoke.2303261650
/workspace/coverage/default/47.sysrst_ctrl_stress_all.4057421449
/workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.1986823143
/workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.3128056007
/workspace/coverage/default/48.sysrst_ctrl_alert_test.3383551289
/workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.1443940204
/workspace/coverage/default/48.sysrst_ctrl_combo_detect.3052662685
/workspace/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.3134819334
/workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.2413622932
/workspace/coverage/default/48.sysrst_ctrl_edge_detect.2507577384
/workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.3218369252
/workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.3667222506
/workspace/coverage/default/48.sysrst_ctrl_pin_access_test.290422671
/workspace/coverage/default/48.sysrst_ctrl_pin_override_test.3122900799
/workspace/coverage/default/48.sysrst_ctrl_smoke.3538043383
/workspace/coverage/default/48.sysrst_ctrl_stress_all.861927816
/workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.959140796
/workspace/coverage/default/49.sysrst_ctrl_alert_test.3815761170
/workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.885544829
/workspace/coverage/default/49.sysrst_ctrl_combo_detect.1795753194
/workspace/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.3555091005
/workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.3196997671
/workspace/coverage/default/49.sysrst_ctrl_edge_detect.3337260209
/workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.3272233424
/workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.4246769609
/workspace/coverage/default/49.sysrst_ctrl_pin_access_test.12039611
/workspace/coverage/default/49.sysrst_ctrl_pin_override_test.1805658971
/workspace/coverage/default/49.sysrst_ctrl_smoke.3190329995
/workspace/coverage/default/49.sysrst_ctrl_stress_all.2859004070
/workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.3044044558
/workspace/coverage/default/5.sysrst_ctrl_alert_test.1260245136
/workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.4016314769
/workspace/coverage/default/5.sysrst_ctrl_combo_detect.2465529975
/workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.1193875196
/workspace/coverage/default/5.sysrst_ctrl_edge_detect.259547353
/workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.3860656303
/workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.2722357832
/workspace/coverage/default/5.sysrst_ctrl_pin_access_test.700477912
/workspace/coverage/default/5.sysrst_ctrl_pin_override_test.3404576576
/workspace/coverage/default/5.sysrst_ctrl_smoke.1502827720
/workspace/coverage/default/5.sysrst_ctrl_stress_all.3712760974
/workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.2495561685
/workspace/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.484536339
/workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.1945451491
/workspace/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.625331443
/workspace/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.190782675
/workspace/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.1969431994
/workspace/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.4136697635
/workspace/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.2826359065
/workspace/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.2995033636
/workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.1318870760
/workspace/coverage/default/6.sysrst_ctrl_alert_test.1966447459
/workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.3704478199
/workspace/coverage/default/6.sysrst_ctrl_combo_detect.1626315378
/workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.2030601492
/workspace/coverage/default/6.sysrst_ctrl_edge_detect.754761377
/workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.3112596678
/workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.1543105111
/workspace/coverage/default/6.sysrst_ctrl_pin_access_test.877026690
/workspace/coverage/default/6.sysrst_ctrl_pin_override_test.827866100
/workspace/coverage/default/6.sysrst_ctrl_smoke.3780112493
/workspace/coverage/default/6.sysrst_ctrl_stress_all.3559098435
/workspace/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.794293600
/workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.1180530588
/workspace/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.1637967024
/workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.4017034921
/workspace/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.3912648010
/workspace/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.439400752
/workspace/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.2654373933
/workspace/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.3490056649
/workspace/coverage/default/7.sysrst_ctrl_alert_test.3604309685
/workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.1004952196
/workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.1107874862
/workspace/coverage/default/7.sysrst_ctrl_edge_detect.3137274561
/workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.915946313
/workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.239416839
/workspace/coverage/default/7.sysrst_ctrl_pin_access_test.219771126
/workspace/coverage/default/7.sysrst_ctrl_pin_override_test.454689269
/workspace/coverage/default/7.sysrst_ctrl_smoke.1639424205
/workspace/coverage/default/7.sysrst_ctrl_stress_all.3685296657
/workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.140192423
/workspace/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.1014073617
/workspace/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.796205765
/workspace/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.3089128701
/workspace/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.275611610
/workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.3570162891
/workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.1672710937
/workspace/coverage/default/8.sysrst_ctrl_alert_test.532840458
/workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.802490684
/workspace/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.674575292
/workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.1775229144
/workspace/coverage/default/8.sysrst_ctrl_edge_detect.952157462
/workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.2467592942
/workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.1660657709
/workspace/coverage/default/8.sysrst_ctrl_pin_access_test.1476001625
/workspace/coverage/default/8.sysrst_ctrl_pin_override_test.3096953294
/workspace/coverage/default/8.sysrst_ctrl_smoke.2208616247
/workspace/coverage/default/8.sysrst_ctrl_stress_all.3472931769
/workspace/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.122689876
/workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.1838599483
/workspace/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.444147407
/workspace/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.3081807866
/workspace/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.3431894275
/workspace/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.2777284079
/workspace/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.1258558602
/workspace/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.2792174237
/workspace/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.331185960
/workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.2594234409
/workspace/coverage/default/9.sysrst_ctrl_alert_test.2295110801
/workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.391637699
/workspace/coverage/default/9.sysrst_ctrl_combo_detect.2005396817
/workspace/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.1837051026
/workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.138354002
/workspace/coverage/default/9.sysrst_ctrl_edge_detect.2655965992
/workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.1467514010
/workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.3875144298
/workspace/coverage/default/9.sysrst_ctrl_pin_access_test.3677112514
/workspace/coverage/default/9.sysrst_ctrl_pin_override_test.3836683102
/workspace/coverage/default/9.sysrst_ctrl_smoke.2164322758
/workspace/coverage/default/9.sysrst_ctrl_stress_all.32412320
/workspace/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.3174335634
/workspace/coverage/default/9.sysrst_ctrl_ultra_low_pwr.1168507741
/workspace/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.3374036485
/workspace/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.813670269
/workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.92328450
/workspace/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.2867972135
/workspace/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.1112444550
/workspace/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.2124880953
/workspace/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.3936702653

Total test records in report: 916

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.4080375685	Mar 28 12:55:19 PM PDT 24	Mar 28 12:59:48 PM PDT 24	1767678367546 ps
T2	/workspace/coverage/default/14.sysrst_ctrl_ultra_low_pwr.2479701518	Mar 28 12:55:18 PM PDT 24	Mar 28 12:55:25 PM PDT 24	2994475371 ps
T4	/workspace/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.964380518	Mar 28 12:55:53 PM PDT 24	Mar 28 12:56:00 PM PDT 24	2610315638 ps
T12	/workspace/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.1969431994	Mar 28 12:57:07 PM PDT 24	Mar 28 12:58:00 PM PDT 24	76177342521 ps
T13	/workspace/coverage/default/48.sysrst_ctrl_smoke.3538043383	Mar 28 12:56:38 PM PDT 24	Mar 28 12:56:44 PM PDT 24	2107988115 ps
T3	/workspace/coverage/default/18.sysrst_ctrl_stress_all.1262469029	Mar 28 12:55:37 PM PDT 24	Mar 28 12:55:46 PM PDT 24	18042763520 ps
T5	/workspace/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.2048105659	Mar 28 12:57:10 PM PDT 24	Mar 28 12:58:17 PM PDT 24	92236161618 ps
T14	/workspace/coverage/default/0.sysrst_ctrl_alert_test.1080130548	Mar 28 12:55:03 PM PDT 24	Mar 28 12:55:09 PM PDT 24	2018124604 ps
T15	/workspace/coverage/default/1.sysrst_ctrl_in_out_inverted.2410428669	Mar 28 12:54:48 PM PDT 24	Mar 28 12:54:56 PM PDT 24	2470363089 ps
T16	/workspace/coverage/default/15.sysrst_ctrl_in_out_inverted.1705168549	Mar 28 12:55:24 PM PDT 24	Mar 28 12:55:31 PM PDT 24	2472654050 ps
T48	/workspace/coverage/default/10.sysrst_ctrl_pin_access_test.3245597605	Mar 28 12:55:15 PM PDT 24	Mar 28 12:55:22 PM PDT 24	2256505086 ps
T6	/workspace/coverage/default/33.sysrst_ctrl_edge_detect.3580288183	Mar 28 12:56:06 PM PDT 24	Mar 28 12:56:13 PM PDT 24	2831961867 ps
T21	/workspace/coverage/default/34.sysrst_ctrl_in_out_inverted.2771086101	Mar 28 12:56:02 PM PDT 24	Mar 28 12:56:09 PM PDT 24	2471710509 ps
T7	/workspace/coverage/default/2.sysrst_ctrl_combo_detect.3332471992	Mar 28 12:54:46 PM PDT 24	Mar 28 12:55:44 PM PDT 24	79220401714 ps
T49	/workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.2307428004	Mar 28 12:56:42 PM PDT 24	Mar 28 12:56:45 PM PDT 24	2629574745 ps
T8	/workspace/coverage/default/26.sysrst_ctrl_combo_detect.1064941205	Mar 28 12:55:51 PM PDT 24	Mar 28 12:58:41 PM PDT 24	66563349733 ps
T23	/workspace/coverage/default/30.sysrst_ctrl_combo_detect_with_pre_cond.2951633147	Mar 28 12:55:52 PM PDT 24	Mar 28 12:56:21 PM PDT 24	22587815698 ps
T9	/workspace/coverage/default/6.sysrst_ctrl_edge_detect.754761377	Mar 28 12:55:08 PM PDT 24	Mar 28 12:55:17 PM PDT 24	4191472401 ps
T90	/workspace/coverage/default/1.sysrst_ctrl_sec_cm.82815397	Mar 28 12:54:50 PM PDT 24	Mar 28 12:56:45 PM PDT 24	42013310499 ps
T10	/workspace/coverage/default/18.sysrst_ctrl_edge_detect.1687542441	Mar 28 12:55:42 PM PDT 24	Mar 28 12:55:45 PM PDT 24	3327853549 ps
T91	/workspace/coverage/default/14.sysrst_ctrl_smoke.3936817644	Mar 28 12:55:15 PM PDT 24	Mar 28 12:55:17 PM PDT 24	2123729326 ps
T108	/workspace/coverage/default/1.sysrst_ctrl_smoke.3500834138	Mar 28 12:54:45 PM PDT 24	Mar 28 12:54:47 PM PDT 24	2126884275 ps
T58	/workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.3667222506	Mar 28 12:56:36 PM PDT 24	Mar 28 12:56:43 PM PDT 24	2458593176 ps
T11	/workspace/coverage/default/43.sysrst_ctrl_edge_detect.3167061332	Mar 28 12:56:24 PM PDT 24	Mar 28 12:56:27 PM PDT 24	3232880136 ps
T31	/workspace/coverage/default/36.sysrst_ctrl_edge_detect.2665035029	Mar 28 12:56:05 PM PDT 24	Mar 28 12:56:57 PM PDT 24	483385461857 ps
T163	/workspace/coverage/default/18.sysrst_ctrl_smoke.3862368016	Mar 28 12:55:18 PM PDT 24	Mar 28 12:55:19 PM PDT 24	2149527051 ps
T32	/workspace/coverage/default/16.sysrst_ctrl_stress_all.1134548092	Mar 28 12:55:17 PM PDT 24	Mar 28 12:55:26 PM PDT 24	12838012555 ps
T52	/workspace/coverage/default/17.sysrst_ctrl_ec_pwr_on_rst.1313352768	Mar 28 12:55:29 PM PDT 24	Mar 28 12:55:40 PM PDT 24	4021560892 ps
T35	/workspace/coverage/default/23.sysrst_ctrl_edge_detect.233442046	Mar 28 12:55:50 PM PDT 24	Mar 28 12:55:53 PM PDT 24	4486353144 ps
T186	/workspace/coverage/default/28.sysrst_ctrl_pin_access_test.531735681	Mar 28 12:55:55 PM PDT 24	Mar 28 12:55:59 PM PDT 24	2202755260 ps
T64	/workspace/coverage/default/25.sysrst_ctrl_flash_wr_prot_out.998071498	Mar 28 12:55:49 PM PDT 24	Mar 28 12:55:56 PM PDT 24	2612330155 ps
T37	/workspace/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.1749179746	Mar 28 12:55:00 PM PDT 24	Mar 28 12:56:59 PM PDT 24	87532700822 ps
T59	/workspace/coverage/default/40.sysrst_ctrl_in_out_inverted.2651033988	Mar 28 12:56:15 PM PDT 24	Mar 28 12:56:19 PM PDT 24	2489944136 ps
T187	/workspace/coverage/default/36.sysrst_ctrl_pin_access_test.1521207004	Mar 28 12:56:03 PM PDT 24	Mar 28 12:56:09 PM PDT 24	2020511551 ps
T188	/workspace/coverage/default/5.sysrst_ctrl_pin_access_test.700477912	Mar 28 12:55:04 PM PDT 24	Mar 28 12:55:08 PM PDT 24	2220346484 ps
T65	/workspace/coverage/default/19.sysrst_ctrl_flash_wr_prot_out.1242044204	Mar 28 12:55:35 PM PDT 24	Mar 28 12:55:38 PM PDT 24	2637722324 ps
T22	/workspace/coverage/default/23.sysrst_ctrl_auto_blk_key_output.4207474333	Mar 28 12:55:51 PM PDT 24	Mar 28 12:55:54 PM PDT 24	3126450096 ps
T38	/workspace/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.1019745601	Mar 28 12:56:06 PM PDT 24	Mar 28 12:57:11 PM PDT 24	25578119081 ps
T245	/workspace/coverage/default/7.sysrst_ctrl_alert_test.3604309685	Mar 28 12:55:06 PM PDT 24	Mar 28 12:55:13 PM PDT 24	2011271045 ps
T246	/workspace/coverage/default/28.sysrst_ctrl_smoke.1772271068	Mar 28 12:56:04 PM PDT 24	Mar 28 12:56:10 PM PDT 24	2110086660 ps
T39	/workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.802490684	Mar 28 12:55:17 PM PDT 24	Mar 28 12:55:28 PM PDT 24	3548739042 ps
T247	/workspace/coverage/default/48.sysrst_ctrl_alert_test.3383551289	Mar 28 12:57:05 PM PDT 24	Mar 28 12:57:11 PM PDT 24	2010742299 ps
T53	/workspace/coverage/default/37.sysrst_ctrl_ec_pwr_on_rst.4117940849	Mar 28 12:56:10 PM PDT 24	Mar 28 12:56:13 PM PDT 24	4006736143 ps
T40	/workspace/coverage/default/20.sysrst_ctrl_auto_blk_key_output.2117236818	Mar 28 12:55:30 PM PDT 24	Mar 28 12:58:07 PM PDT 24	253214412558 ps
T248	/workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.1719796698	Mar 28 12:56:17 PM PDT 24	Mar 28 12:56:20 PM PDT 24	3144361502 ps
T36	/workspace/coverage/default/7.sysrst_ctrl_edge_detect.3137274561	Mar 28 12:55:05 PM PDT 24	Mar 28 12:55:06 PM PDT 24	3612376887 ps
T41	/workspace/coverage/default/39.sysrst_ctrl_auto_blk_key_output.343057961	Mar 28 12:56:07 PM PDT 24	Mar 28 12:56:15 PM PDT 24	12614064128 ps
T184	/workspace/coverage/default/26.sysrst_ctrl_pin_access_test.738386541	Mar 28 12:55:56 PM PDT 24	Mar 28 12:55:58 PM PDT 24	2255969220 ps
T66	/workspace/coverage/default/36.sysrst_ctrl_pin_override_test.2556290777	Mar 28 12:56:03 PM PDT 24	Mar 28 12:56:07 PM PDT 24	2516822858 ps
T30	/workspace/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.500415350	Mar 28 12:55:07 PM PDT 24	Mar 28 12:57:00 PM PDT 24	80280122335 ps
T20	/workspace/coverage/default/31.sysrst_ctrl_ultra_low_pwr.3465937479	Mar 28 12:55:55 PM PDT 24	Mar 28 12:55:59 PM PDT 24	2738293355 ps
T51	/workspace/coverage/default/37.sysrst_ctrl_ultra_low_pwr.1175713689	Mar 28 12:56:09 PM PDT 24	Mar 28 12:56:11 PM PDT 24	4160492136 ps
T42	/workspace/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.879829491	Mar 28 12:55:06 PM PDT 24	Mar 28 12:55:38 PM PDT 24	22590696352 ps
T27	/workspace/coverage/default/8.sysrst_ctrl_combo_detect.87336135	Mar 28 12:55:07 PM PDT 24	Mar 28 12:56:04 PM PDT 24	82291744561 ps
T43	/workspace/coverage/default/11.sysrst_ctrl_auto_blk_key_output.1966605438	Mar 28 12:55:06 PM PDT 24	Mar 28 01:03:40 PM PDT 24	197261714827 ps
T44	/workspace/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.2124880953	Mar 28 12:57:08 PM PDT 24	Mar 28 12:57:22 PM PDT 24	23855008801 ps
T67	/workspace/coverage/default/46.sysrst_ctrl_stress_all.1323610797	Mar 28 12:56:39 PM PDT 24	Mar 28 12:57:00 PM PDT 24	129964421973 ps
T146	/workspace/coverage/default/27.sysrst_ctrl_smoke.3000514546	Mar 28 12:55:48 PM PDT 24	Mar 28 12:55:51 PM PDT 24	2136231829 ps
T28	/workspace/coverage/default/46.sysrst_ctrl_combo_detect.2650045262	Mar 28 12:56:39 PM PDT 24	Mar 28 01:02:17 PM PDT 24	121883410088 ps
T147	/workspace/coverage/default/38.sysrst_ctrl_ec_pwr_on_rst.675994093	Mar 28 12:56:12 PM PDT 24	Mar 28 12:56:16 PM PDT 24	4720242792 ps
T76	/workspace/coverage/default/18.sysrst_ctrl_combo_detect.3879865208	Mar 28 12:55:29 PM PDT 24	Mar 28 12:55:43 PM PDT 24	31583899987 ps
T87	/workspace/coverage/default/41.sysrst_ctrl_combo_detect.2744385892	Mar 28 12:56:25 PM PDT 24	Mar 28 01:01:02 PM PDT 24	134961832482 ps
T259	/workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.2961748874	Mar 28 12:56:40 PM PDT 24	Mar 28 12:56:49 PM PDT 24	3131374433 ps
T69	/workspace/coverage/default/21.sysrst_ctrl_combo_detect_with_pre_cond.1794989845	Mar 28 12:55:51 PM PDT 24	Mar 28 12:57:03 PM PDT 24	56435502532 ps
T68	/workspace/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.1270412352	Mar 28 12:55:26 PM PDT 24	Mar 28 12:55:28 PM PDT 24	2623207984 ps
T260	/workspace/coverage/default/39.sysrst_ctrl_alert_test.3916655179	Mar 28 12:56:31 PM PDT 24	Mar 28 12:56:33 PM PDT 24	2029588492 ps
T261	/workspace/coverage/default/3.sysrst_ctrl_pin_access_test.3391649151	Mar 28 12:54:52 PM PDT 24	Mar 28 12:54:53 PM PDT 24	2194207433 ps
T262	/workspace/coverage/default/47.sysrst_ctrl_pin_access_test.3851215724	Mar 28 12:56:40 PM PDT 24	Mar 28 12:56:44 PM PDT 24	2047072910 ps
T60	/workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.239416839	Mar 28 12:55:07 PM PDT 24	Mar 28 12:55:11 PM PDT 24	2463229372 ps
T263	/workspace/coverage/default/47.sysrst_ctrl_smoke.2303261650	Mar 28 12:56:38 PM PDT 24	Mar 28 12:56:44 PM PDT 24	2114301340 ps
T45	/workspace/coverage/default/44.sysrst_ctrl_stress_all.2778058588	Mar 28 12:56:19 PM PDT 24	Mar 28 12:57:01 PM PDT 24	14806901545 ps
T70	/workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.4017034921	Mar 28 12:57:07 PM PDT 24	Mar 28 12:57:33 PM PDT 24	33836860595 ps
T314	/workspace/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.1717523143	Mar 28 12:55:44 PM PDT 24	Mar 28 12:55:52 PM PDT 24	3131700284 ps
T61	/workspace/coverage/default/31.sysrst_ctrl_in_out_inverted.2624017237	Mar 28 12:56:05 PM PDT 24	Mar 28 12:56:13 PM PDT 24	2453937228 ps
T62	/workspace/coverage/default/25.sysrst_ctrl_in_out_inverted.3315845881	Mar 28 12:55:49 PM PDT 24	Mar 28 12:55:54 PM PDT 24	2466372114 ps
T88	/workspace/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.108000444	Mar 28 12:57:04 PM PDT 24	Mar 28 12:58:11 PM PDT 24	95700539404 ps
T54	/workspace/coverage/default/4.sysrst_ctrl_ultra_low_pwr.1270377388	Mar 28 12:55:04 PM PDT 24	Mar 28 12:55:08 PM PDT 24	4888317285 ps
T141	/workspace/coverage/default/21.sysrst_ctrl_flash_wr_prot_out.1541623577	Mar 28 12:55:45 PM PDT 24	Mar 28 12:55:53 PM PDT 24	2611681634 ps
T29	/workspace/coverage/default/20.sysrst_ctrl_combo_detect.2401952560	Mar 28 12:55:32 PM PDT 24	Mar 28 01:00:20 PM PDT 24	108914160311 ps
T89	/workspace/coverage/default/37.sysrst_ctrl_combo_detect.3121938754	Mar 28 12:56:11 PM PDT 24	Mar 28 01:00:06 PM PDT 24	164799809259 ps
T46	/workspace/coverage/default/17.sysrst_ctrl_stress_all.3710482870	Mar 28 12:55:18 PM PDT 24	Mar 28 12:55:44 PM PDT 24	15596585820 ps
T118	/workspace/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.2784689195	Mar 28 12:57:06 PM PDT 24	Mar 28 01:00:38 PM PDT 24	86850144448 ps
T120	/workspace/coverage/default/35.sysrst_ctrl_combo_detect.3431408524	Mar 28 12:56:04 PM PDT 24	Mar 28 01:02:12 PM PDT 24	135009153073 ps
T142	/workspace/coverage/default/17.sysrst_ctrl_alert_test.1938432350	Mar 28 12:55:23 PM PDT 24	Mar 28 12:55:29 PM PDT 24	2011389627 ps
T33	/workspace/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.2249995996	Mar 28 12:55:55 PM PDT 24	Mar 28 12:56:55 PM PDT 24	64265503989 ps
T143	/workspace/coverage/default/35.sysrst_ctrl_alert_test.871336106	Mar 28 12:56:07 PM PDT 24	Mar 28 12:56:12 PM PDT 24	2010545459 ps
T249	/workspace/coverage/default/33.sysrst_ctrl_combo_detect_with_pre_cond.1997335744	Mar 28 12:56:08 PM PDT 24	Mar 28 01:00:03 PM PDT 24	85559821848 ps
T34	/workspace/coverage/default/25.sysrst_ctrl_edge_detect.749386720	Mar 28 12:55:49 PM PDT 24	Mar 28 12:55:51 PM PDT 24	3918481036 ps
T320	/workspace/coverage/default/2.sysrst_ctrl_pin_override_test.1452847384	Mar 28 12:54:46 PM PDT 24	Mar 28 12:54:53 PM PDT 24	2513861078 ps
T55	/workspace/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.3663675241	Mar 28 12:57:06 PM PDT 24	Mar 28 12:57:52 PM PDT 24	70061491395 ps
T327	/workspace/coverage/default/33.sysrst_ctrl_flash_wr_prot_out.1425879432	Mar 28 12:56:05 PM PDT 24	Mar 28 12:56:08 PM PDT 24	2640873882 ps
T47	/workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.3288974723	Mar 28 12:56:39 PM PDT 24	Mar 28 12:56:42 PM PDT 24	3431525916 ps
T328	/workspace/coverage/default/24.sysrst_ctrl_pin_override_test.895824961	Mar 28 12:55:46 PM PDT 24	Mar 28 12:55:49 PM PDT 24	2526704257 ps
T329	/workspace/coverage/default/14.sysrst_ctrl_pin_override_test.4148441734	Mar 28 12:55:18 PM PDT 24	Mar 28 12:55:20 PM PDT 24	2550745813 ps
T338	/workspace/coverage/default/10.sysrst_ctrl_ec_pwr_on_rst.1463467660	Mar 28 12:55:04 PM PDT 24	Mar 28 12:55:07 PM PDT 24	3327483727 ps
T250	/workspace/coverage/default/20.sysrst_ctrl_combo_detect_with_pre_cond.3914926170	Mar 28 12:55:34 PM PDT 24	Mar 28 01:01:20 PM PDT 24	127629830978 ps
T339	/workspace/coverage/default/5.sysrst_ctrl_smoke.1502827720	Mar 28 12:55:09 PM PDT 24	Mar 28 12:55:16 PM PDT 24	2109479940 ps
T270	/workspace/coverage/default/49.sysrst_ctrl_combo_detect.1795753194	Mar 28 12:57:06 PM PDT 24	Mar 28 01:03:52 PM PDT 24	147522277638 ps
T321	/workspace/coverage/default/40.sysrst_ctrl_pin_override_test.3573638312	Mar 28 12:56:16 PM PDT 24	Mar 28 12:56:19 PM PDT 24	2534915279 ps
T322	/workspace/coverage/default/6.sysrst_ctrl_pin_override_test.827866100	Mar 28 12:55:05 PM PDT 24	Mar 28 12:55:06 PM PDT 24	2608231123 ps
T408	/workspace/coverage/default/12.sysrst_ctrl_alert_test.1050621357	Mar 28 12:55:11 PM PDT 24	Mar 28 12:55:12 PM PDT 24	2093965958 ps
T254	/workspace/coverage/default/23.sysrst_ctrl_combo_detect.2795024906	Mar 28 12:55:53 PM PDT 24	Mar 28 01:01:26 PM PDT 24	123033558154 ps
T63	/workspace/coverage/default/1.sysrst_ctrl_stress_all.259113498	Mar 28 12:54:57 PM PDT 24	Mar 28 12:55:04 PM PDT 24	12170903589 ps
T409	/workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.1193875196	Mar 28 12:55:05 PM PDT 24	Mar 28 12:55:13 PM PDT 24	2705620329 ps
T410	/workspace/coverage/default/16.sysrst_ctrl_flash_wr_prot_out.809246846	Mar 28 12:55:18 PM PDT 24	Mar 28 12:55:20 PM PDT 24	2632990126 ps
T56	/workspace/coverage/default/0.sysrst_ctrl_ultra_low_pwr.1561420143	Mar 28 12:54:49 PM PDT 24	Mar 28 12:54:51 PM PDT 24	2518833108 ps
T411	/workspace/coverage/default/39.sysrst_ctrl_smoke.4000787531	Mar 28 12:56:15 PM PDT 24	Mar 28 12:56:17 PM PDT 24	2136081936 ps
T269	/workspace/coverage/default/13.sysrst_ctrl_combo_detect.3829934275	Mar 28 12:55:15 PM PDT 24	Mar 28 12:56:05 PM PDT 24	76186889944 ps
T253	/workspace/coverage/default/31.sysrst_ctrl_combo_detect_with_pre_cond.2862257269	Mar 28 12:56:01 PM PDT 24	Mar 28 01:00:39 PM PDT 24	103299895089 ps
T412	/workspace/coverage/default/20.sysrst_ctrl_pin_access_test.1672982988	Mar 28 12:55:30 PM PDT 24	Mar 28 12:55:33 PM PDT 24	2094571848 ps
T182	/workspace/coverage/default/19.sysrst_ctrl_edge_detect.370945636	Mar 28 12:55:37 PM PDT 24	Mar 28 12:55:38 PM PDT 24	3358603908 ps
T57	/workspace/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.3826930767	Mar 28 12:56:39 PM PDT 24	Mar 28 12:57:12 PM PDT 24	91998557192 ps
T305	/workspace/coverage/default/13.sysrst_ctrl_ec_pwr_on_rst.1786592248	Mar 28 12:55:23 PM PDT 24	Mar 28 12:55:28 PM PDT 24	2600122059 ps
T306	/workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.135196494	Mar 28 12:56:16 PM PDT 24	Mar 28 12:56:18 PM PDT 24	2638233472 ps
T307	/workspace/coverage/default/44.sysrst_ctrl_pin_override_test.89311201	Mar 28 12:56:15 PM PDT 24	Mar 28 12:56:21 PM PDT 24	2513744312 ps
T308	/workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.3218369252	Mar 28 12:56:40 PM PDT 24	Mar 28 12:56:42 PM PDT 24	2692741917 ps
T309	/workspace/coverage/default/30.sysrst_ctrl_pin_override_test.1707228781	Mar 28 12:56:06 PM PDT 24	Mar 28 12:56:07 PM PDT 24	2601097753 ps
T310	/workspace/coverage/default/31.sysrst_ctrl_alert_test.2276262231	Mar 28 12:56:04 PM PDT 24	Mar 28 12:56:09 PM PDT 24	2013030676 ps
T311	/workspace/coverage/default/29.sysrst_ctrl_in_out_inverted.3606442178	Mar 28 12:56:00 PM PDT 24	Mar 28 12:56:08 PM PDT 24	2468137074 ps
T312	/workspace/coverage/default/3.sysrst_ctrl_alert_test.1253331524	Mar 28 12:55:01 PM PDT 24	Mar 28 12:55:03 PM PDT 24	2025554879 ps
T313	/workspace/coverage/default/42.sysrst_ctrl_combo_detect.1302975943	Mar 28 12:56:31 PM PDT 24	Mar 28 12:58:26 PM PDT 24	93976599070 ps
T92	/workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.1945451491	Mar 28 12:57:08 PM PDT 24	Mar 28 12:57:25 PM PDT 24	25862175417 ps
T71	/workspace/coverage/default/11.sysrst_ctrl_ultra_low_pwr.868453119	Mar 28 12:55:05 PM PDT 24	Mar 28 12:55:14 PM PDT 24	6130786660 ps
T413	/workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst.3487157853	Mar 28 12:54:48 PM PDT 24	Mar 28 12:54:56 PM PDT 24	2424704002 ps
T185	/workspace/coverage/default/11.sysrst_ctrl_stress_all_with_rand_reset.4048052011	Mar 28 12:55:07 PM PDT 24	Mar 28 12:56:07 PM PDT 24	29549157368 ps
T72	/workspace/coverage/default/39.sysrst_ctrl_ultra_low_pwr.3204577957	Mar 28 12:56:01 PM PDT 24	Mar 28 12:56:20 PM PDT 24	149549654238 ps
T414	/workspace/coverage/default/17.sysrst_ctrl_pin_override_test.211677152	Mar 28 12:55:14 PM PDT 24	Mar 28 12:55:18 PM PDT 24	2522063860 ps
T415	/workspace/coverage/default/19.sysrst_ctrl_ec_pwr_on_rst.30686301	Mar 28 12:55:38 PM PDT 24	Mar 28 12:55:41 PM PDT 24	3210730941 ps
T416	/workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.1543105111	Mar 28 12:55:03 PM PDT 24	Mar 28 12:55:11 PM PDT 24	2443472800 ps
T417	/workspace/coverage/default/39.sysrst_ctrl_pin_access_test.3427346648	Mar 28 12:56:06 PM PDT 24	Mar 28 12:56:12 PM PDT 24	2116065402 ps
T418	/workspace/coverage/default/13.sysrst_ctrl_pin_access_test.2385681506	Mar 28 12:55:15 PM PDT 24	Mar 28 12:55:19 PM PDT 24	2143744272 ps
T361	/workspace/coverage/default/40.sysrst_ctrl_stress_all.1645156885	Mar 28 12:56:31 PM PDT 24	Mar 28 12:58:40 PM PDT 24	93751809508 ps
T419	/workspace/coverage/default/29.sysrst_ctrl_smoke.3462752126	Mar 28 12:55:54 PM PDT 24	Mar 28 12:55:56 PM PDT 24	2133143676 ps
T323	/workspace/coverage/default/11.sysrst_ctrl_pin_override_test.3249329469	Mar 28 12:55:06 PM PDT 24	Mar 28 12:55:08 PM PDT 24	2528820700 ps
T420	/workspace/coverage/default/39.sysrst_ctrl_pin_override_test.1833801801	Mar 28 12:56:11 PM PDT 24	Mar 28 12:56:19 PM PDT 24	2509425981 ps
T421	/workspace/coverage/default/24.sysrst_ctrl_pin_access_test.2408032914	Mar 28 12:55:51 PM PDT 24	Mar 28 12:55:55 PM PDT 24	2036784163 ps
T317	/workspace/coverage/default/43.sysrst_ctrl_stress_all.792206426	Mar 28 12:56:16 PM PDT 24	Mar 28 12:56:25 PM PDT 24	13501648708 ps
T422	/workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.138354002	Mar 28 12:55:05 PM PDT 24	Mar 28 12:55:08 PM PDT 24	3726182961 ps
T423	/workspace/coverage/default/15.sysrst_ctrl_smoke.1719427845	Mar 28 12:55:20 PM PDT 24	Mar 28 12:55:22 PM PDT 24	2138430858 ps
T125	/workspace/coverage/default/16.sysrst_ctrl_auto_blk_key_output.740378741	Mar 28 12:55:21 PM PDT 24	Mar 28 12:55:29 PM PDT 24	3031307402 ps
T73	/workspace/coverage/default/35.sysrst_ctrl_ultra_low_pwr.3417177615	Mar 28 12:56:04 PM PDT 24	Mar 28 12:56:12 PM PDT 24	6036978084 ps
T129	/workspace/coverage/default/16.sysrst_ctrl_alert_test.741670575	Mar 28 12:55:28 PM PDT 24	Mar 28 12:55:34 PM PDT 24	2015261195 ps
T130	/workspace/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.439400752	Mar 28 12:57:06 PM PDT 24	Mar 28 12:57:51 PM PDT 24	191882093990 ps
T131	/workspace/coverage/default/14.sysrst_ctrl_alert_test.2798385709	Mar 28 12:55:15 PM PDT 24	Mar 28 12:55:21 PM PDT 24	2012285689 ps
T132	/workspace/coverage/default/45.sysrst_ctrl_combo_detect.2457188150	Mar 28 12:56:39 PM PDT 24	Mar 28 12:57:39 PM PDT 24	103874154077 ps
T133	/workspace/coverage/default/45.sysrst_ctrl_edge_detect.3101349655	Mar 28 12:56:40 PM PDT 24	Mar 28 12:56:44 PM PDT 24	3124675364 ps
T134	/workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.140192423	Mar 28 12:57:05 PM PDT 24	Mar 28 01:00:21 PM PDT 24	73646315068 ps
T135	/workspace/coverage/default/17.sysrst_ctrl_edge_detect.1162415178	Mar 28 12:55:15 PM PDT 24	Mar 28 12:55:20 PM PDT 24	3072458619 ps
T136	/workspace/coverage/default/3.sysrst_ctrl_edge_detect.1388484214	Mar 28 12:55:01 PM PDT 24	Mar 28 12:55:09 PM PDT 24	4231945401 ps
T119	/workspace/coverage/default/42.sysrst_ctrl_auto_blk_key_output.3258242609	Mar 28 12:56:23 PM PDT 24	Mar 28 12:56:31 PM PDT 24	3098243381 ps
T93	/workspace/coverage/default/23.sysrst_ctrl_combo_detect_with_pre_cond.1404334802	Mar 28 12:55:51 PM PDT 24	Mar 28 12:56:26 PM PDT 24	25585882663 ps
T74	/workspace/coverage/default/13.sysrst_ctrl_ultra_low_pwr.398527863	Mar 28 12:55:13 PM PDT 24	Mar 28 12:55:20 PM PDT 24	3808333953 ps
T424	/workspace/coverage/default/0.sysrst_ctrl_in_out_inverted.1702211139	Mar 28 12:54:49 PM PDT 24	Mar 28 12:54:53 PM PDT 24	2448486727 ps
T425	/workspace/coverage/default/15.sysrst_ctrl_alert_test.3103764318	Mar 28 12:55:15 PM PDT 24	Mar 28 12:55:17 PM PDT 24	2047427657 ps
T290	/workspace/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.794293600	Mar 28 12:55:09 PM PDT 24	Mar 28 12:56:04 PM PDT 24	21170810142 ps
T150	/workspace/coverage/default/4.sysrst_ctrl_edge_detect.2411717114	Mar 28 12:55:04 PM PDT 24	Mar 28 12:55:07 PM PDT 24	3393347431 ps
T166	/workspace/coverage/default/2.sysrst_ctrl_stress_all.3136547391	Mar 28 12:54:52 PM PDT 24	Mar 28 12:54:56 PM PDT 24	13651503279 ps
T300	/workspace/coverage/default/0.sysrst_ctrl_pin_access_test.4022481203	Mar 28 12:54:49 PM PDT 24	Mar 28 12:54:55 PM PDT 24	2137281773 ps
T75	/workspace/coverage/default/24.sysrst_ctrl_ultra_low_pwr.2653992307	Mar 28 12:55:55 PM PDT 24	Mar 28 12:56:02 PM PDT 24	3150246510 ps
T301	/workspace/coverage/default/24.sysrst_ctrl_smoke.3294259254	Mar 28 12:55:52 PM PDT 24	Mar 28 12:55:54 PM PDT 24	2146849800 ps
T294	/workspace/coverage/default/25.sysrst_ctrl_auto_blk_key_output.3525046757	Mar 28 12:55:51 PM PDT 24	Mar 28 12:55:54 PM PDT 24	3336434343 ps
T302	/workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.3112596678	Mar 28 12:55:04 PM PDT 24	Mar 28 12:55:07 PM PDT 24	2628277334 ps
T303	/workspace/coverage/default/13.sysrst_ctrl_smoke.2388476292	Mar 28 12:55:24 PM PDT 24	Mar 28 12:55:31 PM PDT 24	2114408647 ps
T304	/workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.2287132940	Mar 28 12:56:15 PM PDT 24	Mar 28 12:56:21 PM PDT 24	3818493520 ps
T291	/workspace/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.3623749973	Mar 28 12:56:17 PM PDT 24	Mar 28 12:57:35 PM PDT 24	36063214410 ps
T292	/workspace/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.3216238339	Mar 28 12:55:53 PM PDT 24	Mar 28 12:56:41 PM PDT 24	34277941608 ps
T265	/workspace/coverage/default/11.sysrst_ctrl_combo_detect.3428277902	Mar 28 12:55:08 PM PDT 24	Mar 28 12:58:20 PM PDT 24	74582331076 ps
T426	/workspace/coverage/default/32.sysrst_ctrl_smoke.3817729674	Mar 28 12:56:01 PM PDT 24	Mar 28 12:56:07 PM PDT 24	2111257737 ps
T427	/workspace/coverage/default/10.sysrst_ctrl_smoke.1221073644	Mar 28 12:55:06 PM PDT 24	Mar 28 12:55:12 PM PDT 24	2114521391 ps
T428	/workspace/coverage/default/32.sysrst_ctrl_pin_access_test.1501022897	Mar 28 12:56:07 PM PDT 24	Mar 28 12:56:10 PM PDT 24	2168989909 ps
T362	/workspace/coverage/default/9.sysrst_ctrl_stress_all.32412320	Mar 28 12:55:06 PM PDT 24	Mar 28 12:56:58 PM PDT 24	45878743593 ps
T121	/workspace/coverage/default/33.sysrst_ctrl_ultra_low_pwr.1929083104	Mar 28 12:56:03 PM PDT 24	Mar 28 12:56:05 PM PDT 24	4802355748 ps
T318	/workspace/coverage/default/37.sysrst_ctrl_in_out_inverted.2095323863	Mar 28 12:56:04 PM PDT 24	Mar 28 12:56:06 PM PDT 24	2485150304 ps
T429	/workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.2084838823	Mar 28 12:55:08 PM PDT 24	Mar 28 12:55:12 PM PDT 24	2184930251 ps
T84	/workspace/coverage/default/30.sysrst_ctrl_ultra_low_pwr.2885578214	Mar 28 12:56:03 PM PDT 24	Mar 28 12:56:05 PM PDT 24	5694700058 ps
T85	/workspace/coverage/default/27.sysrst_ctrl_stress_all.1607587774	Mar 28 12:55:55 PM PDT 24	Mar 28 12:56:10 PM PDT 24	13371270751 ps
T324	/workspace/coverage/default/13.sysrst_ctrl_pin_override_test.4126822069	Mar 28 12:55:18 PM PDT 24	Mar 28 12:55:26 PM PDT 24	2508343786 ps
T430	/workspace/coverage/default/12.sysrst_ctrl_flash_wr_prot_out.3491858599	Mar 28 12:55:16 PM PDT 24	Mar 28 12:55:24 PM PDT 24	2610144156 ps
T293	/workspace/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.993719265	Mar 28 12:56:45 PM PDT 24	Mar 28 12:57:45 PM PDT 24	25258778593 ps
T255	/workspace/coverage/default/0.sysrst_ctrl_combo_detect.620407445	Mar 28 12:54:44 PM PDT 24	Mar 28 12:57:50 PM PDT 24	68745150906 ps
T94	/workspace/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.1287586138	Mar 28 12:56:06 PM PDT 24	Mar 28 12:57:54 PM PDT 24	261869845596 ps
T331	/workspace/coverage/default/9.sysrst_ctrl_alert_test.2295110801	Mar 28 12:55:10 PM PDT 24	Mar 28 12:55:12 PM PDT 24	2022842872 ps
T332	/workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1614369653	Mar 28 12:54:52 PM PDT 24	Mar 28 12:54:54 PM PDT 24	2538763246 ps
T333	/workspace/coverage/default/17.sysrst_ctrl_combo_detect_with_pre_cond.2033874500	Mar 28 12:55:14 PM PDT 24	Mar 28 12:56:10 PM PDT 24	83064175560 ps
T334	/workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.1658081352	Mar 28 12:56:17 PM PDT 24	Mar 28 12:56:23 PM PDT 24	2476976522 ps
T335	/workspace/coverage/default/8.sysrst_ctrl_pin_override_test.3096953294	Mar 28 12:55:05 PM PDT 24	Mar 28 12:55:07 PM PDT 24	2531796249 ps
T295	/workspace/coverage/default/2.sysrst_ctrl_auto_blk_key_output.2856799541	Mar 28 12:54:49 PM PDT 24	Mar 28 12:55:00 PM PDT 24	3651689646 ps
T336	/workspace/coverage/default/24.sysrst_ctrl_flash_wr_prot_out.187793807	Mar 28 12:55:53 PM PDT 24	Mar 28 12:55:55 PM PDT 24	2630197342 ps
T149	/workspace/coverage/default/8.sysrst_ctrl_stress_all.3472931769	Mar 28 12:55:14 PM PDT 24	Mar 28 12:55:25 PM PDT 24	8615313871 ps
T337	/workspace/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.3433585653	Mar 28 12:55:07 PM PDT 24	Mar 28 12:55:10 PM PDT 24	3238274210 ps
T183	/workspace/coverage/default/37.sysrst_ctrl_edge_detect.2477536145	Mar 28 12:56:10 PM PDT 24	Mar 28 12:56:15 PM PDT 24	5471783618 ps
T359	/workspace/coverage/default/30.sysrst_ctrl_combo_detect.2717262867	Mar 28 12:55:55 PM PDT 24	Mar 28 12:57:48 PM PDT 24	173111859436 ps
T431	/workspace/coverage/default/23.sysrst_ctrl_pin_access_test.1521450356	Mar 28 12:55:49 PM PDT 24	Mar 28 12:55:56 PM PDT 24	2254287349 ps
T95	/workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.1318870760	Mar 28 12:57:05 PM PDT 24	Mar 28 12:58:14 PM PDT 24	24578305758 ps
T96	/workspace/coverage/default/10.sysrst_ctrl_combo_detect.844453699	Mar 28 12:55:06 PM PDT 24	Mar 28 01:01:43 PM PDT 24	147635570185 ps
T432	/workspace/coverage/default/18.sysrst_ctrl_flash_wr_prot_out.1707824674	Mar 28 12:55:13 PM PDT 24	Mar 28 12:55:17 PM PDT 24	2618119642 ps
T433	/workspace/coverage/default/4.sysrst_ctrl_smoke.435623912	Mar 28 12:55:06 PM PDT 24	Mar 28 12:55:09 PM PDT 24	2133665980 ps
T434	/workspace/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.3299991744	Mar 28 12:56:05 PM PDT 24	Mar 28 12:56:12 PM PDT 24	2608784954 ps
T435	/workspace/coverage/default/45.sysrst_ctrl_ultra_low_pwr.72864877	Mar 28 12:56:38 PM PDT 24	Mar 28 12:56:40 PM PDT 24	5252938457 ps
T97	/workspace/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.3490056649	Mar 28 12:57:08 PM PDT 24	Mar 28 12:57:23 PM PDT 24	27368987508 ps
T436	/workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3039073430	Mar 28 12:55:04 PM PDT 24	Mar 28 12:55:07 PM PDT 24	2554968077 ps
T86	/workspace/coverage/default/34.sysrst_ctrl_stress_all.3946149419	Mar 28 12:56:08 PM PDT 24	Mar 28 12:56:15 PM PDT 24	17394387173 ps
T437	/workspace/coverage/default/35.sysrst_ctrl_pin_override_test.1638146280	Mar 28 12:56:07 PM PDT 24	Mar 28 12:56:09 PM PDT 24	2529865651 ps
T438	/workspace/coverage/default/10.sysrst_ctrl_stress_all.728824852	Mar 28 12:55:05 PM PDT 24	Mar 28 12:55:30 PM PDT 24	9640875544 ps
T439	/workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.2467592942	Mar 28 12:55:06 PM PDT 24	Mar 28 12:55:09 PM PDT 24	2626899064 ps
T440	/workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.4246769609	Mar 28 12:57:05 PM PDT 24	Mar 28 12:57:07 PM PDT 24	2490801151 ps
T441	/workspace/coverage/default/5.sysrst_ctrl_pin_override_test.3404576576	Mar 28 12:55:09 PM PDT 24	Mar 28 12:55:16 PM PDT 24	2510866777 ps
T442	/workspace/coverage/default/39.sysrst_ctrl_stress_all_with_rand_reset.2916818229	Mar 28 12:56:14 PM PDT 24	Mar 28 12:57:22 PM PDT 24	24954572984 ps
T98	/workspace/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.631779347	Mar 28 12:56:45 PM PDT 24	Mar 28 12:57:50 PM PDT 24	24582019703 ps
T122	/workspace/coverage/default/41.sysrst_ctrl_ultra_low_pwr.4149212335	Mar 28 12:56:31 PM PDT 24	Mar 28 12:56:34 PM PDT 24	7274203936 ps
T443	/workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.285589454	Mar 28 12:56:38 PM PDT 24	Mar 28 12:56:43 PM PDT 24	2617964401 ps
T444	/workspace/coverage/default/31.sysrst_ctrl_smoke.156893284	Mar 28 12:55:53 PM PDT 24	Mar 28 12:55:59 PM PDT 24	2107599433 ps
T99	/workspace/coverage/default/25.sysrst_ctrl_combo_detect_with_pre_cond.1008770896	Mar 28 12:55:49 PM PDT 24	Mar 28 12:56:06 PM PDT 24	22856979244 ps
T445	/workspace/coverage/default/49.sysrst_ctrl_stress_all.2859004070	Mar 28 12:57:05 PM PDT 24	Mar 28 12:57:24 PM PDT 24	9728153442 ps
T252	/workspace/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.190782675	Mar 28 12:57:05 PM PDT 24	Mar 28 12:58:40 PM PDT 24	37111528432 ps
T330	/workspace/coverage/default/0.sysrst_ctrl_stress_all_with_rand_reset.693717368	Mar 28 12:54:49 PM PDT 24	Mar 28 12:55:54 PM PDT 24	96163747177 ps
T446	/workspace/coverage/default/37.sysrst_ctrl_flash_wr_prot_out.1845678987	Mar 28 12:56:06 PM PDT 24	Mar 28 12:56:11 PM PDT 24	2619845131 ps
T151	/workspace/coverage/default/29.sysrst_ctrl_stress_all_with_rand_reset.4223452888	Mar 28 12:55:53 PM PDT 24	Mar 28 12:58:41 PM PDT 24	75780998703 ps
T256	/workspace/coverage/default/17.sysrst_ctrl_combo_detect.2821292880	Mar 28 12:55:29 PM PDT 24	Mar 28 12:56:52 PM PDT 24	31841637360 ps
T447	/workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.4212936734	Mar 28 12:56:43 PM PDT 24	Mar 28 12:56:45 PM PDT 24	2649107556 ps
T448	/workspace/coverage/default/11.sysrst_ctrl_ec_pwr_on_rst.515008087	Mar 28 12:55:06 PM PDT 24	Mar 28 12:55:12 PM PDT 24	3888579606 ps
T167	/workspace/coverage/default/31.sysrst_ctrl_stress_all_with_rand_reset.835982713	Mar 28 12:56:02 PM PDT 24	Mar 28 12:57:31 PM PDT 24	146471398212 ps
T449	/workspace/coverage/default/19.sysrst_ctrl_in_out_inverted.3621555061	Mar 28 12:55:34 PM PDT 24	Mar 28 12:55:39 PM PDT 24	2482728660 ps
T393	/workspace/coverage/default/19.sysrst_ctrl_combo_detect.1153592981	Mar 28 12:55:31 PM PDT 24	Mar 28 12:56:22 PM PDT 24	136662184057 ps
T244	/workspace/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.1637967024	Mar 28 12:57:07 PM PDT 24	Mar 28 12:57:26 PM PDT 24	29353797437 ps
T450	/workspace/coverage/default/6.sysrst_ctrl_pin_access_test.877026690	Mar 28 12:55:04 PM PDT 24	Mar 28 12:55:08 PM PDT 24	2181625895 ps
T451	/workspace/coverage/default/1.sysrst_ctrl_alert_test.506052827	Mar 28 12:54:53 PM PDT 24	Mar 28 12:54:56 PM PDT 24	2019841884 ps
T264	/workspace/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.880707164	Mar 28 12:56:10 PM PDT 24	Mar 28 12:59:54 PM PDT 24	84962480020 ps
T50	/workspace/coverage/default/1.sysrst_ctrl_feature_disable.33422560	Mar 28 12:54:52 PM PDT 24	Mar 28 12:56:16 PM PDT 24	32305445234 ps
T452	/workspace/coverage/default/38.sysrst_ctrl_flash_wr_prot_out.577598283	Mar 28 12:56:07 PM PDT 24	Mar 28 12:56:11 PM PDT 24	2620717024 ps
T453	/workspace/coverage/default/20.sysrst_ctrl_stress_all.3870041540	Mar 28 12:55:49 PM PDT 24	Mar 28 12:56:03 PM PDT 24	9737297705 ps
T395	/workspace/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.2867972135	Mar 28 12:57:08 PM PDT 24	Mar 28 01:03:15 PM PDT 24	140886540032 ps
T454	/workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.3639373003	Mar 28 12:56:17 PM PDT 24	Mar 28 12:56:25 PM PDT 24	2610281176 ps
T455	/workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst.397761906	Mar 28 12:54:52 PM PDT 24	Mar 28 12:55:00 PM PDT 24	2393584027 ps
T456	/workspace/coverage/default/13.sysrst_ctrl_in_out_inverted.346867914	Mar 28 12:55:17 PM PDT 24	Mar 28 12:55:25 PM PDT 24	2468726164 ps
T82	/workspace/coverage/default/1.sysrst_ctrl_edge_detect.4188150211	Mar 28 12:54:51 PM PDT 24	Mar 28 12:54:56 PM PDT 24	6273643920 ps
T457	/workspace/coverage/default/21.sysrst_ctrl_smoke.1315612390	Mar 28 12:55:51 PM PDT 24	Mar 28 12:55:53 PM PDT 24	2164939784 ps
T458	/workspace/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.3936702653	Mar 28 12:57:09 PM PDT 24	Mar 28 12:57:26 PM PDT 24	25358959702 ps
T459	/workspace/coverage/default/44.sysrst_ctrl_pin_access_test.2549706312	Mar 28 12:56:24 PM PDT 24	Mar 28 12:56:30 PM PDT 24	2159261296 ps
T460	/workspace/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.2654373933	Mar 28 12:57:05 PM PDT 24	Mar 28 12:58:20 PM PDT 24	26332581865 ps
T461	/workspace/coverage/default/19.sysrst_ctrl_pin_access_test.1387740341	Mar 28 12:55:33 PM PDT 24	Mar 28 12:55:40 PM PDT 24	2050206390 ps
T391	/workspace/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.2777284079	Mar 28 12:57:05 PM PDT 24	Mar 28 12:59:16 PM PDT 24	51436385955 ps
T243	/workspace/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.2792174237	Mar 28 12:57:04 PM PDT 24	Mar 28 12:58:23 PM PDT 24	32476363298 ps
T462	/workspace/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.3089128701	Mar 28 12:57:09 PM PDT 24	Mar 28 12:57:47 PM PDT 24	26838214881 ps
T463	/workspace/coverage/default/49.sysrst_ctrl_pin_access_test.12039611	Mar 28 12:57:05 PM PDT 24	Mar 28 12:57:07 PM PDT 24	2266187113 ps
T319	/workspace/coverage/default/30.sysrst_ctrl_in_out_inverted.2814504696	Mar 28 12:55:50 PM PDT 24	Mar 28 12:55:54 PM PDT 24	2466268675 ps
T464	/workspace/coverage/default/16.sysrst_ctrl_pin_access_test.4133701557	Mar 28 12:55:14 PM PDT 24	Mar 28 12:55:16 PM PDT 24	2276767903 ps
T465	/workspace/coverage/default/34.sysrst_ctrl_auto_blk_key_output.2453343730	Mar 28 12:56:02 PM PDT 24	Mar 28 12:56:12 PM PDT 24	3647064353 ps
T466	/workspace/coverage/default/8.sysrst_ctrl_alert_test.532840458	Mar 28 12:55:09 PM PDT 24	Mar 28 12:55:15 PM PDT 24	2011704179 ps
T177	/workspace/coverage/default/32.sysrst_ctrl_edge_detect.4150565664	Mar 28 12:56:02 PM PDT 24	Mar 28 12:56:05 PM PDT 24	5458889762 ps