Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1045

1

T1

9

T66

9

T320

7

auto[1]

1095

1

T1

11

T66

11

T320

13

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

520

1

T1

6

T66

5

T320

4

from_0to1

523

1

T1

5

T66

6

T320

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

986

1

T1

8

T66

11

T320

6

auto[1]

1154

1

T1

12

T66

9

T320

14

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1080

1

T1

12

T66

11

T320

7

auto[1]

1060

1

T1

8

T66

9

T320

13

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

63

1

T66

2

T320

1

T55

1

auto[0]

from_1to0

auto[0]

auto[1]

70

1

T66

2

T320

1

T55

2

auto[0]

from_1to0

auto[1]

auto[0]

61

1

T1

1

T55

1

T321

1

auto[0]

from_1to0

auto[1]

auto[1]

59

1

T55

2

T328

3

T329

1

auto[0]

from_0to1

auto[0]

auto[0]

68

1

T1

1

T66

1

T55

2

auto[0]

from_0to1

auto[0]

auto[1]

57

1

T1

1

T55

1

T321

1

auto[0]

from_0to1

auto[1]

auto[0]

69

1

T1

2

T320

1

T55

2

auto[0]

from_0to1

auto[1]

auto[1]

72

1

T66

1

T320

1

T55

1

auto[1]

from_1to0

auto[0]

auto[0]

66

1

T1

2

T320

1

T329

2

auto[1]

from_1to0

auto[0]

auto[1]

57

1

T1

1

T321

1

T322

1

auto[1]

from_1to0

auto[1]

auto[0]

78

1

T1

1

T66

1

T55

2

auto[1]

from_1to0

auto[1]

auto[1]

66

1

T1

1

T320

1

T55

2

auto[1]

from_0to1

auto[0]

auto[0]

50

1

T66

2

T55

1

T329

1

auto[1]

from_0to1

auto[0]

auto[1]

70

1

T66

1

T320

1

T55

2

auto[1]

from_0to1

auto[1]

auto[0]

66

1

T66

1

T320

1

T328

1

auto[1]

from_0to1

auto[1]

auto[1]

71

1

T1

1

T320

1

T328

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1052

1

T1

10

T66

13

T320

8

auto[1]

1088

1

T1

10

T66

7

T320

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

511

1

T1

7

T66

5

T320

4

from_0to1

518

1

T1

6

T66

5

T320

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1087

1

T1

8

T66

10

T320

9

auto[1]

1053

1

T1

12

T66

10

T320

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1064

1

T1

10

T66

8

T320

7

auto[1]

1076

1

T1

10

T66

12

T320

13

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

59

1

T55

2

T328

1

T329

3

auto[0]

from_1to0

auto[0]

auto[1]

73

1

T1

1

T66

3

T320

1

auto[0]

from_1to0

auto[1]

auto[0]

58

1

T1

1

T66

1

T320

2

auto[0]

from_1to0

auto[1]

auto[1]

65

1

T1

1

T66

1

T55

1

auto[0]

from_0to1

auto[0]

auto[0]

66

1

T66

2

T55

2

T329

1

auto[0]

from_0to1

auto[0]

auto[1]

62

1

T1

3

T66

1

T320

1

auto[0]

from_0to1

auto[1]

auto[0]

48

1

T66

1

T328

1

T321

2

auto[0]

from_0to1

auto[1]

auto[1]

60

1

T1

1

T320

1

T55

1

auto[1]

from_1to0

auto[0]

auto[0]

65

1

T1

1

T55

1

T328

1

auto[1]

from_1to0

auto[0]

auto[1]

61

1

T1

1

T63

1

T57

1

auto[1]

from_1to0

auto[1]

auto[0]

64

1

T1

2

T320

1

T329

1

auto[1]

from_1to0

auto[1]

auto[1]

66

1

T55

1

T329

2

T321

1

auto[1]

from_0to1

auto[0]

auto[0]

73

1

T55

1

T328

1

T321

1

auto[1]

from_0to1

auto[0]

auto[1]

70

1

T1

1

T320

1

T55

1

auto[1]

from_0to1

auto[1]

auto[0]

71

1

T55

3

T329

1

T57

3

auto[1]

from_0to1

auto[1]

auto[1]

68

1

T1

1

T66

1

T320

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1097

1

T1

8

T66

17

T320

9

auto[1]

1043

1

T1

12

T66

3

T320

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

513

1

T1

6

T66

4

T320

7

from_0to1

509

1

T1

6

T66

3

T320

7

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1057

1

T1

11

T66

9

T320

10

auto[1]

1083

1

T1

9

T66

11

T320

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1086

1

T1

10

T66

8

T320

7

auto[1]

1054

1

T1

10

T66

12

T320

13

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

59

1

T1

1

T320

1

T329

1

auto[0]

from_1to0

auto[0]

auto[1]

54

1

T66

1

T320

1

T55

2

auto[0]

from_1to0

auto[1]

auto[0]

73

1

T1

1

T66

2

T55

3

auto[0]

from_1to0

auto[1]

auto[1]

63

1

T66

1

T320

1

T55

2

auto[0]

from_0to1

auto[0]

auto[0]

71

1

T66

2

T55

2

T63

2

auto[0]

from_0to1

auto[0]

auto[1]

65

1

T66

1

T320

1

T328

2

auto[0]

from_0to1

auto[1]

auto[0]

79

1

T320

1

T55

4

T329

1

auto[0]

from_0to1

auto[1]

auto[1]

52

1

T1

1

T320

1

T55

1

auto[1]

from_1to0

auto[0]

auto[0]

63

1

T1

2

T329

1

T322

1

auto[1]

from_1to0

auto[0]

auto[1]

77

1

T1

1

T320

2

T55

2

auto[1]

from_1to0

auto[1]

auto[0]

69

1

T1

1

T55

1

T328

1

auto[1]

from_1to0

auto[1]

auto[1]

55

1

T320

2

T55

2

T63

1

auto[1]

from_0to1

auto[0]

auto[0]

61

1

T320

1

T55

2

T328

2

auto[1]

from_0to1

auto[0]

auto[1]

58

1

T1

2

T55

1

T321

1

auto[1]

from_0to1

auto[1]

auto[0]

68

1

T1

2

T320

1

T55

1

auto[1]

from_0to1

auto[1]

auto[1]

55

1

T1

1

T320

2

T329

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1060

1

T1

11

T66

9

T320

12

auto[1]

1080

1

T1

9

T66

11

T320

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

498

1

T1

4

T66

4

T320

4

from_0to1

491

1

T1

5

T66

3

T320

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1056

1

T1

8

T66

8

T320

8

auto[1]

1084

1

T1

12

T66

12

T320

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1121

1

T1

7

T66

10

T320

11

auto[1]

1019

1

T1

13

T66

10

T320

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

62

1

T1

1

T55

1

T329

1

auto[0]

from_1to0

auto[0]

auto[1]

61

1

T320

1

T55

3

T322

1

auto[0]

from_1to0

auto[1]

auto[0]

66

1

T66

1

T320

1

T55

2

auto[0]

from_1to0

auto[1]

auto[1]

57

1

T1

2

T66

1

T320

1

auto[0]

from_0to1

auto[0]

auto[0]

56

1

T320

1

T55

1

T328

1

auto[0]

from_0to1

auto[0]

auto[1]

50

1

T1

1

T55

1

T328

1

auto[0]

from_0to1

auto[1]

auto[0]

60

1

T320

1

T55

1

T321

1

auto[0]

from_0to1

auto[1]

auto[1]

68

1

T1

2

T66

1

T55

2

auto[1]

from_1to0

auto[0]

auto[0]

61

1

T1

1

T55

1

T328

2

auto[1]

from_1to0

auto[0]

auto[1]

64

1

T320

1

T328

1

T321

1

auto[1]

from_1to0

auto[1]

auto[0]

71

1

T66

1

T55

2

T63

1

auto[1]

from_1to0

auto[1]

auto[1]

56

1

T66

1

T55

2

T328

1

auto[1]

from_0to1

auto[0]

auto[0]

69

1

T66

1

T55

3

T321

1

auto[1]

from_0to1

auto[0]

auto[1]

51

1

T66

1

T320

1

T55

1

auto[1]

from_0to1

auto[1]

auto[0]

80

1

T1

2

T320

1

T55

4

auto[1]

from_0to1

auto[1]

auto[1]

57

1

T328

1

T329

1

T321

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1028

1

T1

5

T66

11

T320

12

auto[1]

1112

1

T1

15

T66

9

T320

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

503

1

T1

4

T66

3

T320

5

from_0to1

500

1

T1

4

T66

3

T320

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1088

1

T1

12

T66

9

T320

10

auto[1]

1052

1

T1

8

T66

11

T320

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1058

1

T1

7

T66

12

T320

7

auto[1]

1082

1

T1

13

T66

8

T320

13

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

68

1

T55

4

T328

1

T321

1

auto[0]

from_1to0

auto[0]

auto[1]

57

1

T55

2

T329

1

T322

1

auto[0]

from_1to0

auto[1]

auto[0]

56

1

T320

1

T321

2

T322

1

auto[0]

from_1to0

auto[1]

auto[1]

62

1

T320

1

T57

3

T309

1

auto[0]

from_0to1

auto[0]

auto[0]

64

1

T66

1

T55

3

T63

2

auto[0]

from_0to1

auto[0]

auto[1]

70

1

T1

1

T320

1

T55

3

auto[0]

from_0to1

auto[1]

auto[0]

60

1

T66

1

T320

1

T328

2

auto[0]

from_0to1

auto[1]

auto[1]

48

1

T320

1

T55

1

T328

1

auto[1]

from_1to0

auto[0]

auto[0]

58

1

T1

1

T329

1

T63

2

auto[1]

from_1to0

auto[0]

auto[1]

59

1

T320

1

T55

1

T328

2

auto[1]

from_1to0

auto[1]

auto[0]

73

1

T66

2

T320

1

T55

1

auto[1]

from_1to0

auto[1]

auto[1]

70

1

T1

3

T66

1

T320

1

auto[1]

from_0to1

auto[0]

auto[0]

75

1

T1

2

T320

1

T55

1

auto[1]

from_0to1

auto[0]

auto[1]

58

1

T1

1

T320

1

T55

1

auto[1]

from_0to1

auto[1]

auto[0]

61

1

T328

1

T57

1

T323

1

auto[1]

from_0to1

auto[1]

auto[1]

64

1

T66

1

T320

1

T321

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1015

1

T1

11

T66

9

T320

11

auto[1]

1125

1

T1

9

T66

11

T320

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

518

1

T1

6

T66

5

T320

5

from_0to1

515

1

T1

5

T66

4

T320

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1075

1

T1

11

T66

14

T320

11

auto[1]

1065

1

T1

9

T66

6

T320

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1055

1

T1

14

T66

11

T320

12

auto[1]

1085

1

T1

6

T66

9

T320

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

72

1

T66

1

T55

3

T328

2

auto[0]

from_1to0

auto[0]

auto[1]

68

1

T1

1

T320

1

T328

1

auto[0]

from_1to0

auto[1]

auto[0]

55

1

T1

1

T55

1

T328

1

auto[0]

from_1to0

auto[1]

auto[1]

66

1

T1

1

T55

1

T329

2

auto[0]

from_0to1

auto[0]

auto[0]

66

1

T1

2

T66

1

T55

1

auto[0]

from_0to1

auto[0]

auto[1]

57

1

T328

1

T321

1

T322

1

auto[0]

from_0to1

auto[1]

auto[0]

63

1

T321

1

T322

1

T63

1

auto[0]

from_0to1

auto[1]

auto[1]

63

1

T66

1

T320

1

T55

3

auto[1]

from_1to0

auto[0]

auto[0]

62

1

T1

1

T320

1

T55

1

auto[1]

from_1to0

auto[0]

auto[1]

70

1

T1

1

T66

4

T320

1

auto[1]

from_1to0

auto[1]

auto[0]

51

1

T320

2

T328

1

T57

1

auto[1]

from_1to0

auto[1]

auto[1]

74

1

T1

1

T55

2

T321

2

auto[1]

from_0to1

auto[0]

auto[0]

76

1

T320

1

T55

1

T328

1

auto[1]

from_0to1

auto[0]

auto[1]

60

1

T320

1

T55

2

T328

1

auto[1]

from_0to1

auto[1]

auto[0]

61

1

T1

3

T66

2

T320

1

auto[1]

from_0to1

auto[1]

auto[1]

69

1

T320

1

T55

3

T328

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1068

1

T1

9

T66

12

T320

11

auto[1]

1072

1

T1

11

T66

8

T320

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

501

1

T1

4

T66

4

T320

5

from_0to1

509

1

T1

4

T66

3

T320

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1094

1

T1

9

T66

12

T320

13

auto[1]

1046

1

T1

11

T66

8

T320

7

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1089

1

T1

9

T66

8

T320

14

auto[1]

1051

1

T1

11

T66

12

T320

6

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

74

1

T1

1

T66

1

T55

3

auto[0]

from_1to0

auto[0]

auto[1]

58

1

T321

2

T322

1

T57

4

auto[0]

from_1to0

auto[1]

auto[0]

66

1

T1

1

T66

1

T320

3

auto[0]

from_1to0

auto[1]

auto[1]

56

1

T66

1

T320

1

T328

1

auto[0]

from_0to1

auto[0]

auto[0]

65

1

T66

1

T328

1

T322

1

auto[0]

from_0to1

auto[0]

auto[1]

71

1

T320

1

T328

1

T321

1

auto[0]

from_0to1

auto[1]

auto[0]

62

1

T55

1

T328

1

T321

1

auto[0]

from_0to1

auto[1]

auto[1]

60

1

T55

1

T321

1

T57

1

auto[1]

from_1to0

auto[0]

auto[0]

68

1

T329

1

T321

1

T57

2

auto[1]

from_1to0

auto[0]

auto[1]

67

1

T1

1

T66

1

T320

1

auto[1]

from_1to0

auto[1]

auto[0]

62

1

T55

3

T322

2

T63

1

auto[1]

from_1to0

auto[1]

auto[1]

50

1

T1

1

T55

1

T328

2

auto[1]

from_0to1

auto[0]

auto[0]

69

1

T1

2

T66

1

T320

2

auto[1]

from_0to1

auto[0]

auto[1]

63

1

T320

1

T55

3

T328

1

auto[1]

from_0to1

auto[1]

auto[0]

59

1

T1

1

T66

1

T329

2

auto[1]

from_0to1

auto[1]

auto[1]

60

1

T1

1

T320

1

T55

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1085

1

T1

8

T66

8

T320

12

auto[1]

1055

1

T1

12

T66

12

T320

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

505

1

T1

4

T66

4

T320

3

from_0to1

496

1

T1

5

T66

3

T320

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1053

1

T1

11

T66

12

T320

10

auto[1]

1087

1

T1

9

T66

8

T320

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1078

1

T1

9

T66

9

T320

10

auto[1]

1062

1

T1

11

T66

11

T320

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

72

1

T1

2

T320

1

T328

2

auto[0]

from_1to0

auto[0]

auto[1]

63

1

T1

1

T55

1

T321

1

auto[0]

from_1to0

auto[1]

auto[0]

60

1

T66

1

T328

1

T321

1

auto[0]

from_1to0

auto[1]

auto[1]

55

1

T1

1

T66

1

T329

2

auto[0]

from_0to1

auto[0]

auto[0]

51

1

T320

1

T55

1

T328

1

auto[0]

from_0to1

auto[0]

auto[1]

61

1

T1

1

T66

1

T55

1

auto[0]

from_0to1

auto[1]

auto[0]

62

1

T55

2

T329

1

T321

1

auto[0]

from_0to1

auto[1]

auto[1]

70

1

T320

2

T55

1

T329

1

auto[1]

from_1to0

auto[0]

auto[0]

55

1

T55

2

T321

1

T322

2

auto[1]

from_1to0

auto[0]

auto[1]

68

1

T66

1

T55

1

T57

4

auto[1]

from_1to0

auto[1]

auto[0]

66

1

T66

1

T55

2

T329

1

auto[1]

from_1to0

auto[1]

auto[1]

66

1

T320

2

T55

2

T328

2

auto[1]

from_0to1

auto[0]

auto[0]

74

1

T328

1

T329

1

T321

1

auto[1]

from_0to1

auto[0]

auto[1]

53

1

T1

1

T66

1

T321

1

auto[1]

from_0to1

auto[1]

auto[0]

53

1

T1

1

T55

2

T328

2

auto[1]

from_0to1

auto[1]

auto[1]

72

1

T1

2

T66

1

T55

1