Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	156891	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

119222

1

T1

367

T2

8

T4

21

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	143279	1			T1	506		T2	11		T4	2
values[0x0]	65627	1			T1	142		T2	4		T4	28
values[0x1]	67207	1			T1	139		T2	3		T4	33

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	126693	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

149420

1

T1

428

T2

11

T4

30

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1163	1			T1	2		T12	2		T7	5
valid_sources[0x01]	908	1			T12	2		T23	1		T37	2
valid_sources[0x02]	1457	1			T1	1		T12	6		T15	1
valid_sources[0x03]	1213	1			T12	2		T3	1		T21	1
valid_sources[0x04]	1004	1			T1	5		T12	6		T3	1
valid_sources[0x05]	963	1			T1	2		T12	6		T58	1
valid_sources[0x06]	841	1			T1	9		T12	4		T3	2
valid_sources[0x07]	1333	1			T1	2		T12	3		T7	9
valid_sources[0x08]	985	1			T12	3		T16	8		T7	7
valid_sources[0x09]	844	1			T12	1		T7	1		T23	3
valid_sources[0x0a]	810	1			T1	7		T12	1		T7	6
valid_sources[0x0b]	909	1			T1	2		T12	2		T3	2
valid_sources[0x0c]	975	1			T1	4		T12	2		T23	1
valid_sources[0x0d]	1118	1			T1	7		T12	4		T7	7
valid_sources[0x0e]	1599	1			T1	1		T12	2		T13	1
valid_sources[0x0f]	745	1			T1	3		T12	1		T7	2
valid_sources[0x10]	820	1			T1	1		T12	1		T37	1
valid_sources[0x11]	972	1			T12	1		T23	1		T37	1
valid_sources[0x12]	1113	1			T1	5		T12	1		T7	4
valid_sources[0x13]	850	1			T1	2		T12	3		T7	3
valid_sources[0x14]	925	1			T12	3		T3	4		T7	5
valid_sources[0x15]	909	1			T1	1		T12	7		T7	5
valid_sources[0x16]	920	1			T1	10		T12	2		T3	1
valid_sources[0x17]	1170	1			T1	4		T12	4		T3	1
valid_sources[0x18]	845	1			T1	4		T12	2		T23	4
valid_sources[0x19]	1841	1			T1	3		T12	4		T3	2
valid_sources[0x1a]	1182	1			T1	3		T3	1		T48	1
valid_sources[0x1b]	987	1			T1	3		T12	2		T23	1
valid_sources[0x1c]	947	1			T1	4		T12	2		T7	1
valid_sources[0x1d]	845	1			T1	9		T12	1		T48	3
valid_sources[0x1e]	861	1			T1	3		T12	4		T7	1
valid_sources[0x1f]	819	1			T1	3		T12	5		T3	1
valid_sources[0x20]	933	1			T1	6		T12	5		T15	3
valid_sources[0x21]	907	1			T1	2		T12	4		T3	1
valid_sources[0x22]	958	1			T1	2		T12	2		T21	1
valid_sources[0x23]	1116	1			T1	1		T12	4		T3	2
valid_sources[0x24]	996	1			T1	2		T12	7		T21	2
valid_sources[0x25]	832	1			T12	6		T3	1		T16	1
valid_sources[0x26]	1491	1			T1	2		T12	6		T16	3
valid_sources[0x27]	1021	1			T1	7		T12	1		T3	1
valid_sources[0x28]	894	1			T12	7		T6	16		T7	2
valid_sources[0x29]	907	1			T12	3		T48	1		T37	8
valid_sources[0x2a]	1088	1			T1	4		T12	8		T7	2
valid_sources[0x2b]	1233	1			T1	5		T12	8		T15	3
valid_sources[0x2c]	1095	1			T1	9		T12	2		T21	1
valid_sources[0x2d]	1070	1			T1	7		T12	2		T3	1
valid_sources[0x2e]	1133	1			T1	6		T12	3		T3	1
valid_sources[0x2f]	851	1			T1	2		T12	4		T48	1
valid_sources[0x30]	1156	1			T1	1		T12	4		T7	28
valid_sources[0x31]	886	1			T1	2		T12	4		T3	1
valid_sources[0x32]	934	1			T12	4		T23	3		T37	5
valid_sources[0x33]	952	1			T12	6		T7	6		T23	1
valid_sources[0x34]	2061	1			T1	1		T12	1		T48	1
valid_sources[0x35]	1053	1			T12	2		T7	2		T23	1
valid_sources[0x36]	847	1			T1	3		T12	5		T48	4
valid_sources[0x37]	1015	1			T1	1		T12	3		T15	2
valid_sources[0x38]	1327	1			T1	2		T12	3		T14	9
valid_sources[0x39]	1005	1			T1	5		T12	6		T3	2
valid_sources[0x3a]	1080	1			T1	2		T12	1		T3	1
valid_sources[0x3b]	987	1			T1	2		T7	12		T23	1
valid_sources[0x3c]	865	1			T12	4		T7	4		T23	2
valid_sources[0x3d]	941	1			T1	5		T12	1		T7	2
valid_sources[0x3e]	849	1			T1	2		T12	4		T16	2
valid_sources[0x3f]	922	1			T1	11		T12	9		T21	1
valid_sources[0x40]	890	1			T1	9		T12	1		T49	1
valid_sources[0x41]	751	1			T1	1		T12	5		T37	3
valid_sources[0x42]	870	1			T1	1		T12	1		T3	2
valid_sources[0x43]	1009	1			T1	8		T12	1		T13	1
valid_sources[0x44]	825	1			T1	1		T12	5		T3	3
valid_sources[0x45]	1024	1			T1	2		T12	7		T21	1
valid_sources[0x46]	1360	1			T1	10		T12	1		T23	5
valid_sources[0x47]	932	1			T1	3		T12	9		T48	1
valid_sources[0x48]	1490	1			T1	7		T12	4		T3	1
valid_sources[0x49]	940	1			T1	1		T4	63		T12	5
valid_sources[0x4a]	888	1			T1	5		T12	8		T3	1
valid_sources[0x4b]	963	1			T1	2		T12	1		T15	3
valid_sources[0x4c]	1388	1			T12	4		T23	2		T37	3
valid_sources[0x4d]	900	1			T1	3		T12	4		T3	1
valid_sources[0x4e]	1368	1			T1	9		T12	3		T49	1
valid_sources[0x4f]	891	1			T1	7		T12	4		T3	1
valid_sources[0x50]	1129	1			T1	9		T12	9		T23	3
valid_sources[0x51]	802	1			T1	3		T12	5		T48	2
valid_sources[0x52]	1123	1			T1	1		T12	1		T3	1
valid_sources[0x53]	2219	1			T1	1		T12	4		T3	4
valid_sources[0x54]	990	1			T1	3		T12	2		T7	9
valid_sources[0x55]	907	1			T1	5		T12	7		T3	1
valid_sources[0x56]	1229	1			T1	13		T12	2		T37	6
valid_sources[0x57]	959	1			T1	4		T12	3		T15	1
valid_sources[0x58]	759	1			T1	3		T12	2		T7	4
valid_sources[0x59]	827	1			T1	3		T12	4		T48	1
valid_sources[0x5a]	941	1			T12	3		T3	3		T21	1
valid_sources[0x5b]	948	1			T12	3		T7	16		T23	1
valid_sources[0x5c]	785	1			T12	1		T7	7		T23	2
valid_sources[0x5d]	1386	1			T1	3		T12	2		T3	1
valid_sources[0x5e]	1377	1			T1	2		T12	3		T3	1
valid_sources[0x5f]	1044	1			T1	6		T12	5		T16	2
valid_sources[0x60]	1356	1			T1	1		T12	10		T48	1
valid_sources[0x61]	965	1			T12	7		T7	2		T23	1
valid_sources[0x62]	1039	1			T12	2		T7	1		T23	2
valid_sources[0x63]	898	1			T1	1		T12	3		T23	1
valid_sources[0x64]	1110	1			T12	8		T48	1		T37	7
valid_sources[0x65]	933	1			T1	3		T12	6		T21	1
valid_sources[0x66]	764	1			T1	6		T12	4		T7	1
valid_sources[0x67]	1014	1			T1	1		T12	2		T7	7
valid_sources[0x68]	1246	1			T1	1		T12	5		T48	1
valid_sources[0x69]	894	1			T1	4		T12	8		T7	3
valid_sources[0x6a]	870	1			T12	3		T7	6		T23	2
valid_sources[0x6b]	1169	1			T1	8		T12	2		T21	1
valid_sources[0x6c]	875	1			T12	2		T48	1		T7	4
valid_sources[0x6d]	1001	1			T1	3		T12	2		T21	2
valid_sources[0x6e]	950	1			T1	2		T12	4		T21	1
valid_sources[0x6f]	1366	1			T1	5		T12	6		T23	1
valid_sources[0x70]	1037	1			T1	4		T12	4		T48	1
valid_sources[0x71]	982	1			T12	4		T7	18		T23	1
valid_sources[0x72]	927	1			T1	2		T12	3		T21	1
valid_sources[0x73]	1301	1			T1	7		T12	6		T48	1
valid_sources[0x74]	984	1			T1	4		T12	1		T7	1
valid_sources[0x75]	994	1			T12	4		T7	4		T23	2
valid_sources[0x76]	1287	1			T1	3		T12	8		T23	1
valid_sources[0x77]	823	1			T1	7		T12	4		T3	2
valid_sources[0x78]	805	1			T12	4		T48	1		T7	2
valid_sources[0x79]	895	1			T1	9		T12	2		T23	1
valid_sources[0x7a]	830	1			T1	3		T12	3		T16	1
valid_sources[0x7b]	1218	1			T1	1		T12	1		T23	1
valid_sources[0x7c]	774	1			T12	4		T7	2		T35	1
valid_sources[0x7d]	1139	1			T1	1		T12	6		T23	1
valid_sources[0x7e]	933	1			T1	3		T12	1		T3	1
valid_sources[0x7f]	1748	1			T12	5		T3	1		T5	962
valid_sources[0x80]	1662	1			T1	2		T23	3		T37	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

64146

1

T1

264

T2

6

T4

1

values[0x0]

all_enables

biggest_size

32065

1

T1

67

T2

1

T4

14

values[0x1]

all_enables

biggest_size

23011

1

T1

36

T2

1

T4

6