Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T3,T22

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T1,T3,T22

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T3,T22

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T22
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T3,T22

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T22
0	1	Covered	T80,T107
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T22
0	1	Covered	T1,T3,T22
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T3,T22
1	-	Covered	T1,T3,T22

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T3,T22
DetectSt	168	Covered	T1,T3,T22
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T1,T3,T22

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T3,T22
DebounceSt->IdleSt	163	Covered	T1,T47,T125
DetectSt->IdleSt	186	Covered	T80,T107
DetectSt->StableSt	191	Covered	T1,T3,T22
IdleSt->DebounceSt	148	Covered	T1,T3,T22
StableSt->IdleSt	206	Covered	T1,T3,T22

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T3,T22
0	1	Covered	T1,T3,T22
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T22
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T3,T22
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T50,T77
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T3,T22
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T47,T125
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T3,T22
DetectSt	-	-	-	-	1	-	-	Covered	T80,T107
DetectSt	-	-	-	-	0	1	-	Covered	T1,T3,T22
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T3,T22
StableSt	-	-	-	-	-	-	0	Covered	T1,T3,T22
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6431240	282	0	0
CntIncr_A	6431240	197887	0	0
CntNoWrap_A	6431240	5736190	0	0
DetectStDropOut_A	6431240	2	0	0
DetectedOut_A	6431240	875	0	0
DetectedPulseOut_A	6431240	124	0	0
DisabledIdleSt_A	6431240	5531883	0	0
DisabledNoDetection_A	6431240	5534306	0	0
EnterDebounceSt_A	6431240	160	0	0
EnterDetectSt_A	6431240	126	0	0
EnterStableSt_A	6431240	124	0	0
PulseIsPulse_A	6431240	124	0	0
StayInStableSt	6431240	751	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6431240	7002	0	0
gen_low_level_sva.LowLevelEvent_A	6431240	5738952	0	0
gen_not_sticky_sva.StableStDropOut_A	6431240	124	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	282	0	0
T1	353536	14	0	0
T2	599	0	0	0
T3	3608	2	0	0
T4	522	0	0	0
T5	18447	0	0	0
T12	15235	0	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T22	0	4	0	0
T39	0	4	0	0
T40	0	4	0	0
T41	0	2	0	0
T43	0	4	0	0
T45	0	2	0	0
T46	0	2	0	0
T47	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	197887	0	0
T1	353536	488	0	0
T2	599	0	0	0
T3	3608	23	0	0
T4	522	0	0	0
T5	18447	0	0	0
T12	15235	0	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T22	0	77	0	0
T39	0	102	0	0
T40	0	50048	0	0
T41	0	65	0	0
T43	0	38912	0	0
T45	0	88	0	0
T46	0	96	0	0
T47	0	84	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5736190	0	0
T1	353536	346561	0	0
T2	599	198	0	0
T3	3608	1602	0	0
T4	522	121	0	0
T5	18447	18015	0	0
T12	15235	14795	0	0
T13	421	20	0	0
T14	403	2	0	0
T15	494	93	0	0
T16	494	93	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	2	0	0
T80	47450	1	0	0
T107	0	1	0	0
T109	659	0	0	0
T110	6655	0	0	0
T111	13740	0	0	0
T112	641	0	0	0
T113	873	0	0	0
T114	736	0	0	0
T115	421	0	0	0
T116	522	0	0	0
T117	11604	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	875	0	0
T1	353536	43	0	0
T2	599	0	0	0
T3	3608	7	0	0
T4	522	0	0	0
T5	18447	0	0	0
T12	15235	0	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T22	0	19	0	0
T39	0	17	0	0
T40	0	11	0	0
T41	0	10	0	0
T43	0	7	0	0
T45	0	3	0	0
T46	0	12	0	0
T119	0	10	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	124	0	0
T1	353536	6	0	0
T2	599	0	0	0
T3	3608	1	0	0
T4	522	0	0	0
T5	18447	0	0	0
T12	15235	0	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T22	0	2	0	0
T39	0	2	0	0
T40	0	2	0	0
T41	0	1	0	0
T43	0	2	0	0
T45	0	1	0	0
T46	0	1	0	0
T119	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5531883	0	0
T1	353536	345767	0	0
T2	599	198	0	0
T3	3608	1526	0	0
T4	522	121	0	0
T5	18447	18015	0	0
T12	15235	14795	0	0
T13	421	20	0	0
T14	403	2	0	0
T15	494	93	0	0
T16	494	93	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5534306	0	0
T1	353536	345785	0	0
T2	599	199	0	0
T3	3608	1529	0	0
T4	522	122	0	0
T5	18447	18020	0	0
T12	15235	14800	0	0
T13	421	21	0	0
T14	403	3	0	0
T15	494	94	0	0
T16	494	94	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	160	0	0
T1	353536	8	0	0
T2	599	0	0	0
T3	3608	1	0	0
T4	522	0	0	0
T5	18447	0	0	0
T12	15235	0	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T22	0	2	0	0
T39	0	2	0	0
T40	0	2	0	0
T41	0	1	0	0
T43	0	2	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	126	0	0
T1	353536	6	0	0
T2	599	0	0	0
T3	3608	1	0	0
T4	522	0	0	0
T5	18447	0	0	0
T12	15235	0	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T22	0	2	0	0
T39	0	2	0	0
T40	0	2	0	0
T41	0	1	0	0
T43	0	2	0	0
T45	0	1	0	0
T46	0	1	0	0
T119	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	124	0	0
T1	353536	6	0	0
T2	599	0	0	0
T3	3608	1	0	0
T4	522	0	0	0
T5	18447	0	0	0
T12	15235	0	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T22	0	2	0	0
T39	0	2	0	0
T40	0	2	0	0
T41	0	1	0	0
T43	0	2	0	0
T45	0	1	0	0
T46	0	1	0	0
T119	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	124	0	0
T1	353536	6	0	0
T2	599	0	0	0
T3	3608	1	0	0
T4	522	0	0	0
T5	18447	0	0	0
T12	15235	0	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T22	0	2	0	0
T39	0	2	0	0
T40	0	2	0	0
T41	0	1	0	0
T43	0	2	0	0
T45	0	1	0	0
T46	0	1	0	0
T119	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	751	0	0
T1	353536	37	0	0
T2	599	0	0	0
T3	3608	6	0	0
T4	522	0	0	0
T5	18447	0	0	0
T12	15235	0	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T22	0	17	0	0
T39	0	15	0	0
T40	0	9	0	0
T41	0	9	0	0
T43	0	5	0	0
T45	0	2	0	0
T46	0	11	0	0
T119	0	9	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	7002	0	0
T1	353536	34	0	0
T2	599	1	0	0
T3	3608	16	0	0
T4	522	5	0	0
T5	18447	24	0	0
T12	15235	30	0	0
T13	421	3	0	0
T14	403	0	0	0
T15	494	11	0	0
T16	494	10	0	0
T48	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5738952	0	0
T1	353536	346596	0	0
T2	599	199	0	0
T3	3608	1608	0	0
T4	522	122	0	0
T5	18447	18020	0	0
T12	15235	14800	0	0
T13	421	21	0	0
T14	403	3	0	0
T15	494	94	0	0
T16	494	94	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	124	0	0
T1	353536	6	0	0
T2	599	0	0	0
T3	3608	1	0	0
T4	522	0	0	0
T5	18447	0	0	0
T12	15235	0	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T22	0	2	0	0
T39	0	2	0	0
T40	0	2	0	0
T41	0	1	0	0
T43	0	2	0	0
T45	0	1	0	0
T46	0	1	0	0
T119	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T3,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T2,T3,T20

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T20,T51

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T20
1	0	Covered	T1,T4,T12
1	1	Covered	T2,T3,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T20,T51
0	1	Covered	T73,T85,T86
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T20,T51
0	1	Unreachable
1	0	Covered	T2,T20,T51

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T3,T20
DetectSt	168	Covered	T2,T20,T51
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T2,T20,T51

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T20,T51
DebounceSt->IdleSt	163	Covered	T3,T73,T74
DetectSt->IdleSt	186	Covered	T73,T85,T86
DetectSt->StableSt	191	Covered	T2,T20,T51
IdleSt->DebounceSt	148	Covered	T2,T3,T20
StableSt->IdleSt	206	Covered	T2,T20,T51

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T3,T20
0	1	Covered	T2,T3,T20
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T20,T51
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T3,T20
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T50,T77
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T20,T51
DebounceSt	-	0	1	0	-	-	-	Covered	T3,T73,T74
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T3,T20
DetectSt	-	-	-	-	1	-	-	Covered	T73,T85,T86
DetectSt	-	-	-	-	0	1	-	Covered	T2,T20,T51
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T20,T51
StableSt	-	-	-	-	-	-	0	Covered	T2,T20,T51
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6431240	176	0	0
CntIncr_A	6431240	36685	0	0
CntNoWrap_A	6431240	5736296	0	0
DetectStDropOut_A	6431240	13	0	0
DetectedOut_A	6431240	92237	0	0
DetectedPulseOut_A	6431240	44	0	0
DisabledIdleSt_A	6431240	5312239	0	0
DisabledNoDetection_A	6431240	5314715	0	0
EnterDebounceSt_A	6431240	121	0	0
EnterDetectSt_A	6431240	57	0	0
EnterStableSt_A	6431240	44	0	0
PulseIsPulse_A	6431240	44	0	0
StayInStableSt	6431240	92193	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6431240	7002	0	0
gen_low_level_sva.LowLevelEvent_A	6431240	5738952	0	0
gen_sticky_sva.StableStDropOut_A	6431240	282378	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	176	0	0
T2	599	2	0	0
T3	3608	3	0	0
T4	522	0	0	0
T5	18447	0	0	0
T12	15235	0	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T20	0	2	0	0
T48	451	0	0	0
T51	0	2	0	0
T54	0	4	0	0
T71	0	6	0	0
T72	0	2	0	0
T73	0	5	0	0
T74	0	3	0	0
T75	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	36685	0	0
T2	599	32	0	0
T3	3608	294	0	0
T4	522	0	0	0
T5	18447	0	0	0
T12	15235	0	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T20	0	76	0	0
T48	451	0	0	0
T51	0	41	0	0
T54	0	80	0	0
T71	0	147	0	0
T72	0	3888	0	0
T73	0	192	0	0
T74	0	147	0	0
T75	0	136	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5736296	0	0
T1	353536	346575	0	0
T2	599	196	0	0
T3	3608	1601	0	0
T4	522	121	0	0
T5	18447	18015	0	0
T12	15235	14795	0	0
T13	421	20	0	0
T14	403	2	0	0
T15	494	93	0	0
T16	494	93	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	13	0	0
T73	1207	2	0	0
T85	0	2	0	0
T86	0	4	0	0
T119	619	0	0	0
T126	0	2	0	0
T127	0	1	0	0
T128	0	2	0	0
T129	402	0	0	0
T130	38376	0	0	0
T131	402	0	0	0
T132	20775	0	0	0
T133	625	0	0	0
T134	14729	0	0	0
T135	614	0	0	0
T136	846	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	92237	0	0
T2	599	18	0	0
T3	3608	0	0	0
T4	522	0	0	0
T5	18447	0	0	0
T12	15235	0	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T20	0	1	0	0
T48	451	0	0	0
T51	0	152	0	0
T54	0	177	0	0
T71	0	346	0	0
T72	0	5893	0	0
T84	0	64	0	0
T121	0	89	0	0
T122	0	148	0	0
T123	0	142	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	44	0	0
T2	599	1	0	0
T3	3608	0	0	0
T4	522	0	0	0
T5	18447	0	0	0
T12	15235	0	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T20	0	1	0	0
T48	451	0	0	0
T51	0	1	0	0
T54	0	2	0	0
T71	0	3	0	0
T72	0	1	0	0
T84	0	1	0	0
T121	0	2	0	0
T122	0	1	0	0
T123	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5312239	0	0
T1	353536	346575	0	0
T2	599	30	0	0
T3	3608	1177	0	0
T4	522	121	0	0
T5	18447	18015	0	0
T12	15235	14795	0	0
T13	421	20	0	0
T14	403	2	0	0
T15	494	93	0	0
T16	494	93	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5314715	0	0
T1	353536	346596	0	0
T2	599	31	0	0
T3	3608	1181	0	0
T4	522	122	0	0
T5	18447	18020	0	0
T12	15235	14800	0	0
T13	421	21	0	0
T14	403	3	0	0
T15	494	94	0	0
T16	494	94	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	121	0	0
T2	599	1	0	0
T3	3608	3	0	0
T4	522	0	0	0
T5	18447	0	0	0
T12	15235	0	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T20	0	1	0	0
T48	451	0	0	0
T51	0	1	0	0
T54	0	2	0	0
T71	0	3	0	0
T72	0	1	0	0
T73	0	3	0	0
T74	0	3	0	0
T75	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	57	0	0
T2	599	1	0	0
T3	3608	0	0	0
T4	522	0	0	0
T5	18447	0	0	0
T12	15235	0	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T20	0	1	0	0
T48	451	0	0	0
T51	0	1	0	0
T54	0	2	0	0
T71	0	3	0	0
T72	0	1	0	0
T73	0	2	0	0
T84	0	1	0	0
T85	0	2	0	0
T121	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	44	0	0
T2	599	1	0	0
T3	3608	0	0	0
T4	522	0	0	0
T5	18447	0	0	0
T12	15235	0	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T20	0	1	0	0
T48	451	0	0	0
T51	0	1	0	0
T54	0	2	0	0
T71	0	3	0	0
T72	0	1	0	0
T84	0	1	0	0
T121	0	2	0	0
T122	0	1	0	0
T123	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	44	0	0
T2	599	1	0	0
T3	3608	0	0	0
T4	522	0	0	0
T5	18447	0	0	0
T12	15235	0	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T20	0	1	0	0
T48	451	0	0	0
T51	0	1	0	0
T54	0	2	0	0
T71	0	3	0	0
T72	0	1	0	0
T84	0	1	0	0
T121	0	2	0	0
T122	0	1	0	0
T123	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	92193	0	0
T2	599	17	0	0
T3	3608	0	0	0
T4	522	0	0	0
T5	18447	0	0	0
T12	15235	0	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T48	451	0	0	0
T51	0	151	0	0
T54	0	175	0	0
T71	0	343	0	0
T72	0	5892	0	0
T84	0	63	0	0
T121	0	87	0	0
T122	0	147	0	0
T123	0	141	0	0
T137	0	396	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	7002	0	0
T1	353536	34	0	0
T2	599	1	0	0
T3	3608	16	0	0
T4	522	5	0	0
T5	18447	24	0	0
T12	15235	30	0	0
T13	421	3	0	0
T14	403	0	0	0
T15	494	11	0	0
T16	494	10	0	0
T48	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5738952	0	0
T1	353536	346596	0	0
T2	599	199	0	0
T3	3608	1608	0	0
T4	522	122	0	0
T5	18447	18020	0	0
T12	15235	14800	0	0
T13	421	21	0	0
T14	403	3	0	0
T15	494	94	0	0
T16	494	94	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	282378	0	0
T2	599	97	0	0
T3	3608	0	0	0
T4	522	0	0	0
T5	18447	0	0	0
T12	15235	0	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T20	0	37	0	0
T48	451	0	0	0
T51	0	194	0	0
T54	0	235	0	0
T71	0	206	0	0
T72	0	30	0	0
T84	0	101	0	0
T121	0	343	0	0
T122	0	175	0	0
T123	0	258	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T3,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T2,T3,T20

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T3,T20,T54

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T20
1	0	Covered	T1,T4,T13
1	1	Covered	T2,T3,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T20,T71
0	1	Covered	T54,T84,T85
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T20,T71
0	1	Unreachable
1	0	Covered	T3,T20,T71

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T3,T20
DetectSt	168	Covered	T3,T20,T54
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T3,T20,T71

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T20,T54
DebounceSt->IdleSt	163	Covered	T2,T51,T54
DetectSt->IdleSt	186	Covered	T54,T84,T85
DetectSt->StableSt	191	Covered	T3,T20,T71
IdleSt->DebounceSt	148	Covered	T2,T3,T20
StableSt->IdleSt	206	Covered	T3,T20,T71

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T3,T20
0	1	Covered	T2,T3,T20
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T20,T54
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T3,T20
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T50,T77
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T20,T54
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T51,T54
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T3,T20
DetectSt	-	-	-	-	1	-	-	Covered	T54,T84,T85
DetectSt	-	-	-	-	0	1	-	Covered	T3,T20,T71
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T20,T71
StableSt	-	-	-	-	-	-	0	Covered	T3,T20,T71
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6431240	165	0	0
CntIncr_A	6431240	79265	0	0
CntNoWrap_A	6431240	5736307	0	0
DetectStDropOut_A	6431240	14	0	0
DetectedOut_A	6431240	216730	0	0
DetectedPulseOut_A	6431240	52	0	0
DisabledIdleSt_A	6431240	5312239	0	0
DisabledNoDetection_A	6431240	5314715	0	0
EnterDebounceSt_A	6431240	101	0	0
EnterDetectSt_A	6431240	66	0	0
EnterStableSt_A	6431240	52	0	0
PulseIsPulse_A	6431240	52	0	0
StayInStableSt	6431240	216678	0	0
gen_high_level_sva.HighLevelEvent_A	6431240	5738952	0	0
gen_sticky_sva.StableStDropOut_A	6431240	124329	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	165	0	0
T2	599	1	0	0
T3	3608	2	0	0
T4	522	0	0	0
T5	18447	0	0	0
T12	15235	0	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T20	0	2	0	0
T48	451	0	0	0
T51	0	3	0	0
T54	0	9	0	0
T71	0	6	0	0
T72	0	2	0	0
T73	0	2	0	0
T74	0	3	0	0
T75	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	79265	0	0
T2	599	75	0	0
T3	3608	44	0	0
T4	522	0	0	0
T5	18447	0	0	0
T12	15235	0	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T20	0	28	0	0
T48	451	0	0	0
T51	0	96	0	0
T54	0	228	0	0
T71	0	90	0	0
T72	0	23	0	0
T73	0	67	0	0
T74	0	120	0	0
T75	0	40	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5736307	0	0
T1	353536	346575	0	0
T2	599	197	0	0
T3	3608	1602	0	0
T4	522	121	0	0
T5	18447	18015	0	0
T12	15235	14795	0	0
T13	421	20	0	0
T14	403	2	0	0
T15	494	93	0	0
T16	494	93	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	14	0	0
T29	21783	0	0	0
T33	12853	0	0	0
T46	3119	0	0	0
T54	977	3	0	0
T84	0	1	0	0
T85	0	1	0	0
T89	32959	0	0	0
T118	17370	0	0	0
T120	27001	0	0	0
T122	0	3	0	0
T138	0	1	0	0
T139	0	3	0	0
T140	0	2	0	0
T141	522	0	0	0
T142	402	0	0	0
T143	402	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	216730	0	0
T3	3608	196	0	0
T5	18447	0	0	0
T6	566	0	0	0
T7	15844	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T20	0	3	0	0
T21	494	0	0	0
T48	451	0	0	0
T49	526	0	0	0
T71	0	202	0	0
T72	0	35	0	0
T73	0	317	0	0
T75	0	53	0	0
T84	0	1	0	0
T121	0	60	0	0
T123	0	600	0	0
T124	0	291	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	52	0	0
T3	3608	1	0	0
T5	18447	0	0	0
T6	566	0	0	0
T7	15844	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T20	0	1	0	0
T21	494	0	0	0
T48	451	0	0	0
T49	526	0	0	0
T71	0	3	0	0
T72	0	1	0	0
T73	0	1	0	0
T75	0	1	0	0
T84	0	1	0	0
T121	0	2	0	0
T123	0	1	0	0
T124	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5312239	0	0
T1	353536	346575	0	0
T2	599	30	0	0
T3	3608	1177	0	0
T4	522	121	0	0
T5	18447	18015	0	0
T12	15235	14795	0	0
T13	421	20	0	0
T14	403	2	0	0
T15	494	93	0	0
T16	494	93	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5314715	0	0
T1	353536	346596	0	0
T2	599	31	0	0
T3	3608	1181	0	0
T4	522	122	0	0
T5	18447	18020	0	0
T12	15235	14800	0	0
T13	421	21	0	0
T14	403	3	0	0
T15	494	94	0	0
T16	494	94	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	101	0	0
T2	599	1	0	0
T3	3608	1	0	0
T4	522	0	0	0
T5	18447	0	0	0
T12	15235	0	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T20	0	1	0	0
T48	451	0	0	0
T51	0	3	0	0
T54	0	6	0	0
T71	0	3	0	0
T72	0	1	0	0
T73	0	1	0	0
T74	0	3	0	0
T75	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	66	0	0
T3	3608	1	0	0
T5	18447	0	0	0
T6	566	0	0	0
T7	15844	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T20	0	1	0	0
T21	494	0	0	0
T48	451	0	0	0
T49	526	0	0	0
T54	0	3	0	0
T71	0	3	0	0
T72	0	1	0	0
T73	0	1	0	0
T75	0	1	0	0
T84	0	2	0	0
T85	0	1	0	0
T121	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	52	0	0
T3	3608	1	0	0
T5	18447	0	0	0
T6	566	0	0	0
T7	15844	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T20	0	1	0	0
T21	494	0	0	0
T48	451	0	0	0
T49	526	0	0	0
T71	0	3	0	0
T72	0	1	0	0
T73	0	1	0	0
T75	0	1	0	0
T84	0	1	0	0
T121	0	2	0	0
T123	0	1	0	0
T124	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	52	0	0
T3	3608	1	0	0
T5	18447	0	0	0
T6	566	0	0	0
T7	15844	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T20	0	1	0	0
T21	494	0	0	0
T48	451	0	0	0
T49	526	0	0	0
T71	0	3	0	0
T72	0	1	0	0
T73	0	1	0	0
T75	0	1	0	0
T84	0	1	0	0
T121	0	2	0	0
T123	0	1	0	0
T124	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	216678	0	0
T3	3608	195	0	0
T5	18447	0	0	0
T6	566	0	0	0
T7	15844	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T20	0	2	0	0
T21	494	0	0	0
T48	451	0	0	0
T49	526	0	0	0
T71	0	199	0	0
T72	0	34	0	0
T73	0	316	0	0
T75	0	52	0	0
T121	0	58	0	0
T123	0	599	0	0
T124	0	289	0	0
T126	0	199	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5738952	0	0
T1	353536	346596	0	0
T2	599	199	0	0
T3	3608	1608	0	0
T4	522	122	0	0
T5	18447	18020	0	0
T12	15235	14800	0	0
T13	421	21	0	0
T14	403	3	0	0
T15	494	94	0	0
T16	494	94	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	124329	0	0
T3	3608	173	0	0
T5	18447	0	0	0
T6	566	0	0	0
T7	15844	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T20	0	68	0	0
T21	494	0	0	0
T48	451	0	0	0
T49	526	0	0	0
T71	0	413	0	0
T72	0	9753	0	0
T73	0	73	0	0
T75	0	86	0	0
T84	0	35	0	0
T121	0	381	0	0
T123	0	92	0	0
T124	0	124	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T3,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T2,T3,T20

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T3,T20

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T20
1	0	Covered	T1,T4,T12
1	1	Covered	T2,T3,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T51
0	1	Covered	T20,T54,T75
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T51
0	1	Unreachable
1	0	Covered	T2,T3,T51

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T3,T20
DetectSt	168	Covered	T2,T3,T20
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T2,T3,T51

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T3,T20
DebounceSt->IdleSt	163	Covered	T54,T75,T50
DetectSt->IdleSt	186	Covered	T20,T54,T75
DetectSt->StableSt	191	Covered	T2,T3,T51
IdleSt->DebounceSt	148	Covered	T2,T3,T20
StableSt->IdleSt	206	Covered	T2,T3,T51

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T3,T20
0	1	Covered	T2,T3,T20
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T20
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T3,T20
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T50,T77
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T3,T20
DebounceSt	-	0	1	0	-	-	-	Covered	T54,T75,T123
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T3,T20
DetectSt	-	-	-	-	1	-	-	Covered	T20,T54,T75
DetectSt	-	-	-	-	0	1	-	Covered	T2,T3,T51
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T3,T51
StableSt	-	-	-	-	-	-	0	Covered	T2,T3,T51
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6431240	178	0	0
CntIncr_A	6431240	5955	0	0
CntNoWrap_A	6431240	5736294	0	0
DetectStDropOut_A	6431240	20	0	0
DetectedOut_A	6431240	6087	0	0
DetectedPulseOut_A	6431240	51	0	0
DisabledIdleSt_A	6431240	5312239	0	0
DisabledNoDetection_A	6431240	5314715	0	0
EnterDebounceSt_A	6431240	109	0	0
EnterDetectSt_A	6431240	71	0	0
EnterStableSt_A	6431240	51	0	0
PulseIsPulse_A	6431240	51	0	0
StayInStableSt	6431240	6036	0	0
gen_high_event_sva.HighLevelEvent_A	6431240	5738952	0	0
gen_high_level_sva.HighLevelEvent_A	6431240	5738952	0	0
gen_sticky_sva.StableStDropOut_A	6431240	130858	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	178	0	0
T2	599	2	0	0
T3	3608	2	0	0
T4	522	0	0	0
T5	18447	0	0	0
T12	15235	0	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T20	0	2	0	0
T48	451	0	0	0
T51	0	2	0	0
T54	0	9	0	0
T71	0	6	0	0
T72	0	2	0	0
T73	0	2	0	0
T74	0	2	0	0
T75	0	3	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5955	0	0
T2	599	11	0	0
T3	3608	85	0	0
T4	522	0	0	0
T5	18447	0	0	0
T12	15235	0	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T20	0	89	0	0
T48	451	0	0	0
T51	0	58	0	0
T54	0	355	0	0
T71	0	255	0	0
T72	0	74	0	0
T73	0	32	0	0
T74	0	41	0	0
T75	0	136	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5736294	0	0
T1	353536	346575	0	0
T2	599	196	0	0
T3	3608	1602	0	0
T4	522	121	0	0
T5	18447	18015	0	0
T12	15235	14795	0	0
T13	421	20	0	0
T14	403	2	0	0
T15	494	93	0	0
T16	494	93	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	20	0	0
T20	547	1	0	0
T27	16458	0	0	0
T28	24376	0	0	0
T42	4517	0	0	0
T43	39452	0	0	0
T44	4771	0	0	0
T51	831	0	0	0
T54	0	2	0	0
T67	25992	0	0	0
T75	0	1	0	0
T80	0	2	0	0
T121	0	4	0	0
T122	0	1	0	0
T123	0	4	0	0
T140	0	1	0	0
T144	0	1	0	0
T145	0	1	0	0
T146	427	0	0	0
T147	944	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	6087	0	0
T2	599	2	0	0
T3	3608	238	0	0
T4	522	0	0	0
T5	18447	0	0	0
T12	15235	0	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T48	451	0	0	0
T51	0	230	0	0
T54	0	73	0	0
T71	0	370	0	0
T72	0	77	0	0
T73	0	156	0	0
T74	0	174	0	0
T84	0	137	0	0
T121	0	1	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	51	0	0
T2	599	1	0	0
T3	3608	1	0	0
T4	522	0	0	0
T5	18447	0	0	0
T12	15235	0	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T48	451	0	0	0
T51	0	1	0	0
T54	0	2	0	0
T71	0	3	0	0
T72	0	1	0	0
T73	0	1	0	0
T74	0	1	0	0
T84	0	1	0	0
T121	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5312239	0	0
T1	353536	346575	0	0
T2	599	30	0	0
T3	3608	1177	0	0
T4	522	121	0	0
T5	18447	18015	0	0
T12	15235	14795	0	0
T13	421	20	0	0
T14	403	2	0	0
T15	494	93	0	0
T16	494	93	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5314715	0	0
T1	353536	346596	0	0
T2	599	31	0	0
T3	3608	1181	0	0
T4	522	122	0	0
T5	18447	18020	0	0
T12	15235	14800	0	0
T13	421	21	0	0
T14	403	3	0	0
T15	494	94	0	0
T16	494	94	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	109	0	0
T2	599	1	0	0
T3	3608	1	0	0
T4	522	0	0	0
T5	18447	0	0	0
T12	15235	0	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T20	0	1	0	0
T48	451	0	0	0
T51	0	1	0	0
T54	0	5	0	0
T71	0	3	0	0
T72	0	1	0	0
T73	0	1	0	0
T74	0	1	0	0
T75	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	71	0	0
T2	599	1	0	0
T3	3608	1	0	0
T4	522	0	0	0
T5	18447	0	0	0
T12	15235	0	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T20	0	1	0	0
T48	451	0	0	0
T51	0	1	0	0
T54	0	4	0	0
T71	0	3	0	0
T72	0	1	0	0
T73	0	1	0	0
T74	0	1	0	0
T75	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	51	0	0
T2	599	1	0	0
T3	3608	1	0	0
T4	522	0	0	0
T5	18447	0	0	0
T12	15235	0	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T48	451	0	0	0
T51	0	1	0	0
T54	0	2	0	0
T71	0	3	0	0
T72	0	1	0	0
T73	0	1	0	0
T74	0	1	0	0
T84	0	1	0	0
T121	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	51	0	0
T2	599	1	0	0
T3	3608	1	0	0
T4	522	0	0	0
T5	18447	0	0	0
T12	15235	0	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T48	451	0	0	0
T51	0	1	0	0
T54	0	2	0	0
T71	0	3	0	0
T72	0	1	0	0
T73	0	1	0	0
T74	0	1	0	0
T84	0	1	0	0
T121	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	6036	0	0
T2	599	1	0	0
T3	3608	237	0	0
T4	522	0	0	0
T5	18447	0	0	0
T12	15235	0	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T48	451	0	0	0
T51	0	229	0	0
T54	0	71	0	0
T71	0	367	0	0
T72	0	76	0	0
T73	0	155	0	0
T74	0	173	0	0
T84	0	136	0	0
T85	0	56	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5738952	0	0
T1	353536	346596	0	0
T2	599	199	0	0
T3	3608	1608	0	0
T4	522	122	0	0
T5	18447	18020	0	0
T12	15235	14800	0	0
T13	421	21	0	0
T14	403	3	0	0
T15	494	94	0	0
T16	494	94	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5738952	0	0
T1	353536	346596	0	0
T2	599	199	0	0
T3	3608	1608	0	0
T4	522	122	0	0
T5	18447	18020	0	0
T12	15235	14800	0	0
T13	421	21	0	0
T14	403	3	0	0
T15	494	94	0	0
T16	494	94	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	130858	0	0
T2	599	148	0	0
T3	3608	97	0	0
T4	522	0	0	0
T5	18447	0	0	0
T12	15235	0	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T48	451	0	0	0
T51	0	112	0	0
T54	0	61	0	0
T71	0	102	0	0
T72	0	9680	0	0
T73	0	271	0	0
T74	0	113	0	0
T84	0	26	0	0
T121	0	25	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T6,T10,T32

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T6,T10,T32

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T6,T10,T32

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T10,T31
1	0	Covered	T1,T2,T4
1	1	Covered	T6,T10,T32

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T10,T32
0	1	Covered	T148
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T10,T32
0	1	Covered	T10,T32,T149
1	0	Covered	T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T10,T32
1	-	Covered	T10,T32,T149

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T10,T32
DetectSt	168	Covered	T6,T10,T32
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T6,T10,T32

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T10,T32
DebounceSt->IdleSt	163	Covered	T77
DetectSt->IdleSt	186	Covered	T148
DetectSt->StableSt	191	Covered	T6,T10,T32
IdleSt->DebounceSt	148	Covered	T6,T10,T32
StableSt->IdleSt	206	Covered	T10,T32,T33

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T10,T32
0	1	Covered	T6,T10,T32
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T10,T32
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T10,T32
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T77
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T10,T32
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T10,T32
DetectSt	-	-	-	-	1	-	-	Covered	T148
DetectSt	-	-	-	-	0	1	-	Covered	T6,T10,T32
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T32,T149
StableSt	-	-	-	-	-	-	0	Covered	T6,T10,T32
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6431240	65	0	0
CntIncr_A	6431240	1982	0	0
CntNoWrap_A	6431240	5736407	0	0
DetectStDropOut_A	6431240	1	0	0
DetectedOut_A	6431240	1499	0	0
DetectedPulseOut_A	6431240	31	0	0
DisabledIdleSt_A	6431240	5620427	0	0
DisabledNoDetection_A	6431240	5622853	0	0
EnterDebounceSt_A	6431240	33	0	0
EnterDetectSt_A	6431240	32	0	0
EnterStableSt_A	6431240	31	0	0
PulseIsPulse_A	6431240	31	0	0
StayInStableSt	6431240	1450	0	0
gen_high_level_sva.HighLevelEvent_A	6431240	5738952	0	0
gen_not_sticky_sva.StableStDropOut_A	6431240	12	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	65	0	0
T6	566	2	0	0
T7	15844	0	0	0
T8	13312	0	0	0
T9	838	0	0	0
T10	665	2	0	0
T21	494	0	0	0
T23	4517	0	0	0
T32	0	4	0	0
T33	0	2	0	0
T35	0	2	0	0
T49	526	0	0	0
T90	8402	0	0	0
T91	424	0	0	0
T135	0	2	0	0
T136	0	2	0	0
T149	0	2	0	0
T150	0	2	0	0
T151	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	1982	0	0
T6	566	15	0	0
T7	15844	0	0	0
T8	13312	0	0	0
T9	838	0	0	0
T10	665	35	0	0
T21	494	0	0	0
T23	4517	0	0	0
T32	0	136	0	0
T33	0	28	0	0
T35	0	100	0	0
T49	526	0	0	0
T90	8402	0	0	0
T91	424	0	0	0
T135	0	95	0	0
T136	0	88	0	0
T149	0	37	0	0
T150	0	45	0	0
T151	0	33	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5736407	0	0
T1	353536	346575	0	0
T2	599	198	0	0
T3	3608	1604	0	0
T4	522	121	0	0
T5	18447	18015	0	0
T12	15235	14795	0	0
T13	421	20	0	0
T14	403	2	0	0
T15	494	93	0	0
T16	494	93	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	1	0	0
T106	21011	0	0	0
T140	2906	0	0	0
T148	776	1	0	0
T152	494	0	0	0
T153	423	0	0	0
T154	965	0	0	0
T155	7681	0	0	0
T156	489	0	0	0
T157	2133	0	0	0
T158	522	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	1499	0	0
T6	566	39	0	0
T7	15844	0	0	0
T8	13312	0	0	0
T9	838	0	0	0
T10	665	91	0	0
T21	494	0	0	0
T23	4517	0	0	0
T32	0	85	0	0
T33	0	41	0	0
T35	0	42	0	0
T49	526	0	0	0
T90	8402	0	0	0
T91	424	0	0	0
T135	0	41	0	0
T136	0	42	0	0
T149	0	26	0	0
T150	0	41	0	0
T151	0	101	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	31	0	0
T6	566	1	0	0
T7	15844	0	0	0
T8	13312	0	0	0
T9	838	0	0	0
T10	665	1	0	0
T21	494	0	0	0
T23	4517	0	0	0
T32	0	2	0	0
T33	0	1	0	0
T35	0	1	0	0
T49	526	0	0	0
T90	8402	0	0	0
T91	424	0	0	0
T135	0	1	0	0
T136	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T151	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5620427	0	0
T1	353536	346575	0	0
T2	599	198	0	0
T3	3608	1604	0	0
T4	522	121	0	0
T5	18447	18015	0	0
T12	15235	14795	0	0
T13	421	20	0	0
T14	403	2	0	0
T15	494	93	0	0
T16	494	93	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5622853	0	0
T1	353536	346596	0	0
T2	599	199	0	0
T3	3608	1608	0	0
T4	522	122	0	0
T5	18447	18020	0	0
T12	15235	14800	0	0
T13	421	21	0	0
T14	403	3	0	0
T15	494	94	0	0
T16	494	94	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	33	0	0
T6	566	1	0	0
T7	15844	0	0	0
T8	13312	0	0	0
T9	838	0	0	0
T10	665	1	0	0
T21	494	0	0	0
T23	4517	0	0	0
T32	0	2	0	0
T33	0	1	0	0
T35	0	1	0	0
T49	526	0	0	0
T90	8402	0	0	0
T91	424	0	0	0
T135	0	1	0	0
T136	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T151	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	32	0	0
T6	566	1	0	0
T7	15844	0	0	0
T8	13312	0	0	0
T9	838	0	0	0
T10	665	1	0	0
T21	494	0	0	0
T23	4517	0	0	0
T32	0	2	0	0
T33	0	1	0	0
T35	0	1	0	0
T49	526	0	0	0
T90	8402	0	0	0
T91	424	0	0	0
T135	0	1	0	0
T136	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T151	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	31	0	0
T6	566	1	0	0
T7	15844	0	0	0
T8	13312	0	0	0
T9	838	0	0	0
T10	665	1	0	0
T21	494	0	0	0
T23	4517	0	0	0
T32	0	2	0	0
T33	0	1	0	0
T35	0	1	0	0
T49	526	0	0	0
T90	8402	0	0	0
T91	424	0	0	0
T135	0	1	0	0
T136	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T151	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	31	0	0
T6	566	1	0	0
T7	15844	0	0	0
T8	13312	0	0	0
T9	838	0	0	0
T10	665	1	0	0
T21	494	0	0	0
T23	4517	0	0	0
T32	0	2	0	0
T33	0	1	0	0
T35	0	1	0	0
T49	526	0	0	0
T90	8402	0	0	0
T91	424	0	0	0
T135	0	1	0	0
T136	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T151	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	1450	0	0
T6	566	37	0	0
T7	15844	0	0	0
T8	13312	0	0	0
T9	838	0	0	0
T10	665	90	0	0
T21	494	0	0	0
T23	4517	0	0	0
T32	0	82	0	0
T33	0	39	0	0
T35	0	40	0	0
T49	526	0	0	0
T90	8402	0	0	0
T91	424	0	0	0
T135	0	39	0	0
T136	0	40	0	0
T149	0	25	0	0
T150	0	39	0	0
T151	0	100	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5738952	0	0
T1	353536	346596	0	0
T2	599	199	0	0
T3	3608	1608	0	0
T4	522	122	0	0
T5	18447	18020	0	0
T12	15235	14800	0	0
T13	421	21	0	0
T14	403	3	0	0
T15	494	94	0	0
T16	494	94	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	12	0	0
T10	665	1	0	0
T11	646	0	0	0
T31	96676	0	0	0
T32	2567	1	0	0
T35	897	0	0	0
T52	803	0	0	0
T58	491	0	0	0
T79	0	1	0	0
T82	0	1	0	0
T91	424	0	0	0
T108	425	0	0	0
T149	0	1	0	0
T151	0	1	0	0
T159	0	1	0	0
T160	0	1	0	0
T161	0	1	0	0
T162	0	1	0	0
T163	429	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T6,T9,T32

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T6,T9,T32

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T6,T9,T32

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T9,T31
1	0	Covered	T1,T4,T12
1	1	Covered	T6,T9,T32

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T9,T32
0	1	Covered	T78,T79
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T9,T32
0	1	Covered	T6,T9,T32
1	0	Covered	T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T9,T32
1	-	Covered	T6,T9,T32

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T9,T32
DetectSt	168	Covered	T6,T9,T32
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T6,T9,T32

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T9,T32
DebounceSt->IdleSt	163	Covered	T36,T164,T165
DetectSt->IdleSt	186	Covered	T78,T79
DetectSt->StableSt	191	Covered	T6,T9,T32
IdleSt->DebounceSt	148	Covered	T6,T9,T32
StableSt->IdleSt	206	Covered	T6,T9,T32

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T9,T32
0	1	Covered	T6,T9,T32
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T9,T32
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T9,T32
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T77
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T9,T32
DebounceSt	-	0	1	0	-	-	-	Covered	T36,T164,T165
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T9,T32
DetectSt	-	-	-	-	1	-	-	Covered	T78,T79
DetectSt	-	-	-	-	0	1	-	Covered	T6,T9,T32
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T6,T9,T32
StableSt	-	-	-	-	-	-	0	Covered	T6,T9,T32
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6431240	139	0	0
CntIncr_A	6431240	18471	0	0
CntNoWrap_A	6431240	5736333	0	0
DetectStDropOut_A	6431240	2	0	0
DetectedOut_A	6431240	22588	0	0
DetectedPulseOut_A	6431240	64	0	0
DisabledIdleSt_A	6431240	5561026	0	0
DisabledNoDetection_A	6431240	5563443	0	0
EnterDebounceSt_A	6431240	73	0	0
EnterDetectSt_A	6431240	66	0	0
EnterStableSt_A	6431240	64	0	0
PulseIsPulse_A	6431240	64	0	0
StayInStableSt	6431240	22492	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6431240	2708	0	0
gen_low_level_sva.LowLevelEvent_A	6431240	5738952	0	0
gen_not_sticky_sva.StableStDropOut_A	6431240	31	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	139	0	0
T6	566	2	0	0
T7	15844	0	0	0
T8	13312	0	0	0
T9	838	4	0	0
T10	665	0	0	0
T21	494	0	0	0
T23	4517	0	0	0
T32	0	10	0	0
T33	0	6	0	0
T35	0	2	0	0
T36	0	2	0	0
T49	526	0	0	0
T90	8402	0	0	0
T91	424	0	0	0
T133	0	2	0	0
T150	0	2	0	0
T166	0	2	0	0
T167	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	18471	0	0
T6	566	15	0	0
T7	15844	0	0	0
T8	13312	0	0	0
T9	838	164	0	0
T10	665	0	0	0
T21	494	0	0	0
T23	4517	0	0	0
T32	0	181	0	0
T33	0	159	0	0
T35	0	100	0	0
T36	0	108	0	0
T49	526	0	0	0
T90	8402	0	0	0
T91	424	0	0	0
T133	0	60	0	0
T150	0	45	0	0
T166	0	86	0	0
T167	0	73	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5736333	0	0
T1	353536	346575	0	0
T2	599	198	0	0
T3	3608	1604	0	0
T4	522	121	0	0
T5	18447	18015	0	0
T12	15235	14795	0	0
T13	421	20	0	0
T14	403	2	0	0
T15	494	93	0	0
T16	494	93	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	2	0	0
T78	646	1	0	0
T79	0	1	0	0
T168	950	0	0	0
T169	682	0	0	0
T170	532	0	0	0
T171	522	0	0	0
T172	404	0	0	0
T173	501	0	0	0
T174	4003	0	0	0
T175	421	0	0	0
T176	502	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	22588	0	0
T6	566	87	0	0
T7	15844	0	0	0
T8	13312	0	0	0
T9	838	141	0	0
T10	665	0	0	0
T21	494	0	0	0
T23	4517	0	0	0
T32	0	203	0	0
T33	0	243	0	0
T35	0	244	0	0
T49	526	0	0	0
T50	0	9	0	0
T90	8402	0	0	0
T91	424	0	0	0
T133	0	41	0	0
T150	0	115	0	0
T166	0	153	0	0
T167	0	213	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	64	0	0
T6	566	1	0	0
T7	15844	0	0	0
T8	13312	0	0	0
T9	838	2	0	0
T10	665	0	0	0
T21	494	0	0	0
T23	4517	0	0	0
T32	0	5	0	0
T33	0	3	0	0
T35	0	1	0	0
T49	526	0	0	0
T50	0	1	0	0
T90	8402	0	0	0
T91	424	0	0	0
T133	0	1	0	0
T150	0	1	0	0
T166	0	1	0	0
T167	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5561026	0	0
T1	353536	346575	0	0
T2	599	198	0	0
T3	3608	1604	0	0
T4	522	121	0	0
T5	18447	18015	0	0
T12	15235	14795	0	0
T13	421	20	0	0
T14	403	2	0	0
T15	494	93	0	0
T16	494	93	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5563443	0	0
T1	353536	346596	0	0
T2	599	199	0	0
T3	3608	1608	0	0
T4	522	122	0	0
T5	18447	18020	0	0
T12	15235	14800	0	0
T13	421	21	0	0
T14	403	3	0	0
T15	494	94	0	0
T16	494	94	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	73	0	0
T6	566	1	0	0
T7	15844	0	0	0
T8	13312	0	0	0
T9	838	2	0	0
T10	665	0	0	0
T21	494	0	0	0
T23	4517	0	0	0
T32	0	5	0	0
T33	0	3	0	0
T35	0	1	0	0
T36	0	2	0	0
T49	526	0	0	0
T90	8402	0	0	0
T91	424	0	0	0
T133	0	1	0	0
T150	0	1	0	0
T166	0	1	0	0
T167	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	66	0	0
T6	566	1	0	0
T7	15844	0	0	0
T8	13312	0	0	0
T9	838	2	0	0
T10	665	0	0	0
T21	494	0	0	0
T23	4517	0	0	0
T32	0	5	0	0
T33	0	3	0	0
T35	0	1	0	0
T49	526	0	0	0
T50	0	1	0	0
T90	8402	0	0	0
T91	424	0	0	0
T133	0	1	0	0
T150	0	1	0	0
T166	0	1	0	0
T167	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	64	0	0
T6	566	1	0	0
T7	15844	0	0	0
T8	13312	0	0	0
T9	838	2	0	0
T10	665	0	0	0
T21	494	0	0	0
T23	4517	0	0	0
T32	0	5	0	0
T33	0	3	0	0
T35	0	1	0	0
T49	526	0	0	0
T50	0	1	0	0
T90	8402	0	0	0
T91	424	0	0	0
T133	0	1	0	0
T150	0	1	0	0
T166	0	1	0	0
T167	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	64	0	0
T6	566	1	0	0
T7	15844	0	0	0
T8	13312	0	0	0
T9	838	2	0	0
T10	665	0	0	0
T21	494	0	0	0
T23	4517	0	0	0
T32	0	5	0	0
T33	0	3	0	0
T35	0	1	0	0
T49	526	0	0	0
T50	0	1	0	0
T90	8402	0	0	0
T91	424	0	0	0
T133	0	1	0	0
T150	0	1	0	0
T166	0	1	0	0
T167	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	22492	0	0
T6	566	86	0	0
T7	15844	0	0	0
T8	13312	0	0	0
T9	838	138	0	0
T10	665	0	0	0
T21	494	0	0	0
T23	4517	0	0	0
T32	0	197	0	0
T33	0	238	0	0
T35	0	243	0	0
T49	526	0	0	0
T50	0	8	0	0
T90	8402	0	0	0
T91	424	0	0	0
T133	0	39	0	0
T150	0	114	0	0
T166	0	151	0	0
T167	0	209	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	2708	0	0
T1	353536	23	0	0
T2	599	0	0	0
T3	3608	6	0	0
T4	522	4	0	0
T5	18447	0	0	0
T6	0	1	0	0
T12	15235	0	0	0
T13	421	2	0	0
T14	403	0	0	0
T15	494	5	0	0
T16	494	5	0	0
T21	0	6	0	0
T48	0	5	0	0
T49	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5738952	0	0
T1	353536	346596	0	0
T2	599	199	0	0
T3	3608	1608	0	0
T4	522	122	0	0
T5	18447	18020	0	0
T12	15235	14800	0	0
T13	421	21	0	0
T14	403	3	0	0
T15	494	94	0	0
T16	494	94	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	31	0	0
T6	566	1	0	0
T7	15844	0	0	0
T8	13312	0	0	0
T9	838	1	0	0
T10	665	0	0	0
T21	494	0	0	0
T23	4517	0	0	0
T32	0	4	0	0
T33	0	1	0	0
T35	0	1	0	0
T49	526	0	0	0
T90	8402	0	0	0
T91	424	0	0	0
T150	0	1	0	0
T177	0	1	0	0
T178	0	1	0	0
T179	0	1	0	0
T180	0	1	0	0