Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.21	93.48	90.48		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.21	93.48	90.48		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T4,T12

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T4,T12
1	1	Covered	T1,T4,T12

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T11,T32,T35

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T11,T32,T35

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T11,T32,T35

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T32,T35
1	0	Covered	T1,T4,T12
1	1	Covered	T11,T32,T35

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T32,T35
0	1	Covered	T35,T82,T178
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T32,T35
0	1	Covered	T32,T33,T34
1	0	Covered	T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T32,T35
1	-	Covered	T32,T33,T34

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T11,T32,T35
DetectSt	168	Covered	T11,T32,T35
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T11,T32,T35

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T11,T32,T35
DebounceSt->IdleSt	163	Covered	T11,T33,T167
DetectSt->IdleSt	186	Covered	T35,T82,T178
DetectSt->StableSt	191	Covered	T11,T32,T35
IdleSt->DebounceSt	148	Covered	T11,T32,T35
StableSt->IdleSt	206	Covered	T32,T33,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T11,T32,T35
0	1	Covered	T11,T32,T35
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T32,T35
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T11,T32,T35
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T12
DebounceSt	-	1	-	-	-	-	-	Covered	T77
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T32,T35
DebounceSt	-	0	1	0	-	-	-	Covered	T11,T33,T167
DebounceSt	-	0	0	-	-	-	-	Covered	T11,T32,T35
DetectSt	-	-	-	-	1	-	-	Covered	T35,T82,T178
DetectSt	-	-	-	-	0	1	-	Covered	T11,T32,T35
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T32,T33,T34
StableSt	-	-	-	-	-	-	0	Covered	T11,T32,T35
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6431240	142	0	0
CntIncr_A	6431240	4205	0	0
CntNoWrap_A	6431240	5736330	0	0
DetectStDropOut_A	6431240	4	0	0
DetectedOut_A	6431240	4702	0	0
DetectedPulseOut_A	6431240	62	0	0
DisabledIdleSt_A	6431240	5716053	0	0
DisabledNoDetection_A	6431240	5718477	0	0
EnterDebounceSt_A	6431240	76	0	0
EnterDetectSt_A	6431240	66	0	0
EnterStableSt_A	6431240	62	0	0
PulseIsPulse_A	6431240	62	0	0
StayInStableSt	6431240	4612	0	0
gen_high_level_sva.HighLevelEvent_A	6431240	5738952	0	0
gen_not_sticky_sva.StableStDropOut_A	6431240	33	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	142	0	0
T11	646	3	0	0
T31	96676	0	0	0
T32	2567	6	0	0
T33	0	10	0	0
T34	0	2	0	0
T35	897	4	0	0
T37	17506	0	0	0
T50	0	2	0	0
T52	803	0	0	0
T59	498	0	0	0
T64	522	0	0	0
T86	0	4	0	0
T150	0	2	0	0
T163	429	0	0	0
T167	0	9	0	0
T185	0	2	0	0
T186	440	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	4205	0	0
T11	646	82	0	0
T31	96676	0	0	0
T32	2567	151	0	0
T33	0	259	0	0
T34	0	58	0	0
T35	897	200	0	0
T37	17506	0	0	0
T50	0	18	0	0
T52	803	0	0	0
T59	498	0	0	0
T64	522	0	0	0
T86	0	54	0	0
T150	0	45	0	0
T163	429	0	0	0
T167	0	224	0	0
T185	0	78	0	0
T186	440	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5736330	0	0
T1	353536	346575	0	0
T2	599	198	0	0
T3	3608	1604	0	0
T4	522	121	0	0
T5	18447	18015	0	0
T12	15235	14795	0	0
T13	421	20	0	0
T14	403	2	0	0
T15	494	93	0	0
T16	494	93	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	4	0	0
T22	624	0	0	0
T35	897	1	0	0
T37	17506	0	0	0
T38	5115	0	0	0
T59	498	0	0	0
T64	522	0	0	0
T65	527	0	0	0
T82	0	1	0	0
T155	0	1	0	0
T178	0	1	0	0
T186	440	0	0	0
T187	403	0	0	0
T188	443	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	4702	0	0
T11	646	80	0	0
T31	96676	0	0	0
T32	2567	401	0	0
T33	0	197	0	0
T34	0	43	0	0
T35	897	42	0	0
T37	17506	0	0	0
T50	0	8	0	0
T52	803	0	0	0
T59	498	0	0	0
T64	522	0	0	0
T86	0	115	0	0
T150	0	115	0	0
T163	429	0	0	0
T167	0	195	0	0
T185	0	57	0	0
T186	440	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	62	0	0
T11	646	1	0	0
T31	96676	0	0	0
T32	2567	3	0	0
T33	0	4	0	0
T34	0	1	0	0
T35	897	1	0	0
T37	17506	0	0	0
T50	0	1	0	0
T52	803	0	0	0
T59	498	0	0	0
T64	522	0	0	0
T86	0	2	0	0
T150	0	1	0	0
T163	429	0	0	0
T167	0	4	0	0
T185	0	1	0	0
T186	440	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5716053	0	0
T1	353536	346575	0	0
T2	599	198	0	0
T3	3608	1604	0	0
T4	522	121	0	0
T5	18447	18015	0	0
T12	15235	14795	0	0
T13	421	20	0	0
T14	403	2	0	0
T15	494	93	0	0
T16	494	93	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5718477	0	0
T1	353536	346596	0	0
T2	599	199	0	0
T3	3608	1608	0	0
T4	522	122	0	0
T5	18447	18020	0	0
T12	15235	14800	0	0
T13	421	21	0	0
T14	403	3	0	0
T15	494	94	0	0
T16	494	94	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	76	0	0
T11	646	2	0	0
T31	96676	0	0	0
T32	2567	3	0	0
T33	0	6	0	0
T34	0	1	0	0
T35	897	2	0	0
T37	17506	0	0	0
T50	0	1	0	0
T52	803	0	0	0
T59	498	0	0	0
T64	522	0	0	0
T86	0	2	0	0
T150	0	1	0	0
T163	429	0	0	0
T167	0	5	0	0
T185	0	1	0	0
T186	440	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	66	0	0
T11	646	1	0	0
T31	96676	0	0	0
T32	2567	3	0	0
T33	0	4	0	0
T34	0	1	0	0
T35	897	2	0	0
T37	17506	0	0	0
T50	0	1	0	0
T52	803	0	0	0
T59	498	0	0	0
T64	522	0	0	0
T86	0	2	0	0
T150	0	1	0	0
T163	429	0	0	0
T167	0	4	0	0
T185	0	1	0	0
T186	440	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	62	0	0
T11	646	1	0	0
T31	96676	0	0	0
T32	2567	3	0	0
T33	0	4	0	0
T34	0	1	0	0
T35	897	1	0	0
T37	17506	0	0	0
T50	0	1	0	0
T52	803	0	0	0
T59	498	0	0	0
T64	522	0	0	0
T86	0	2	0	0
T150	0	1	0	0
T163	429	0	0	0
T167	0	4	0	0
T185	0	1	0	0
T186	440	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	62	0	0
T11	646	1	0	0
T31	96676	0	0	0
T32	2567	3	0	0
T33	0	4	0	0
T34	0	1	0	0
T35	897	1	0	0
T37	17506	0	0	0
T50	0	1	0	0
T52	803	0	0	0
T59	498	0	0	0
T64	522	0	0	0
T86	0	2	0	0
T150	0	1	0	0
T163	429	0	0	0
T167	0	4	0	0
T185	0	1	0	0
T186	440	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	4612	0	0
T11	646	78	0	0
T31	96676	0	0	0
T32	2567	397	0	0
T33	0	191	0	0
T34	0	42	0	0
T35	897	40	0	0
T37	17506	0	0	0
T50	0	7	0	0
T52	803	0	0	0
T59	498	0	0	0
T64	522	0	0	0
T86	0	113	0	0
T150	0	114	0	0
T163	429	0	0	0
T167	0	188	0	0
T185	0	55	0	0
T186	440	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5738952	0	0
T1	353536	346596	0	0
T2	599	199	0	0
T3	3608	1608	0	0
T4	522	122	0	0
T5	18447	18020	0	0
T12	15235	14800	0	0
T13	421	21	0	0
T14	403	3	0	0
T15	494	94	0	0
T16	494	94	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	33	0	0
T32	2567	2	0	0
T33	0	2	0	0
T34	0	1	0	0
T35	897	0	0	0
T37	17506	0	0	0
T52	803	0	0	0
T59	498	0	0	0
T64	522	0	0	0
T65	527	0	0	0
T82	0	1	0	0
T86	0	2	0	0
T126	0	1	0	0
T150	0	1	0	0
T167	0	1	0	0
T178	0	1	0	0
T186	440	0	0	0
T187	403	0	0	0
T188	443	0	0	0
T205	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T12
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T12
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T10,T32

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T1,T10,T32

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T10,T32

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T10
1	0	Covered	T1,T4,T12
1	1	Covered	T1,T10,T32

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T10,T32
0	1	Covered	T206
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T10,T32
0	1	Covered	T10,T32,T149
1	0	Covered	T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T10,T32
1	-	Covered	T10,T32,T149

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T10,T32
DetectSt	168	Covered	T1,T10,T32
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T1,T10,T32

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T10,T32
DebounceSt->IdleSt	163	Covered	T77,T204,T207
DetectSt->IdleSt	186	Covered	T206
DetectSt->StableSt	191	Covered	T1,T10,T32
IdleSt->DebounceSt	148	Covered	T1,T10,T32
StableSt->IdleSt	206	Covered	T1,T10,T32

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T10,T32
0	1	Covered	T1,T10,T32
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T10,T32
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T10,T32
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T77
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T10,T32
DebounceSt	-	0	1	0	-	-	-	Covered	T207
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T10,T32
DetectSt	-	-	-	-	1	-	-	Covered	T206
DetectSt	-	-	-	-	0	1	-	Covered	T1,T10,T32
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T32,T149
StableSt	-	-	-	-	-	-	0	Covered	T1,T10,T32
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6431240	72	0	0
CntIncr_A	6431240	2166	0	0
CntNoWrap_A	6431240	5736400	0	0
DetectStDropOut_A	6431240	1	0	0
DetectedOut_A	6431240	2751	0	0
DetectedPulseOut_A	6431240	34	0	0
DisabledIdleSt_A	6431240	5658105	0	0
DisabledNoDetection_A	6431240	5660531	0	0
EnterDebounceSt_A	6431240	38	0	0
EnterDetectSt_A	6431240	35	0	0
EnterStableSt_A	6431240	34	0	0
PulseIsPulse_A	6431240	34	0	0
StayInStableSt	6431240	2699	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6431240	6468	0	0
gen_low_level_sva.LowLevelEvent_A	6431240	5738952	0	0
gen_not_sticky_sva.StableStDropOut_A	6431240	15	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	72	0	0
T1	353536	2	0	0
T2	599	0	0	0
T3	3608	0	0	0
T4	522	0	0	0
T5	18447	0	0	0
T10	0	2	0	0
T12	15235	0	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T32	0	2	0	0
T50	0	2	0	0
T82	0	4	0	0
T100	0	4	0	0
T136	0	2	0	0
T149	0	2	0	0
T166	0	2	0	0
T167	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	2166	0	0
T1	353536	92	0	0
T2	599	0	0	0
T3	3608	0	0	0
T4	522	0	0	0
T5	18447	0	0	0
T10	0	35	0	0
T12	15235	0	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T32	0	68	0	0
T50	0	18	0	0
T82	0	200	0	0
T100	0	139	0	0
T136	0	88	0	0
T149	0	37	0	0
T166	0	86	0	0
T167	0	32	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5736400	0	0
T1	353536	346573	0	0
T2	599	198	0	0
T3	3608	1604	0	0
T4	522	121	0	0
T5	18447	18015	0	0
T12	15235	14795	0	0
T13	421	20	0	0
T14	403	2	0	0
T15	494	93	0	0
T16	494	93	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	1	0	0
T206	252509	1	0	0
T218	423	0	0	0
T219	402	0	0	0
T220	493	0	0	0
T221	512	0	0	0
T222	568	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	2751	0	0
T1	353536	40	0	0
T2	599	0	0	0
T3	3608	0	0	0
T4	522	0	0	0
T5	18447	0	0	0
T10	0	17	0	0
T12	15235	0	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T32	0	26	0	0
T50	0	8	0	0
T82	0	371	0	0
T100	0	348	0	0
T136	0	113	0	0
T149	0	28	0	0
T166	0	62	0	0
T167	0	41	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	34	0	0
T1	353536	1	0	0
T2	599	0	0	0
T3	3608	0	0	0
T4	522	0	0	0
T5	18447	0	0	0
T10	0	1	0	0
T12	15235	0	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T32	0	1	0	0
T50	0	1	0	0
T82	0	2	0	0
T100	0	2	0	0
T136	0	1	0	0
T149	0	1	0	0
T166	0	1	0	0
T167	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5658105	0	0
T1	353536	346345	0	0
T2	599	198	0	0
T3	3608	1604	0	0
T4	522	121	0	0
T5	18447	18015	0	0
T12	15235	14795	0	0
T13	421	20	0	0
T14	403	2	0	0
T15	494	93	0	0
T16	494	93	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5660531	0	0
T1	353536	346365	0	0
T2	599	199	0	0
T3	3608	1608	0	0
T4	522	122	0	0
T5	18447	18020	0	0
T12	15235	14800	0	0
T13	421	21	0	0
T14	403	3	0	0
T15	494	94	0	0
T16	494	94	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	38	0	0
T1	353536	1	0	0
T2	599	0	0	0
T3	3608	0	0	0
T4	522	0	0	0
T5	18447	0	0	0
T10	0	1	0	0
T12	15235	0	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T32	0	1	0	0
T50	0	1	0	0
T82	0	2	0	0
T100	0	2	0	0
T136	0	1	0	0
T149	0	1	0	0
T166	0	1	0	0
T167	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	35	0	0
T1	353536	1	0	0
T2	599	0	0	0
T3	3608	0	0	0
T4	522	0	0	0
T5	18447	0	0	0
T10	0	1	0	0
T12	15235	0	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T32	0	1	0	0
T50	0	1	0	0
T82	0	2	0	0
T100	0	2	0	0
T136	0	1	0	0
T149	0	1	0	0
T166	0	1	0	0
T167	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	34	0	0
T1	353536	1	0	0
T2	599	0	0	0
T3	3608	0	0	0
T4	522	0	0	0
T5	18447	0	0	0
T10	0	1	0	0
T12	15235	0	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T32	0	1	0	0
T50	0	1	0	0
T82	0	2	0	0
T100	0	2	0	0
T136	0	1	0	0
T149	0	1	0	0
T166	0	1	0	0
T167	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	34	0	0
T1	353536	1	0	0
T2	599	0	0	0
T3	3608	0	0	0
T4	522	0	0	0
T5	18447	0	0	0
T10	0	1	0	0
T12	15235	0	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T32	0	1	0	0
T50	0	1	0	0
T82	0	2	0	0
T100	0	2	0	0
T136	0	1	0	0
T149	0	1	0	0
T166	0	1	0	0
T167	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	2699	0	0
T1	353536	38	0	0
T2	599	0	0	0
T3	3608	0	0	0
T4	522	0	0	0
T5	18447	0	0	0
T10	0	16	0	0
T12	15235	0	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T32	0	25	0	0
T50	0	7	0	0
T82	0	368	0	0
T100	0	344	0	0
T136	0	111	0	0
T149	0	27	0	0
T166	0	60	0	0
T167	0	40	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	6468	0	0
T1	353536	22	0	0
T2	599	0	0	0
T3	3608	1	0	0
T4	522	4	0	0
T5	18447	29	0	0
T12	15235	36	0	0
T13	421	3	0	0
T14	403	0	0	0
T15	494	4	0	0
T16	494	7	0	0
T21	0	8	0	0
T48	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5738952	0	0
T1	353536	346596	0	0
T2	599	199	0	0
T3	3608	1608	0	0
T4	522	122	0	0
T5	18447	18020	0	0
T12	15235	14800	0	0
T13	421	21	0	0
T14	403	3	0	0
T15	494	94	0	0
T16	494	94	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	15	0	0
T10	665	1	0	0
T11	646	0	0	0
T31	96676	0	0	0
T32	2567	1	0	0
T35	897	0	0	0
T52	803	0	0	0
T58	491	0	0	0
T82	0	1	0	0
T91	424	0	0	0
T108	425	0	0	0
T149	0	1	0	0
T159	0	1	0	0
T163	429	0	0	0
T167	0	1	0	0
T178	0	1	0	0
T189	0	1	0	0
T199	0	1	0	0
T223	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T4,T12

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T4,T12
1	1	Covered	T1,T4,T12

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T6,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T1,T6,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T6,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T11
1	0	Covered	T1,T4,T12
1	1	Covered	T1,T6,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T11
0	1	Covered	T127
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T11,T36
0	1	Covered	T6,T36,T33
1	0	Covered	T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T11,T36
1	-	Covered	T6,T36,T33

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T6,T11
DetectSt	168	Covered	T1,T6,T11
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T1,T6,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T6,T11
DebounceSt->IdleSt	163	Covered	T167,T202,T164
DetectSt->IdleSt	186	Covered	T127
DetectSt->StableSt	191	Covered	T1,T6,T11
IdleSt->DebounceSt	148	Covered	T1,T6,T11
StableSt->IdleSt	206	Covered	T1,T6,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T6,T11
0	1	Covered	T1,T6,T11
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T11
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T6,T11
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T12
DebounceSt	-	1	-	-	-	-	-	Covered	T77
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T6,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T167,T202,T164
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T6,T11
DetectSt	-	-	-	-	1	-	-	Covered	T127
DetectSt	-	-	-	-	0	1	-	Covered	T1,T6,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T6,T36,T33
StableSt	-	-	-	-	-	-	0	Covered	T1,T11,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6431240	124	0	0
CntIncr_A	6431240	57231	0	0
CntNoWrap_A	6431240	5736348	0	0
DetectStDropOut_A	6431240	1	0	0
DetectedOut_A	6431240	6302	0	0
DetectedPulseOut_A	6431240	58	0	0
DisabledIdleSt_A	6431240	5589851	0	0
DisabledNoDetection_A	6431240	5592278	0	0
EnterDebounceSt_A	6431240	65	0	0
EnterDetectSt_A	6431240	59	0	0
EnterStableSt_A	6431240	58	0	0
PulseIsPulse_A	6431240	58	0	0
StayInStableSt	6431240	6221	0	0
gen_high_level_sva.HighLevelEvent_A	6431240	5738952	0	0
gen_not_sticky_sva.StableStDropOut_A	6431240	34	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	124	0	0
T1	353536	2	0	0
T2	599	0	0	0
T3	3608	0	0	0
T4	522	0	0	0
T5	18447	0	0	0
T6	0	2	0	0
T11	0	2	0	0
T12	15235	0	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T33	0	4	0	0
T36	0	2	0	0
T57	0	2	0	0
T136	0	4	0	0
T149	0	4	0	0
T166	0	2	0	0
T182	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	57231	0	0
T1	353536	92	0	0
T2	599	0	0	0
T3	3608	0	0	0
T4	522	0	0	0
T5	18447	0	0	0
T6	0	15	0	0
T11	0	41	0	0
T12	15235	0	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T33	0	123	0	0
T36	0	54	0	0
T57	0	87	0	0
T136	0	176	0	0
T149	0	74	0	0
T166	0	86	0	0
T182	0	74	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5736348	0	0
T1	353536	346573	0	0
T2	599	198	0	0
T3	3608	1604	0	0
T4	522	121	0	0
T5	18447	18015	0	0
T12	15235	14795	0	0
T13	421	20	0	0
T14	403	2	0	0
T15	494	93	0	0
T16	494	93	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	1	0	0
T127	52139	1	0	0
T224	682	0	0	0
T225	426	0	0	0
T226	807	0	0	0
T227	3521	0	0	0
T228	527	0	0	0
T229	10418	0	0	0
T230	422	0	0	0
T231	632	0	0	0
T232	674	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	6302	0	0
T1	353536	134	0	0
T2	599	0	0	0
T3	3608	0	0	0
T4	522	0	0	0
T5	18447	0	0	0
T6	0	1	0	0
T11	0	165	0	0
T12	15235	0	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T33	0	169	0	0
T36	0	95	0	0
T57	0	188	0	0
T136	0	127	0	0
T149	0	147	0	0
T166	0	61	0	0
T182	0	65	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	58	0	0
T1	353536	1	0	0
T2	599	0	0	0
T3	3608	0	0	0
T4	522	0	0	0
T5	18447	0	0	0
T6	0	1	0	0
T11	0	1	0	0
T12	15235	0	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T33	0	2	0	0
T36	0	1	0	0
T57	0	1	0	0
T136	0	2	0	0
T149	0	2	0	0
T166	0	1	0	0
T182	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5589851	0	0
T1	353536	346345	0	0
T2	599	198	0	0
T3	3608	1604	0	0
T4	522	121	0	0
T5	18447	18015	0	0
T12	15235	14795	0	0
T13	421	20	0	0
T14	403	2	0	0
T15	494	93	0	0
T16	494	93	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5592278	0	0
T1	353536	346365	0	0
T2	599	199	0	0
T3	3608	1608	0	0
T4	522	122	0	0
T5	18447	18020	0	0
T12	15235	14800	0	0
T13	421	21	0	0
T14	403	3	0	0
T15	494	94	0	0
T16	494	94	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	65	0	0
T1	353536	1	0	0
T2	599	0	0	0
T3	3608	0	0	0
T4	522	0	0	0
T5	18447	0	0	0
T6	0	1	0	0
T11	0	1	0	0
T12	15235	0	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T33	0	2	0	0
T36	0	1	0	0
T57	0	1	0	0
T136	0	2	0	0
T149	0	2	0	0
T166	0	1	0	0
T182	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	59	0	0
T1	353536	1	0	0
T2	599	0	0	0
T3	3608	0	0	0
T4	522	0	0	0
T5	18447	0	0	0
T6	0	1	0	0
T11	0	1	0	0
T12	15235	0	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T33	0	2	0	0
T36	0	1	0	0
T57	0	1	0	0
T136	0	2	0	0
T149	0	2	0	0
T166	0	1	0	0
T182	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	58	0	0
T1	353536	1	0	0
T2	599	0	0	0
T3	3608	0	0	0
T4	522	0	0	0
T5	18447	0	0	0
T6	0	1	0	0
T11	0	1	0	0
T12	15235	0	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T33	0	2	0	0
T36	0	1	0	0
T57	0	1	0	0
T136	0	2	0	0
T149	0	2	0	0
T166	0	1	0	0
T182	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	58	0	0
T1	353536	1	0	0
T2	599	0	0	0
T3	3608	0	0	0
T4	522	0	0	0
T5	18447	0	0	0
T6	0	1	0	0
T11	0	1	0	0
T12	15235	0	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T33	0	2	0	0
T36	0	1	0	0
T57	0	1	0	0
T136	0	2	0	0
T149	0	2	0	0
T166	0	1	0	0
T182	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	6221	0	0
T1	353536	132	0	0
T2	599	0	0	0
T3	3608	0	0	0
T4	522	0	0	0
T5	18447	0	0	0
T11	0	163	0	0
T12	15235	0	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T33	0	166	0	0
T36	0	94	0	0
T57	0	187	0	0
T86	0	70	0	0
T136	0	124	0	0
T149	0	144	0	0
T166	0	59	0	0
T182	0	62	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5738952	0	0
T1	353536	346596	0	0
T2	599	199	0	0
T3	3608	1608	0	0
T4	522	122	0	0
T5	18447	18020	0	0
T12	15235	14800	0	0
T13	421	21	0	0
T14	403	3	0	0
T15	494	94	0	0
T16	494	94	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	34	0	0
T6	566	1	0	0
T7	15844	0	0	0
T8	13312	0	0	0
T9	838	0	0	0
T10	665	0	0	0
T21	494	0	0	0
T23	4517	0	0	0
T33	0	1	0	0
T36	0	1	0	0
T49	526	0	0	0
T57	0	1	0	0
T82	0	2	0	0
T86	0	2	0	0
T90	8402	0	0	0
T91	424	0	0	0
T136	0	1	0	0
T149	0	1	0	0
T167	0	1	0	0
T182	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T12
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T12
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T6,T10,T32

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T6,T10,T32

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T6,T10,T32

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T10
1	0	Covered	T1,T4,T12
1	1	Covered	T6,T10,T32

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T10,T32
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T10,T32
0	1	Covered	T10,T32,T136
1	0	Covered	T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T10,T32
1	-	Covered	T10,T32,T136

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T10,T32
DetectSt	168	Covered	T6,T10,T32
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T6,T10,T32

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T10,T32
DebounceSt->IdleSt	163	Covered	T77
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T6,T10,T32
IdleSt->DebounceSt	148	Covered	T6,T10,T32
StableSt->IdleSt	206	Covered	T10,T32,T33

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T10,T32
0	1	Covered	T6,T10,T32
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T10,T32
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T10,T32
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T77
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T10,T32
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T10,T32
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T6,T10,T32
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T32,T136
StableSt	-	-	-	-	-	-	0	Covered	T6,T10,T32
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6431240	81	0	0
CntIncr_A	6431240	2456	0	0
CntNoWrap_A	6431240	5736391	0	0
DetectStDropOut_A	6431240	0	0	0
DetectedOut_A	6431240	2936	0	0
DetectedPulseOut_A	6431240	40	0	0
DisabledIdleSt_A	6431240	5716371	0	0
DisabledNoDetection_A	6431240	5718800	0	0
EnterDebounceSt_A	6431240	41	0	0
EnterDetectSt_A	6431240	40	0	0
EnterStableSt_A	6431240	40	0	0
PulseIsPulse_A	6431240	40	0	0
StayInStableSt	6431240	2876	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6431240	6478	0	0
gen_low_level_sva.LowLevelEvent_A	6431240	5738952	0	0
gen_not_sticky_sva.StableStDropOut_A	6431240	19	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	81	0	0
T6	566	2	0	0
T7	15844	0	0	0
T8	13312	0	0	0
T9	838	0	0	0
T10	665	2	0	0
T21	494	0	0	0
T23	4517	0	0	0
T32	0	2	0	0
T33	0	2	0	0
T49	526	0	0	0
T57	0	2	0	0
T86	0	6	0	0
T90	8402	0	0	0
T91	424	0	0	0
T135	0	2	0	0
T136	0	2	0	0
T149	0	2	0	0
T183	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	2456	0	0
T6	566	15	0	0
T7	15844	0	0	0
T8	13312	0	0	0
T9	838	0	0	0
T10	665	35	0	0
T21	494	0	0	0
T23	4517	0	0	0
T32	0	15	0	0
T33	0	28	0	0
T49	526	0	0	0
T57	0	87	0	0
T86	0	171	0	0
T90	8402	0	0	0
T91	424	0	0	0
T135	0	95	0	0
T136	0	88	0	0
T149	0	37	0	0
T183	0	79	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5736391	0	0
T1	353536	346575	0	0
T2	599	198	0	0
T3	3608	1604	0	0
T4	522	121	0	0
T5	18447	18015	0	0
T12	15235	14795	0	0
T13	421	20	0	0
T14	403	2	0	0
T15	494	93	0	0
T16	494	93	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	2936	0	0
T6	566	38	0	0
T7	15844	0	0	0
T8	13312	0	0	0
T9	838	0	0	0
T10	665	15	0	0
T21	494	0	0	0
T23	4517	0	0	0
T32	0	69	0	0
T33	0	41	0	0
T49	526	0	0	0
T57	0	51	0	0
T86	0	164	0	0
T90	8402	0	0	0
T91	424	0	0	0
T135	0	40	0	0
T136	0	43	0	0
T149	0	11	0	0
T183	0	44	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	40	0	0
T6	566	1	0	0
T7	15844	0	0	0
T8	13312	0	0	0
T9	838	0	0	0
T10	665	1	0	0
T21	494	0	0	0
T23	4517	0	0	0
T32	0	1	0	0
T33	0	1	0	0
T49	526	0	0	0
T57	0	1	0	0
T86	0	3	0	0
T90	8402	0	0	0
T91	424	0	0	0
T135	0	1	0	0
T136	0	1	0	0
T149	0	1	0	0
T183	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5716371	0	0
T1	353536	346345	0	0
T2	599	198	0	0
T3	3608	1604	0	0
T4	522	121	0	0
T5	18447	18015	0	0
T12	15235	14795	0	0
T13	421	20	0	0
T14	403	2	0	0
T15	494	93	0	0
T16	494	93	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5718800	0	0
T1	353536	346365	0	0
T2	599	199	0	0
T3	3608	1608	0	0
T4	522	122	0	0
T5	18447	18020	0	0
T12	15235	14800	0	0
T13	421	21	0	0
T14	403	3	0	0
T15	494	94	0	0
T16	494	94	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	41	0	0
T6	566	1	0	0
T7	15844	0	0	0
T8	13312	0	0	0
T9	838	0	0	0
T10	665	1	0	0
T21	494	0	0	0
T23	4517	0	0	0
T32	0	1	0	0
T33	0	1	0	0
T49	526	0	0	0
T57	0	1	0	0
T86	0	3	0	0
T90	8402	0	0	0
T91	424	0	0	0
T135	0	1	0	0
T136	0	1	0	0
T149	0	1	0	0
T183	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	40	0	0
T6	566	1	0	0
T7	15844	0	0	0
T8	13312	0	0	0
T9	838	0	0	0
T10	665	1	0	0
T21	494	0	0	0
T23	4517	0	0	0
T32	0	1	0	0
T33	0	1	0	0
T49	526	0	0	0
T57	0	1	0	0
T86	0	3	0	0
T90	8402	0	0	0
T91	424	0	0	0
T135	0	1	0	0
T136	0	1	0	0
T149	0	1	0	0
T183	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	40	0	0
T6	566	1	0	0
T7	15844	0	0	0
T8	13312	0	0	0
T9	838	0	0	0
T10	665	1	0	0
T21	494	0	0	0
T23	4517	0	0	0
T32	0	1	0	0
T33	0	1	0	0
T49	526	0	0	0
T57	0	1	0	0
T86	0	3	0	0
T90	8402	0	0	0
T91	424	0	0	0
T135	0	1	0	0
T136	0	1	0	0
T149	0	1	0	0
T183	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	40	0	0
T6	566	1	0	0
T7	15844	0	0	0
T8	13312	0	0	0
T9	838	0	0	0
T10	665	1	0	0
T21	494	0	0	0
T23	4517	0	0	0
T32	0	1	0	0
T33	0	1	0	0
T49	526	0	0	0
T57	0	1	0	0
T86	0	3	0	0
T90	8402	0	0	0
T91	424	0	0	0
T135	0	1	0	0
T136	0	1	0	0
T149	0	1	0	0
T183	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	2876	0	0
T6	566	36	0	0
T7	15844	0	0	0
T8	13312	0	0	0
T9	838	0	0	0
T10	665	14	0	0
T21	494	0	0	0
T23	4517	0	0	0
T32	0	68	0	0
T33	0	39	0	0
T49	526	0	0	0
T57	0	49	0	0
T86	0	160	0	0
T90	8402	0	0	0
T91	424	0	0	0
T135	0	38	0	0
T136	0	42	0	0
T149	0	10	0	0
T183	0	42	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	6478	0	0
T1	353536	20	0	0
T2	599	0	0	0
T3	3608	5	0	0
T4	522	4	0	0
T5	18447	23	0	0
T6	0	1	0	0
T12	15235	32	0	0
T13	421	1	0	0
T14	403	0	0	0
T15	494	8	0	0
T16	494	7	0	0
T48	0	7	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5738952	0	0
T1	353536	346596	0	0
T2	599	199	0	0
T3	3608	1608	0	0
T4	522	122	0	0
T5	18447	18020	0	0
T12	15235	14800	0	0
T13	421	21	0	0
T14	403	3	0	0
T15	494	94	0	0
T16	494	94	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	19	0	0
T10	665	1	0	0
T11	646	0	0	0
T31	96676	0	0	0
T32	2567	1	0	0
T35	897	0	0	0
T52	803	0	0	0
T58	491	0	0	0
T82	0	1	0	0
T86	0	2	0	0
T91	424	0	0	0
T100	0	1	0	0
T108	425	0	0	0
T136	0	1	0	0
T149	0	1	0	0
T163	429	0	0	0
T165	0	2	0	0
T177	0	2	0	0
T233	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T9,T32

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T1,T9,T32

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T9,T32

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T9,T11
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T9,T32

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T9,T32
0	1	Covered	T161
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T9,T32
0	1	Covered	T9,T32,T33
1	0	Covered	T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T9,T32
1	-	Covered	T9,T32,T33

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T9,T32
DetectSt	168	Covered	T1,T9,T32
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T1,T9,T32

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T9,T32
DebounceSt->IdleSt	163	Covered	T57,T167,T83
DetectSt->IdleSt	186	Covered	T161
DetectSt->StableSt	191	Covered	T1,T9,T32
IdleSt->DebounceSt	148	Covered	T1,T9,T32
StableSt->IdleSt	206	Covered	T1,T9,T32

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T9,T32
0	1	Covered	T1,T9,T32
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T9,T32
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T9,T32
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T77
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T9,T32
DebounceSt	-	0	1	0	-	-	-	Covered	T57,T167,T83
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T9,T32
DetectSt	-	-	-	-	1	-	-	Covered	T161
DetectSt	-	-	-	-	0	1	-	Covered	T1,T9,T32
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T32,T33
StableSt	-	-	-	-	-	-	0	Covered	T1,T9,T32
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6431240	128	0	0
CntIncr_A	6431240	29602	0	0
CntNoWrap_A	6431240	5736344	0	0
DetectStDropOut_A	6431240	1	0	0
DetectedOut_A	6431240	6440	0	0
DetectedPulseOut_A	6431240	60	0	0
DisabledIdleSt_A	6431240	5646498	0	0
DisabledNoDetection_A	6431240	5648920	0	0
EnterDebounceSt_A	6431240	67	0	0
EnterDetectSt_A	6431240	61	0	0
EnterStableSt_A	6431240	60	0	0
PulseIsPulse_A	6431240	60	0	0
StayInStableSt	6431240	6349	0	0
gen_high_level_sva.HighLevelEvent_A	6431240	5738952	0	0
gen_not_sticky_sva.StableStDropOut_A	6431240	28	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	128	0	0
T1	353536	2	0	0
T2	599	0	0	0
T3	3608	0	0	0
T4	522	0	0	0
T5	18447	0	0	0
T9	0	4	0	0
T12	15235	0	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T32	0	4	0	0
T33	0	8	0	0
T34	0	2	0	0
T57	0	3	0	0
T136	0	4	0	0
T150	0	2	0	0
T182	0	2	0	0
T185	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	29602	0	0
T1	353536	92	0	0
T2	599	0	0	0
T3	3608	0	0	0
T4	522	0	0	0
T5	18447	0	0	0
T9	0	164	0	0
T12	15235	0	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T32	0	136	0	0
T33	0	195	0	0
T34	0	58	0	0
T57	0	174	0	0
T136	0	176	0	0
T150	0	45	0	0
T182	0	37	0	0
T185	0	78	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5736344	0	0
T1	353536	346573	0	0
T2	599	198	0	0
T3	3608	1604	0	0
T4	522	121	0	0
T5	18447	18015	0	0
T12	15235	14795	0	0
T13	421	20	0	0
T14	403	2	0	0
T15	494	93	0	0
T16	494	93	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	1	0	0
T161	11477	1	0	0
T234	426	0	0	0
T235	455	0	0	0
T236	502	0	0	0
T237	20477	0	0	0
T238	4971	0	0	0
T239	128703	0	0	0
T240	10611	0	0	0
T241	9036	0	0	0
T242	679	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	6440	0	0
T1	353536	134	0	0
T2	599	0	0	0
T3	3608	0	0	0
T4	522	0	0	0
T5	18447	0	0	0
T9	0	168	0	0
T12	15235	0	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T32	0	179	0	0
T33	0	162	0	0
T34	0	212	0	0
T57	0	172	0	0
T136	0	85	0	0
T150	0	42	0	0
T182	0	225	0	0
T185	0	41	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	60	0	0
T1	353536	1	0	0
T2	599	0	0	0
T3	3608	0	0	0
T4	522	0	0	0
T5	18447	0	0	0
T9	0	2	0	0
T12	15235	0	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T32	0	2	0	0
T33	0	4	0	0
T34	0	1	0	0
T57	0	1	0	0
T136	0	2	0	0
T150	0	1	0	0
T182	0	1	0	0
T185	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5646498	0	0
T1	353536	346345	0	0
T2	599	198	0	0
T3	3608	1604	0	0
T4	522	121	0	0
T5	18447	18015	0	0
T12	15235	14795	0	0
T13	421	20	0	0
T14	403	2	0	0
T15	494	93	0	0
T16	494	93	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5648920	0	0
T1	353536	346365	0	0
T2	599	199	0	0
T3	3608	1608	0	0
T4	522	122	0	0
T5	18447	18020	0	0
T12	15235	14800	0	0
T13	421	21	0	0
T14	403	3	0	0
T15	494	94	0	0
T16	494	94	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	67	0	0
T1	353536	1	0	0
T2	599	0	0	0
T3	3608	0	0	0
T4	522	0	0	0
T5	18447	0	0	0
T9	0	2	0	0
T12	15235	0	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T32	0	2	0	0
T33	0	4	0	0
T34	0	1	0	0
T57	0	2	0	0
T136	0	2	0	0
T150	0	1	0	0
T182	0	1	0	0
T185	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	61	0	0
T1	353536	1	0	0
T2	599	0	0	0
T3	3608	0	0	0
T4	522	0	0	0
T5	18447	0	0	0
T9	0	2	0	0
T12	15235	0	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T32	0	2	0	0
T33	0	4	0	0
T34	0	1	0	0
T57	0	1	0	0
T136	0	2	0	0
T150	0	1	0	0
T182	0	1	0	0
T185	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	60	0	0
T1	353536	1	0	0
T2	599	0	0	0
T3	3608	0	0	0
T4	522	0	0	0
T5	18447	0	0	0
T9	0	2	0	0
T12	15235	0	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T32	0	2	0	0
T33	0	4	0	0
T34	0	1	0	0
T57	0	1	0	0
T136	0	2	0	0
T150	0	1	0	0
T182	0	1	0	0
T185	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	60	0	0
T1	353536	1	0	0
T2	599	0	0	0
T3	3608	0	0	0
T4	522	0	0	0
T5	18447	0	0	0
T9	0	2	0	0
T12	15235	0	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T32	0	2	0	0
T33	0	4	0	0
T34	0	1	0	0
T57	0	1	0	0
T136	0	2	0	0
T150	0	1	0	0
T182	0	1	0	0
T185	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	6349	0	0
T1	353536	132	0	0
T2	599	0	0	0
T3	3608	0	0	0
T4	522	0	0	0
T5	18447	0	0	0
T9	0	165	0	0
T12	15235	0	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T32	0	176	0	0
T33	0	157	0	0
T34	0	211	0	0
T57	0	170	0	0
T136	0	82	0	0
T150	0	41	0	0
T182	0	223	0	0
T185	0	39	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5738952	0	0
T1	353536	346596	0	0
T2	599	199	0	0
T3	3608	1608	0	0
T4	522	122	0	0
T5	18447	18020	0	0
T12	15235	14800	0	0
T13	421	21	0	0
T14	403	3	0	0
T15	494	94	0	0
T16	494	94	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	28	0	0
T9	838	1	0	0
T10	665	0	0	0
T11	646	0	0	0
T31	96676	0	0	0
T32	2567	1	0	0
T33	0	3	0	0
T34	0	1	0	0
T58	491	0	0	0
T86	0	1	0	0
T90	8402	0	0	0
T91	424	0	0	0
T108	425	0	0	0
T136	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T163	429	0	0	0
T178	0	1	0	0
T183	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T31,T32,T33

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T31,T32,T33

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T31,T32,T33

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T10,T11
1	0	Covered	T1,T2,T4
1	1	Covered	T31,T32,T33

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T31,T32,T33
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T31,T32,T33
0	1	Covered	T32,T33,T149
1	0	Covered	T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T31,T32,T33
1	-	Covered	T32,T33,T149

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T31,T32,T33
DetectSt	168	Covered	T31,T32,T33
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T31,T32,T33

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T31,T32,T33
DebounceSt->IdleSt	163	Covered	T136,T77,T204
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T31,T32,T33
IdleSt->DebounceSt	148	Covered	T31,T32,T33
StableSt->IdleSt	206	Covered	T32,T33,T149

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T31,T32,T33
0	1	Covered	T31,T32,T33
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T33
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T31,T32,T33
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T77
DebounceSt	-	0	1	1	-	-	-	Covered	T31,T32,T33
DebounceSt	-	0	1	0	-	-	-	Covered	T136
DebounceSt	-	0	0	-	-	-	-	Covered	T31,T32,T33
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T31,T32,T33
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T32,T33,T149
StableSt	-	-	-	-	-	-	0	Covered	T31,T32,T33
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6431240	86	0	0
CntIncr_A	6431240	58001	0	0
CntNoWrap_A	6431240	5736386	0	0
DetectStDropOut_A	6431240	0	0	0
DetectedOut_A	6431240	2166	0	0
DetectedPulseOut_A	6431240	42	0	0
DisabledIdleSt_A	6431240	5557896	0	0
DisabledNoDetection_A	6431240	5560314	0	0
EnterDebounceSt_A	6431240	45	0	0
EnterDetectSt_A	6431240	42	0	0
EnterStableSt_A	6431240	42	0	0
PulseIsPulse_A	6431240	42	0	0
StayInStableSt	6431240	2105	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6431240	7002	0	0
gen_low_level_sva.LowLevelEvent_A	6431240	5738952	0	0
gen_not_sticky_sva.StableStDropOut_A	6431240	22	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	86	0	0
T31	96676	2	0	0
T32	2567	6	0	0
T33	0	6	0	0
T35	897	0	0	0
T37	17506	0	0	0
T50	0	2	0	0
T52	803	0	0	0
T59	498	0	0	0
T64	522	0	0	0
T82	0	4	0	0
T136	0	1	0	0
T149	0	2	0	0
T150	0	2	0	0
T163	429	0	0	0
T167	0	2	0	0
T177	0	2	0	0
T186	440	0	0	0
T187	403	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	58001	0	0
T31	96676	41005	0	0
T32	2567	98	0	0
T33	0	159	0	0
T35	897	0	0	0
T37	17506	0	0	0
T50	0	18	0	0
T52	803	0	0	0
T59	498	0	0	0
T64	522	0	0	0
T82	0	200	0	0
T136	0	88	0	0
T149	0	37	0	0
T150	0	45	0	0
T163	429	0	0	0
T167	0	32	0	0
T177	0	78	0	0
T186	440	0	0	0
T187	403	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5736386	0	0
T1	353536	346575	0	0
T2	599	198	0	0
T3	3608	1604	0	0
T4	522	121	0	0
T5	18447	18015	0	0
T12	15235	14795	0	0
T13	421	20	0	0
T14	403	2	0	0
T15	494	93	0	0
T16	494	93	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	2166	0	0
T31	96676	41	0	0
T32	2567	139	0	0
T33	0	66	0	0
T35	897	0	0	0
T37	17506	0	0	0
T50	0	8	0	0
T52	803	0	0	0
T59	498	0	0	0
T64	522	0	0	0
T82	0	112	0	0
T83	0	38	0	0
T149	0	88	0	0
T150	0	114	0	0
T163	429	0	0	0
T167	0	44	0	0
T177	0	43	0	0
T186	440	0	0	0
T187	403	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	42	0	0
T31	96676	1	0	0
T32	2567	3	0	0
T33	0	3	0	0
T35	897	0	0	0
T37	17506	0	0	0
T50	0	1	0	0
T52	803	0	0	0
T59	498	0	0	0
T64	522	0	0	0
T82	0	2	0	0
T83	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T163	429	0	0	0
T167	0	1	0	0
T177	0	1	0	0
T186	440	0	0	0
T187	403	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5557896	0	0
T1	353536	346345	0	0
T2	599	198	0	0
T3	3608	1604	0	0
T4	522	121	0	0
T5	18447	18015	0	0
T12	15235	14795	0	0
T13	421	20	0	0
T14	403	2	0	0
T15	494	93	0	0
T16	494	93	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5560314	0	0
T1	353536	346365	0	0
T2	599	199	0	0
T3	3608	1608	0	0
T4	522	122	0	0
T5	18447	18020	0	0
T12	15235	14800	0	0
T13	421	21	0	0
T14	403	3	0	0
T15	494	94	0	0
T16	494	94	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	45	0	0
T31	96676	1	0	0
T32	2567	3	0	0
T33	0	3	0	0
T35	897	0	0	0
T37	17506	0	0	0
T50	0	1	0	0
T52	803	0	0	0
T59	498	0	0	0
T64	522	0	0	0
T82	0	2	0	0
T136	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T163	429	0	0	0
T167	0	1	0	0
T177	0	1	0	0
T186	440	0	0	0
T187	403	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	42	0	0
T31	96676	1	0	0
T32	2567	3	0	0
T33	0	3	0	0
T35	897	0	0	0
T37	17506	0	0	0
T50	0	1	0	0
T52	803	0	0	0
T59	498	0	0	0
T64	522	0	0	0
T82	0	2	0	0
T83	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T163	429	0	0	0
T167	0	1	0	0
T177	0	1	0	0
T186	440	0	0	0
T187	403	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	42	0	0
T31	96676	1	0	0
T32	2567	3	0	0
T33	0	3	0	0
T35	897	0	0	0
T37	17506	0	0	0
T50	0	1	0	0
T52	803	0	0	0
T59	498	0	0	0
T64	522	0	0	0
T82	0	2	0	0
T83	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T163	429	0	0	0
T167	0	1	0	0
T177	0	1	0	0
T186	440	0	0	0
T187	403	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	42	0	0
T31	96676	1	0	0
T32	2567	3	0	0
T33	0	3	0	0
T35	897	0	0	0
T37	17506	0	0	0
T50	0	1	0	0
T52	803	0	0	0
T59	498	0	0	0
T64	522	0	0	0
T82	0	2	0	0
T83	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T163	429	0	0	0
T167	0	1	0	0
T177	0	1	0	0
T186	440	0	0	0
T187	403	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	2105	0	0
T31	96676	39	0	0
T32	2567	135	0	0
T33	0	62	0	0
T35	897	0	0	0
T37	17506	0	0	0
T50	0	7	0	0
T52	803	0	0	0
T59	498	0	0	0
T64	522	0	0	0
T82	0	109	0	0
T83	0	36	0	0
T149	0	87	0	0
T150	0	112	0	0
T163	429	0	0	0
T167	0	42	0	0
T177	0	42	0	0
T186	440	0	0	0
T187	403	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	7002	0	0
T1	353536	34	0	0
T2	599	1	0	0
T3	3608	16	0	0
T4	522	5	0	0
T5	18447	24	0	0
T12	15235	30	0	0
T13	421	3	0	0
T14	403	0	0	0
T15	494	11	0	0
T16	494	10	0	0
T48	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5738952	0	0
T1	353536	346596	0	0
T2	599	199	0	0
T3	3608	1608	0	0
T4	522	122	0	0
T5	18447	18020	0	0
T12	15235	14800	0	0
T13	421	21	0	0
T14	403	3	0	0
T15	494	94	0	0
T16	494	94	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	22	0	0
T32	2567	2	0	0
T33	0	2	0	0
T35	897	0	0	0
T37	17506	0	0	0
T52	803	0	0	0
T59	498	0	0	0
T64	522	0	0	0
T65	527	0	0	0
T82	0	1	0	0
T126	0	1	0	0
T149	0	1	0	0
T164	0	1	0	0
T165	0	1	0	0
T177	0	1	0	0
T178	0	1	0	0
T186	440	0	0	0
T187	403	0	0	0
T188	443	0	0	0
T217	0	1	0	0