Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T12,T5,T23
1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T12,T5,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T12,T5,T23

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T12,T5,T23

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T5,T23
1	0	Covered	T12,T5,T37
1	1	Covered	T12,T5,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T5,T23
0	1	Covered	T38,T42,T69
1	0	Covered	T69,T50,T243

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T5,T23
0	1	Covered	T12,T5,T23
1	0	Covered	T77

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T5,T23
1	-	Covered	T12,T5,T23

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T12,T5,T23
DetectSt	168	Covered	T12,T5,T23
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T12,T5,T23

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T12,T5,T23
DebounceSt->IdleSt	163	Covered	T23,T44,T50
DetectSt->IdleSt	186	Covered	T38,T42,T69
DetectSt->StableSt	191	Covered	T12,T5,T23
IdleSt->DebounceSt	148	Covered	T12,T5,T23
StableSt->IdleSt	206	Covered	T12,T5,T23

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T12,T5,T23
0	1	Covered	T12,T5,T23
0	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T5,T23
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T12,T5,T23
IdleSt	0	-	-	-	-	-	-	Covered	T12,T5,T23
DebounceSt	-	1	-	-	-	-	-	Covered	T50,T77
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T5,T23
DebounceSt	-	0	1	0	-	-	-	Covered	T23,T44,T50
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T5,T23
DetectSt	-	-	-	-	1	-	-	Covered	T38,T42,T69
DetectSt	-	-	-	-	0	1	-	Covered	T12,T5,T23
DetectSt	-	-	-	-	0	0	-	Covered	T12,T5,T23
StableSt	-	-	-	-	-	-	1	Covered	T12,T5,T23
StableSt	-	-	-	-	-	-	0	Covered	T12,T5,T23
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6431240	2822	0	0
CntIncr_A	6431240	88636	0	0
CntNoWrap_A	6431240	5733650	0	0
DetectStDropOut_A	6431240	364	0	0
DetectedOut_A	6431240	65550	0	0
DetectedPulseOut_A	6431240	865	0	0
DisabledIdleSt_A	6431240	5315013	0	0
DisabledNoDetection_A	6431240	5317297	0	0
EnterDebounceSt_A	6431240	1429	0	0
EnterDetectSt_A	6431240	1395	0	0
EnterStableSt_A	6431240	865	0	0
PulseIsPulse_A	6431240	865	0	0
StayInStableSt	6431240	64580	0	0
gen_high_event_sva.HighLevelEvent_A	6431240	5738952	0	0
gen_high_level_sva.HighLevelEvent_A	6431240	5738952	0	0
gen_not_sticky_sva.StableStDropOut_A	6431240	759	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	2822	0	0
T3	3608	0	0	0
T5	18447	24	0	0
T6	566	0	0	0
T12	15235	58	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T23	0	19	0	0
T30	0	12	0	0
T37	0	8	0	0
T38	0	53	0	0
T42	0	22	0	0
T44	0	18	0	0
T48	451	0	0	0
T69	0	22	0	0
T70	0	52	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	88636	0	0
T3	3608	0	0	0
T5	18447	1056	0	0
T6	566	0	0	0
T12	15235	1160	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T23	0	681	0	0
T30	0	528	0	0
T37	0	320	0	0
T38	0	1355	0	0
T42	0	413	0	0
T44	0	810	0	0
T48	451	0	0	0
T69	0	661	0	0
T70	0	1352	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5733650	0	0
T1	353536	346575	0	0
T2	599	198	0	0
T3	3608	1604	0	0
T4	522	121	0	0
T5	18447	17991	0	0
T12	15235	14737	0	0
T13	421	20	0	0
T14	403	2	0	0
T15	494	93	0	0
T16	494	93	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	364	0	0
T36	722	0	0	0
T38	5115	26	0	0
T39	709	0	0	0
T40	50642	0	0	0
T41	2522	0	0	0
T42	0	11	0	0
T53	801	0	0	0
T69	0	3	0	0
T92	0	8	0	0
T93	0	7	0	0
T95	0	25	0	0
T97	0	6	0	0
T98	0	6	0	0
T99	0	3	0	0
T244	0	10	0	0
T245	402	0	0	0
T246	422	0	0	0
T247	402	0	0	0
T248	628	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	65550	0	0
T3	3608	0	0	0
T5	18447	742	0	0
T6	566	0	0	0
T12	15235	2142	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T23	0	141	0	0
T30	0	284	0	0
T37	0	205	0	0
T48	451	0	0	0
T70	0	1287	0	0
T88	0	1382	0	0
T118	0	1666	0	0
T249	0	830	0	0
T250	0	1665	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	865	0	0
T3	3608	0	0	0
T5	18447	12	0	0
T6	566	0	0	0
T12	15235	29	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T23	0	7	0	0
T30	0	6	0	0
T37	0	4	0	0
T48	451	0	0	0
T70	0	26	0	0
T88	0	11	0	0
T118	0	12	0	0
T249	0	10	0	0
T250	0	14	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5315013	0	0
T1	353536	346575	0	0
T2	599	198	0	0
T3	3608	1604	0	0
T4	522	121	0	0
T5	18447	11987	0	0
T12	15235	10072	0	0
T13	421	20	0	0
T14	403	2	0	0
T15	494	93	0	0
T16	494	93	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5317297	0	0
T1	353536	346596	0	0
T2	599	199	0	0
T3	3608	1608	0	0
T4	522	122	0	0
T5	18447	11990	0	0
T12	15235	10072	0	0
T13	421	21	0	0
T14	403	3	0	0
T15	494	94	0	0
T16	494	94	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	1429	0	0
T3	3608	0	0	0
T5	18447	12	0	0
T6	566	0	0	0
T12	15235	29	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T23	0	13	0	0
T30	0	6	0	0
T37	0	4	0	0
T38	0	27	0	0
T42	0	11	0	0
T44	0	18	0	0
T48	451	0	0	0
T69	0	11	0	0
T70	0	26	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	1395	0	0
T3	3608	0	0	0
T5	18447	12	0	0
T6	566	0	0	0
T12	15235	29	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T23	0	7	0	0
T30	0	6	0	0
T37	0	4	0	0
T38	0	27	0	0
T42	0	11	0	0
T48	451	0	0	0
T69	0	11	0	0
T70	0	26	0	0
T88	0	11	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	865	0	0
T3	3608	0	0	0
T5	18447	12	0	0
T6	566	0	0	0
T12	15235	29	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T23	0	7	0	0
T30	0	6	0	0
T37	0	4	0	0
T48	451	0	0	0
T70	0	26	0	0
T88	0	11	0	0
T118	0	12	0	0
T249	0	10	0	0
T250	0	14	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	865	0	0
T3	3608	0	0	0
T5	18447	12	0	0
T6	566	0	0	0
T12	15235	29	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T23	0	7	0	0
T30	0	6	0	0
T37	0	4	0	0
T48	451	0	0	0
T70	0	26	0	0
T88	0	11	0	0
T118	0	12	0	0
T249	0	10	0	0
T250	0	14	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	64580	0	0
T3	3608	0	0	0
T5	18447	729	0	0
T6	566	0	0	0
T12	15235	2109	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T23	0	134	0	0
T30	0	277	0	0
T37	0	200	0	0
T48	451	0	0	0
T70	0	1261	0	0
T88	0	1365	0	0
T118	0	1653	0	0
T249	0	818	0	0
T250	0	1647	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5738952	0	0
T1	353536	346596	0	0
T2	599	199	0	0
T3	3608	1608	0	0
T4	522	122	0	0
T5	18447	18020	0	0
T12	15235	14800	0	0
T13	421	21	0	0
T14	403	3	0	0
T15	494	94	0	0
T16	494	94	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5738952	0	0
T1	353536	346596	0	0
T2	599	199	0	0
T3	3608	1608	0	0
T4	522	122	0	0
T5	18447	18020	0	0
T12	15235	14800	0	0
T13	421	21	0	0
T14	403	3	0	0
T15	494	94	0	0
T16	494	94	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	759	0	0
T3	3608	0	0	0
T5	18447	11	0	0
T6	566	0	0	0
T12	15235	25	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T23	0	7	0	0
T30	0	5	0	0
T37	0	3	0	0
T48	451	0	0	0
T70	0	26	0	0
T88	0	5	0	0
T118	0	11	0	0
T249	0	8	0	0
T250	0	10	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T12,T5,T7
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T5,T7
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T12,T5,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T12,T5,T7

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T12,T5,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T5,T7
1	0	Covered	T1,T12,T3
1	1	Covered	T12,T5,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T5,T7
0	1	Covered	T7,T94,T96
1	0	Covered	T50,T77

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T5,T27
0	1	Covered	T5,T27,T67
1	0	Covered	T50,T77,T251

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T5,T27
1	-	Covered	T5,T27,T67

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T12,T5,T7
DetectSt	168	Covered	T12,T5,T7
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T12,T5,T27

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T12,T5,T7
DebounceSt->IdleSt	163	Covered	T27,T67,T28
DetectSt->IdleSt	186	Covered	T7,T94,T96
DetectSt->StableSt	191	Covered	T12,T5,T27
IdleSt->DebounceSt	148	Covered	T12,T5,T7
StableSt->IdleSt	206	Covered	T12,T5,T27

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T12,T5,T7
0	1	Covered	T12,T5,T7
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T5,T7
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T12,T5,T7
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T50,T77
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T5,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T27,T67,T28
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T5,T7
DetectSt	-	-	-	-	1	-	-	Covered	T7,T94,T96
DetectSt	-	-	-	-	0	1	-	Covered	T12,T5,T27
DetectSt	-	-	-	-	0	0	-	Covered	T12,T5,T7
StableSt	-	-	-	-	-	-	1	Covered	T5,T27,T67
StableSt	-	-	-	-	-	-	0	Covered	T12,T5,T27
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6431240	1070	0	0
CntIncr_A	6431240	50390	0	0
CntNoWrap_A	6431240	5735402	0	0
DetectStDropOut_A	6431240	75	0	0
DetectedOut_A	6431240	14392	0	0
DetectedPulseOut_A	6431240	413	0	0
DisabledIdleSt_A	6431240	5341171	0	0
DisabledNoDetection_A	6431240	5342815	0	0
EnterDebounceSt_A	6431240	578	0	0
EnterDetectSt_A	6431240	492	0	0
EnterStableSt_A	6431240	413	0	0
PulseIsPulse_A	6431240	413	0	0
StayInStableSt	6431240	13946	0	0
gen_high_level_sva.HighLevelEvent_A	6431240	5738952	0	0
gen_not_sticky_sva.StableStDropOut_A	6431240	375	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	1070	0	0
T3	3608	0	0	0
T5	18447	2	0	0
T6	566	0	0	0
T7	0	4	0	0
T12	15235	8	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T27	0	3	0	0
T28	0	11	0	0
T29	0	17	0	0
T48	451	0	0	0
T67	0	5	0	0
T87	0	10	0	0
T88	0	13	0	0
T89	0	30	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	50390	0	0
T3	3608	0	0	0
T5	18447	76	0	0
T6	566	0	0	0
T7	0	210	0	0
T12	15235	188	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T27	0	150	0	0
T28	0	653	0	0
T29	0	857	0	0
T48	451	0	0	0
T67	0	200	0	0
T87	0	495	0	0
T88	0	353	0	0
T89	0	2070	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5735402	0	0
T1	353536	346575	0	0
T2	599	198	0	0
T3	3608	1604	0	0
T4	522	121	0	0
T5	18447	18013	0	0
T12	15235	14787	0	0
T13	421	20	0	0
T14	403	2	0	0
T15	494	93	0	0
T16	494	93	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	75	0	0
T7	15844	2	0	0
T8	13312	0	0	0
T9	838	0	0	0
T10	665	0	0	0
T23	4517	0	0	0
T49	526	0	0	0
T58	491	0	0	0
T90	8402	0	0	0
T91	424	0	0	0
T94	0	3	0	0
T96	0	2	0	0
T100	0	1	0	0
T101	0	12	0	0
T102	0	7	0	0
T103	0	9	0	0
T104	0	11	0	0
T105	0	12	0	0
T106	0	1	0	0
T108	425	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	14392	0	0
T3	3608	0	0	0
T5	18447	88	0	0
T6	566	0	0	0
T12	15235	246	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T27	0	31	0	0
T28	0	67	0	0
T29	0	50	0	0
T48	451	0	0	0
T67	0	83	0	0
T87	0	286	0	0
T88	0	143	0	0
T89	0	336	0	0
T118	0	63	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	413	0	0
T3	3608	0	0	0
T5	18447	1	0	0
T6	566	0	0	0
T12	15235	4	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T27	0	1	0	0
T28	0	5	0	0
T29	0	8	0	0
T48	451	0	0	0
T67	0	2	0	0
T87	0	5	0	0
T88	0	6	0	0
T89	0	13	0	0
T118	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5341171	0	0
T1	353536	346575	0	0
T2	599	198	0	0
T3	3608	1604	0	0
T4	522	121	0	0
T5	18447	17274	0	0
T12	15235	12657	0	0
T13	421	20	0	0
T14	403	2	0	0
T15	494	93	0	0
T16	494	93	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5342815	0	0
T1	353536	346596	0	0
T2	599	199	0	0
T3	3608	1608	0	0
T4	522	122	0	0
T5	18447	17278	0	0
T12	15235	12658	0	0
T13	421	21	0	0
T14	403	3	0	0
T15	494	94	0	0
T16	494	94	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	578	0	0
T3	3608	0	0	0
T5	18447	1	0	0
T6	566	0	0	0
T7	0	2	0	0
T12	15235	4	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T27	0	2	0	0
T28	0	6	0	0
T29	0	9	0	0
T48	451	0	0	0
T67	0	3	0	0
T87	0	5	0	0
T88	0	7	0	0
T89	0	17	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	492	0	0
T3	3608	0	0	0
T5	18447	1	0	0
T6	566	0	0	0
T7	0	2	0	0
T12	15235	4	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T27	0	1	0	0
T28	0	5	0	0
T29	0	8	0	0
T48	451	0	0	0
T67	0	2	0	0
T87	0	5	0	0
T88	0	6	0	0
T89	0	13	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	413	0	0
T3	3608	0	0	0
T5	18447	1	0	0
T6	566	0	0	0
T12	15235	4	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T27	0	1	0	0
T28	0	5	0	0
T29	0	8	0	0
T48	451	0	0	0
T67	0	2	0	0
T87	0	5	0	0
T88	0	6	0	0
T89	0	13	0	0
T118	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	413	0	0
T3	3608	0	0	0
T5	18447	1	0	0
T6	566	0	0	0
T12	15235	4	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T27	0	1	0	0
T28	0	5	0	0
T29	0	8	0	0
T48	451	0	0	0
T67	0	2	0	0
T87	0	5	0	0
T88	0	6	0	0
T89	0	13	0	0
T118	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	13946	0	0
T3	3608	0	0	0
T5	18447	87	0	0
T6	566	0	0	0
T12	15235	238	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T27	0	30	0	0
T28	0	62	0	0
T29	0	42	0	0
T48	451	0	0	0
T67	0	81	0	0
T87	0	281	0	0
T88	0	132	0	0
T89	0	323	0	0
T118	0	62	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5738952	0	0
T1	353536	346596	0	0
T2	599	199	0	0
T3	3608	1608	0	0
T4	522	122	0	0
T5	18447	18020	0	0
T12	15235	14800	0	0
T13	421	21	0	0
T14	403	3	0	0
T15	494	94	0	0
T16	494	94	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	375	0	0
T5	18447	1	0	0
T6	566	0	0	0
T7	15844	0	0	0
T8	13312	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T27	0	1	0	0
T28	0	5	0	0
T29	0	8	0	0
T48	451	0	0	0
T49	526	0	0	0
T67	0	2	0	0
T87	0	5	0	0
T88	0	1	0	0
T89	0	13	0	0
T118	0	1	0	0
T120	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T12,T5,T23
1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T12,T5,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T12,T5,T23

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T12,T5,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T5,T23
1	0	Covered	T12,T5,T37
1	1	Covered	T12,T5,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T5,T37
0	1	Covered	T12,T38,T42
1	0	Covered	T12,T70,T252

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T37,T30
0	1	Covered	T5,T37,T30
1	0	Covered	T81

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T37,T30
1	-	Covered	T5,T37,T30

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T12,T5,T23
DetectSt	168	Covered	T12,T5,T37
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T5,T37,T30

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T12,T5,T37
DebounceSt->IdleSt	163	Covered	T23,T44,T50
DetectSt->IdleSt	186	Covered	T12,T38,T42
DetectSt->StableSt	191	Covered	T5,T37,T30
IdleSt->DebounceSt	148	Covered	T12,T5,T23
StableSt->IdleSt	206	Covered	T5,T37,T30

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T12,T5,T23
0	1	Covered	T12,T5,T23
0	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T5,T37
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T12,T5,T23
IdleSt	0	-	-	-	-	-	-	Covered	T12,T5,T23
DebounceSt	-	1	-	-	-	-	-	Covered	T50,T77
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T5,T37
DebounceSt	-	0	1	0	-	-	-	Covered	T23,T44,T50
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T5,T23
DetectSt	-	-	-	-	1	-	-	Covered	T12,T38,T42
DetectSt	-	-	-	-	0	1	-	Covered	T5,T37,T30
DetectSt	-	-	-	-	0	0	-	Covered	T12,T5,T37
StableSt	-	-	-	-	-	-	1	Covered	T5,T37,T30
StableSt	-	-	-	-	-	-	0	Covered	T5,T37,T30
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6431240	2977	0	0
CntIncr_A	6431240	104024	0	0
CntNoWrap_A	6431240	5733495	0	0
DetectStDropOut_A	6431240	443	0	0
DetectedOut_A	6431240	71809	0	0
DetectedPulseOut_A	6431240	832	0	0
DisabledIdleSt_A	6431240	5311993	0	0
DisabledNoDetection_A	6431240	5314304	0	0
EnterDebounceSt_A	6431240	1509	0	0
EnterDetectSt_A	6431240	1469	0	0
EnterStableSt_A	6431240	832	0	0
PulseIsPulse_A	6431240	832	0	0
StayInStableSt	6431240	70898	0	0
gen_high_event_sva.HighLevelEvent_A	6431240	5738952	0	0
gen_high_level_sva.HighLevelEvent_A	6431240	5738952	0	0
gen_not_sticky_sva.StableStDropOut_A	6431240	751	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	2977	0	0
T3	3608	0	0	0
T5	18447	54	0	0
T6	566	0	0	0
T12	15235	28	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T23	0	3	0	0
T30	0	22	0	0
T37	0	48	0	0
T38	0	48	0	0
T42	0	14	0	0
T44	0	26	0	0
T48	451	0	0	0
T69	0	26	0	0
T70	0	28	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	104024	0	0
T3	3608	0	0	0
T5	18447	1539	0	0
T6	566	0	0	0
T12	15235	803	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T23	0	132	0	0
T30	0	605	0	0
T37	0	2040	0	0
T38	0	1202	0	0
T42	0	261	0	0
T44	0	1170	0	0
T48	451	0	0	0
T69	0	611	0	0
T70	0	861	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5733495	0	0
T1	353536	346575	0	0
T2	599	198	0	0
T3	3608	1604	0	0
T4	522	121	0	0
T5	18447	17961	0	0
T12	15235	14767	0	0
T13	421	20	0	0
T14	403	2	0	0
T15	494	93	0	0
T16	494	93	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	443	0	0
T3	3608	0	0	0
T5	18447	0	0	0
T6	566	0	0	0
T12	15235	5	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T38	0	24	0	0
T42	0	7	0	0
T48	451	0	0	0
T92	0	28	0	0
T93	0	1	0	0
T95	0	12	0	0
T97	0	21	0	0
T98	0	9	0	0
T99	0	5	0	0
T244	0	10	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	71809	0	0
T5	18447	2719	0	0
T6	566	0	0	0
T7	15844	0	0	0
T8	13312	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T30	0	1646	0	0
T37	0	1668	0	0
T48	451	0	0	0
T49	526	0	0	0
T69	0	323	0	0
T88	0	137	0	0
T118	0	1026	0	0
T130	0	6826	0	0
T249	0	1668	0	0
T250	0	1331	0	0
T253	0	66	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	832	0	0
T5	18447	27	0	0
T6	566	0	0	0
T7	15844	0	0	0
T8	13312	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T30	0	11	0	0
T37	0	24	0	0
T48	451	0	0	0
T49	526	0	0	0
T69	0	13	0	0
T88	0	3	0	0
T118	0	9	0	0
T130	0	33	0	0
T249	0	14	0	0
T250	0	12	0	0
T253	0	8	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5311993	0	0
T1	353536	346575	0	0
T2	599	198	0	0
T3	3608	1604	0	0
T4	522	121	0	0
T5	18447	11109	0	0
T12	15235	11717	0	0
T13	421	20	0	0
T14	403	2	0	0
T15	494	93	0	0
T16	494	93	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5314304	0	0
T1	353536	346596	0	0
T2	599	199	0	0
T3	3608	1608	0	0
T4	522	122	0	0
T5	18447	11109	0	0
T12	15235	11721	0	0
T13	421	21	0	0
T14	403	3	0	0
T15	494	94	0	0
T16	494	94	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	1509	0	0
T3	3608	0	0	0
T5	18447	27	0	0
T6	566	0	0	0
T12	15235	14	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T23	0	3	0	0
T30	0	11	0	0
T37	0	24	0	0
T38	0	24	0	0
T42	0	7	0	0
T44	0	26	0	0
T48	451	0	0	0
T69	0	13	0	0
T70	0	14	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	1469	0	0
T3	3608	0	0	0
T5	18447	27	0	0
T6	566	0	0	0
T12	15235	14	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T30	0	11	0	0
T37	0	24	0	0
T38	0	24	0	0
T42	0	7	0	0
T48	451	0	0	0
T69	0	13	0	0
T70	0	14	0	0
T88	0	3	0	0
T118	0	9	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	832	0	0
T5	18447	27	0	0
T6	566	0	0	0
T7	15844	0	0	0
T8	13312	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T30	0	11	0	0
T37	0	24	0	0
T48	451	0	0	0
T49	526	0	0	0
T69	0	13	0	0
T88	0	3	0	0
T118	0	9	0	0
T130	0	33	0	0
T249	0	14	0	0
T250	0	12	0	0
T253	0	8	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	832	0	0
T5	18447	27	0	0
T6	566	0	0	0
T7	15844	0	0	0
T8	13312	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T30	0	11	0	0
T37	0	24	0	0
T48	451	0	0	0
T49	526	0	0	0
T69	0	13	0	0
T88	0	3	0	0
T118	0	9	0	0
T130	0	33	0	0
T249	0	14	0	0
T250	0	12	0	0
T253	0	8	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	70898	0	0
T5	18447	2688	0	0
T6	566	0	0	0
T7	15844	0	0	0
T8	13312	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T30	0	1632	0	0
T37	0	1642	0	0
T48	451	0	0	0
T49	526	0	0	0
T69	0	309	0	0
T88	0	133	0	0
T118	0	1016	0	0
T130	0	6791	0	0
T249	0	1652	0	0
T250	0	1315	0	0
T253	0	58	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5738952	0	0
T1	353536	346596	0	0
T2	599	199	0	0
T3	3608	1608	0	0
T4	522	122	0	0
T5	18447	18020	0	0
T12	15235	14800	0	0
T13	421	21	0	0
T14	403	3	0	0
T15	494	94	0	0
T16	494	94	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5738952	0	0
T1	353536	346596	0	0
T2	599	199	0	0
T3	3608	1608	0	0
T4	522	122	0	0
T5	18447	18020	0	0
T12	15235	14800	0	0
T13	421	21	0	0
T14	403	3	0	0
T15	494	94	0	0
T16	494	94	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	751	0	0
T5	18447	23	0	0
T6	566	0	0	0
T7	15844	0	0	0
T8	13312	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T30	0	8	0	0
T37	0	22	0	0
T48	451	0	0	0
T49	526	0	0	0
T69	0	12	0	0
T88	0	2	0	0
T118	0	8	0	0
T130	0	31	0	0
T249	0	12	0	0
T250	0	8	0	0
T253	0	8	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T12,T5,T7
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T5,T7
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T5,T7,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T5,T7,T8

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T5,T7,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Covered	T1,T12,T3
1	1	Covered	T5,T7,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T76,T254,T255
1	0	Covered	T50,T77

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T5,T7,T8
1	0	Covered	T37,T50,T77

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T7,T8
1	-	Covered	T5,T7,T8

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T7,T8
DetectSt	168	Covered	T5,T7,T8
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T5,T7,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T7,T8
DebounceSt->IdleSt	163	Covered	T7,T37,T67
DetectSt->IdleSt	186	Covered	T76,T254,T255
DetectSt->StableSt	191	Covered	T5,T7,T8
IdleSt->DebounceSt	148	Covered	T5,T7,T8
StableSt->IdleSt	206	Covered	T5,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T5,T7,T8
0	1	Covered	T5,T7,T8
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T8
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T5,T7,T8
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T50,T77
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T7,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T7,T37,T67
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T7,T8
DetectSt	-	-	-	-	1	-	-	Covered	T76,T254,T255
DetectSt	-	-	-	-	0	1	-	Covered	T5,T7,T8
DetectSt	-	-	-	-	0	0	-	Covered	T5,T7,T8
StableSt	-	-	-	-	-	-	1	Covered	T5,T7,T8
StableSt	-	-	-	-	-	-	0	Covered	T5,T7,T8
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6431240	924	0	0
CntIncr_A	6431240	53106	0	0
CntNoWrap_A	6431240	5735548	0	0
DetectStDropOut_A	6431240	56	0	0
DetectedOut_A	6431240	14963	0	0
DetectedPulseOut_A	6431240	372	0	0
DisabledIdleSt_A	6431240	5338960	0	0
DisabledNoDetection_A	6431240	5340749	0	0
EnterDebounceSt_A	6431240	492	0	0
EnterDetectSt_A	6431240	432	0	0
EnterStableSt_A	6431240	372	0	0
PulseIsPulse_A	6431240	372	0	0
StayInStableSt	6431240	14558	0	0
gen_high_level_sva.HighLevelEvent_A	6431240	5738952	0	0
gen_not_sticky_sva.StableStDropOut_A	6431240	333	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	924	0	0
T5	18447	6	0	0
T6	566	0	0	0
T7	15844	5	0	0
T8	13312	4	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T27	0	10	0	0
T28	0	21	0	0
T30	0	6	0	0
T37	0	11	0	0
T48	451	0	0	0
T49	526	0	0	0
T67	0	5	0	0
T76	0	23	0	0
T87	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	53106	0	0
T5	18447	345	0	0
T6	566	0	0	0
T7	15844	228	0	0
T8	13312	190	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T27	0	630	0	0
T28	0	756	0	0
T30	0	195	0	0
T37	0	288	0	0
T48	451	0	0	0
T49	526	0	0	0
T67	0	238	0	0
T76	0	1653	0	0
T87	0	302	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5735548	0	0
T1	353536	346575	0	0
T2	599	198	0	0
T3	3608	1604	0	0
T4	522	121	0	0
T5	18447	18009	0	0
T12	15235	14795	0	0
T13	421	20	0	0
T14	403	2	0	0
T15	494	93	0	0
T16	494	93	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	56	0	0
T60	492	0	0	0
T68	524	0	0	0
T69	11286	0	0	0
T76	6316	10	0	0
T79	0	2	0	0
T83	0	1	0	0
T87	26992	0	0	0
T145	0	4	0	0
T151	0	4	0	0
T254	0	3	0	0
T255	0	5	0	0
T256	0	1	0	0
T257	0	4	0	0
T258	0	6	0	0
T259	625	0	0	0
T260	406	0	0	0
T261	438	0	0	0
T262	409	0	0	0
T263	422	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	14963	0	0
T5	18447	143	0	0
T6	566	0	0	0
T7	15844	35	0	0
T8	13312	176	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T27	0	24	0	0
T28	0	595	0	0
T30	0	235	0	0
T37	0	392	0	0
T48	451	0	0	0
T49	526	0	0	0
T67	0	91	0	0
T69	0	61	0	0
T87	0	10	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	372	0	0
T5	18447	3	0	0
T6	566	0	0	0
T7	15844	2	0	0
T8	13312	2	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T27	0	5	0	0
T28	0	9	0	0
T30	0	3	0	0
T37	0	5	0	0
T48	451	0	0	0
T49	526	0	0	0
T67	0	2	0	0
T69	0	1	0	0
T87	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5338960	0	0
T1	353536	346575	0	0
T2	599	198	0	0
T3	3608	1604	0	0
T4	522	121	0	0
T5	18447	15300	0	0
T12	15235	14795	0	0
T13	421	20	0	0
T14	403	2	0	0
T15	494	93	0	0
T16	494	93	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5340749	0	0
T1	353536	346596	0	0
T2	599	199	0	0
T3	3608	1608	0	0
T4	522	122	0	0
T5	18447	15301	0	0
T12	15235	14800	0	0
T13	421	21	0	0
T14	403	3	0	0
T15	494	94	0	0
T16	494	94	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	492	0	0
T5	18447	3	0	0
T6	566	0	0	0
T7	15844	3	0	0
T8	13312	2	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T27	0	5	0	0
T28	0	12	0	0
T30	0	3	0	0
T37	0	6	0	0
T48	451	0	0	0
T49	526	0	0	0
T67	0	3	0	0
T76	0	13	0	0
T87	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	432	0	0
T5	18447	3	0	0
T6	566	0	0	0
T7	15844	2	0	0
T8	13312	2	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T27	0	5	0	0
T28	0	9	0	0
T30	0	3	0	0
T37	0	5	0	0
T48	451	0	0	0
T49	526	0	0	0
T67	0	2	0	0
T76	0	10	0	0
T87	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	372	0	0
T5	18447	3	0	0
T6	566	0	0	0
T7	15844	2	0	0
T8	13312	2	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T27	0	5	0	0
T28	0	9	0	0
T30	0	3	0	0
T37	0	5	0	0
T48	451	0	0	0
T49	526	0	0	0
T67	0	2	0	0
T69	0	1	0	0
T87	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	372	0	0
T5	18447	3	0	0
T6	566	0	0	0
T7	15844	2	0	0
T8	13312	2	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T27	0	5	0	0
T28	0	9	0	0
T30	0	3	0	0
T37	0	5	0	0
T48	451	0	0	0
T49	526	0	0	0
T67	0	2	0	0
T69	0	1	0	0
T87	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	14558	0	0
T5	18447	138	0	0
T6	566	0	0	0
T7	15844	33	0	0
T8	13312	174	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T27	0	19	0	0
T28	0	586	0	0
T30	0	232	0	0
T37	0	386	0	0
T48	451	0	0	0
T49	526	0	0	0
T67	0	89	0	0
T69	0	59	0	0
T87	0	8	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5738952	0	0
T1	353536	346596	0	0
T2	599	199	0	0
T3	3608	1608	0	0
T4	522	122	0	0
T5	18447	18020	0	0
T12	15235	14800	0	0
T13	421	21	0	0
T14	403	3	0	0
T15	494	94	0	0
T16	494	94	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	333	0	0
T5	18447	1	0	0
T6	566	0	0	0
T7	15844	2	0	0
T8	13312	2	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T27	0	5	0	0
T28	0	9	0	0
T30	0	3	0	0
T37	0	3	0	0
T48	451	0	0	0
T49	526	0	0	0
T67	0	2	0	0
T87	0	2	0	0
T88	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T12,T5,T23
1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T12,T5,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T12,T5,T23

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T12,T5,T23

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T5,T23
1	0	Covered	T12,T5,T37
1	1	Covered	T12,T5,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T5,T23
0	1	Covered	T38,T42,T88
1	0	Covered	T12,T30,T70

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T23,T37
0	1	Covered	T5,T23,T37
1	0	Covered	T50,T241

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T23,T37
1	-	Covered	T5,T23,T37

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T12,T5,T23
DetectSt	168	Covered	T12,T5,T23
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T5,T23,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T12,T5,T23
DebounceSt->IdleSt	163	Covered	T23,T44,T50
DetectSt->IdleSt	186	Covered	T12,T38,T30
DetectSt->StableSt	191	Covered	T5,T23,T37
IdleSt->DebounceSt	148	Covered	T12,T5,T23
StableSt->IdleSt	206	Covered	T5,T23,T37

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T12,T5,T23
0	1	Covered	T12,T5,T23
0	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T5,T23
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T12,T5,T23
IdleSt	0	-	-	-	-	-	-	Covered	T12,T5,T23
DebounceSt	-	1	-	-	-	-	-	Covered	T50,T77
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T5,T23
DebounceSt	-	0	1	0	-	-	-	Covered	T23,T44,T50
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T5,T23
DetectSt	-	-	-	-	1	-	-	Covered	T12,T38,T30
DetectSt	-	-	-	-	0	1	-	Covered	T5,T23,T37
DetectSt	-	-	-	-	0	0	-	Covered	T12,T5,T23
StableSt	-	-	-	-	-	-	1	Covered	T5,T23,T37
StableSt	-	-	-	-	-	-	0	Covered	T5,T23,T37
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6431240	3225	0	0
CntIncr_A	6431240	105249	0	0
CntNoWrap_A	6431240	5733247	0	0
DetectStDropOut_A	6431240	583	0	0
DetectedOut_A	6431240	52269	0	0
DetectedPulseOut_A	6431240	707	0	0
DisabledIdleSt_A	6431240	5322540	0	0
DisabledNoDetection_A	6431240	5324852	0	0
EnterDebounceSt_A	6431240	1635	0	0
EnterDetectSt_A	6431240	1591	0	0
EnterStableSt_A	6431240	707	0	0
PulseIsPulse_A	6431240	707	0	0
StayInStableSt	6431240	51484	0	0
gen_high_event_sva.HighLevelEvent_A	6431240	5738952	0	0
gen_high_level_sva.HighLevelEvent_A	6431240	5738952	0	0
gen_not_sticky_sva.StableStDropOut_A	6431240	626	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	3225	0	0
T3	3608	0	0	0
T5	18447	34	0	0
T6	566	0	0	0
T12	15235	32	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T23	0	9	0	0
T30	0	16	0	0
T37	0	26	0	0
T38	0	38	0	0
T42	0	52	0	0
T44	0	26	0	0
T48	451	0	0	0
T69	0	62	0	0
T70	0	26	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	105249	0	0
T3	3608	0	0	0
T5	18447	1462	0	0
T6	566	0	0	0
T12	15235	922	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T23	0	404	0	0
T30	0	863	0	0
T37	0	1053	0	0
T38	0	945	0	0
T42	0	982	0	0
T44	0	1170	0	0
T48	451	0	0	0
T69	0	1860	0	0
T70	0	802	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5733247	0	0
T1	353536	346575	0	0
T2	599	198	0	0
T3	3608	1604	0	0
T4	522	121	0	0
T5	18447	17981	0	0
T12	15235	14763	0	0
T13	421	20	0	0
T14	403	2	0	0
T15	494	93	0	0
T16	494	93	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	583	0	0
T36	722	0	0	0
T38	5115	19	0	0
T39	709	0	0	0
T40	50642	0	0	0
T41	2522	0	0	0
T42	0	26	0	0
T53	801	0	0	0
T88	0	19	0	0
T92	0	21	0	0
T93	0	24	0	0
T95	0	23	0	0
T97	0	14	0	0
T98	0	5	0	0
T99	0	10	0	0
T130	0	5	0	0
T245	402	0	0	0
T246	422	0	0	0
T247	402	0	0	0
T248	628	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	52269	0	0
T5	18447	704	0	0
T6	566	0	0	0
T7	15844	0	0	0
T8	13312	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T23	0	25	0	0
T37	0	1018	0	0
T48	451	0	0	0
T49	526	0	0	0
T50	0	308	0	0
T69	0	1593	0	0
T118	0	1623	0	0
T134	0	2443	0	0
T249	0	899	0	0
T250	0	722	0	0
T264	0	1165	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	707	0	0
T5	18447	17	0	0
T6	566	0	0	0
T7	15844	0	0	0
T8	13312	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T23	0	1	0	0
T37	0	13	0	0
T48	451	0	0	0
T49	526	0	0	0
T50	0	5	0	0
T69	0	31	0	0
T118	0	20	0	0
T134	0	28	0	0
T249	0	16	0	0
T250	0	10	0	0
T264	0	17	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5322540	0	0
T1	353536	346575	0	0
T2	599	198	0	0
T3	3608	1604	0	0
T4	522	121	0	0
T5	18447	12141	0	0
T12	15235	11717	0	0
T13	421	20	0	0
T14	403	2	0	0
T15	494	93	0	0
T16	494	93	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5324852	0	0
T1	353536	346596	0	0
T2	599	199	0	0
T3	3608	1608	0	0
T4	522	122	0	0
T5	18447	12144	0	0
T12	15235	11721	0	0
T13	421	21	0	0
T14	403	3	0	0
T15	494	94	0	0
T16	494	94	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	1635	0	0
T3	3608	0	0	0
T5	18447	17	0	0
T6	566	0	0	0
T12	15235	16	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T23	0	9	0	0
T30	0	8	0	0
T37	0	13	0	0
T38	0	19	0	0
T42	0	26	0	0
T44	0	26	0	0
T48	451	0	0	0
T69	0	31	0	0
T70	0	13	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	1591	0	0
T3	3608	0	0	0
T5	18447	17	0	0
T6	566	0	0	0
T12	15235	16	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T23	0	1	0	0
T30	0	8	0	0
T37	0	13	0	0
T38	0	19	0	0
T42	0	26	0	0
T48	451	0	0	0
T69	0	31	0	0
T70	0	13	0	0
T88	0	24	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	707	0	0
T5	18447	17	0	0
T6	566	0	0	0
T7	15844	0	0	0
T8	13312	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T23	0	1	0	0
T37	0	13	0	0
T48	451	0	0	0
T49	526	0	0	0
T50	0	5	0	0
T69	0	31	0	0
T118	0	20	0	0
T134	0	28	0	0
T249	0	16	0	0
T250	0	10	0	0
T264	0	17	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	707	0	0
T5	18447	17	0	0
T6	566	0	0	0
T7	15844	0	0	0
T8	13312	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T23	0	1	0	0
T37	0	13	0	0
T48	451	0	0	0
T49	526	0	0	0
T50	0	5	0	0
T69	0	31	0	0
T118	0	20	0	0
T134	0	28	0	0
T249	0	16	0	0
T250	0	10	0	0
T264	0	17	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	51484	0	0
T5	18447	686	0	0
T6	566	0	0	0
T7	15844	0	0	0
T8	13312	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T23	0	24	0	0
T37	0	1001	0	0
T48	451	0	0	0
T49	526	0	0	0
T50	0	303	0	0
T69	0	1560	0	0
T118	0	1602	0	0
T134	0	2413	0	0
T249	0	882	0	0
T250	0	710	0	0
T264	0	1145	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5738952	0	0
T1	353536	346596	0	0
T2	599	199	0	0
T3	3608	1608	0	0
T4	522	122	0	0
T5	18447	18020	0	0
T12	15235	14800	0	0
T13	421	21	0	0
T14	403	3	0	0
T15	494	94	0	0
T16	494	94	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5738952	0	0
T1	353536	346596	0	0
T2	599	199	0	0
T3	3608	1608	0	0
T4	522	122	0	0
T5	18447	18020	0	0
T12	15235	14800	0	0
T13	421	21	0	0
T14	403	3	0	0
T15	494	94	0	0
T16	494	94	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	626	0	0
T5	18447	16	0	0
T6	566	0	0	0
T7	15844	0	0	0
T8	13312	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T23	0	1	0	0
T37	0	9	0	0
T48	451	0	0	0
T49	526	0	0	0
T50	0	4	0	0
T69	0	29	0	0
T118	0	19	0	0
T134	0	26	0	0
T249	0	15	0	0
T250	0	8	0	0
T264	0	14	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T12,T5,T7
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T5,T7
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T5,T7,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T5,T7,T8

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T5,T7,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Covered	T1,T12,T3
1	1	Covered	T5,T7,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T27,T265,T50
1	0	Covered	T50,T77

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T5,T7,T8
1	0	Covered	T77

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T7,T8
1	-	Covered	T5,T7,T8

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T7,T8
DetectSt	168	Covered	T5,T7,T8
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T5,T7,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T7,T8
DebounceSt->IdleSt	163	Covered	T27,T67,T89
DetectSt->IdleSt	186	Covered	T27,T265,T50
DetectSt->StableSt	191	Covered	T5,T7,T8
IdleSt->DebounceSt	148	Covered	T5,T7,T8
StableSt->IdleSt	206	Covered	T5,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T5,T7,T8
0	1	Covered	T5,T7,T8
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T8
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T5,T7,T8
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T50,T77
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T7,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T27,T67,T89
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T7,T8
DetectSt	-	-	-	-	1	-	-	Covered	T27,T265,T50
DetectSt	-	-	-	-	0	1	-	Covered	T5,T7,T8
DetectSt	-	-	-	-	0	0	-	Covered	T5,T7,T8
StableSt	-	-	-	-	-	-	1	Covered	T5,T7,T8
StableSt	-	-	-	-	-	-	0	Covered	T5,T7,T8
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6431240	911	0	0
CntIncr_A	6431240	46672	0	0
CntNoWrap_A	6431240	5735561	0	0
DetectStDropOut_A	6431240	50	0	0
DetectedOut_A	6431240	16043	0	0
DetectedPulseOut_A	6431240	377	0	0
DisabledIdleSt_A	6431240	5356589	0	0
DisabledNoDetection_A	6431240	5358345	0	0
EnterDebounceSt_A	6431240	482	0	0
EnterDetectSt_A	6431240	431	0	0
EnterStableSt_A	6431240	377	0	0
PulseIsPulse_A	6431240	377	0	0
StayInStableSt	6431240	15643	0	0
gen_high_level_sva.HighLevelEvent_A	6431240	5738952	0	0
gen_not_sticky_sva.StableStDropOut_A	6431240	353	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	911	0	0
T5	18447	2	0	0
T6	566	0	0	0
T7	15844	10	0	0
T8	13312	2	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T27	0	13	0	0
T28	0	6	0	0
T37	0	8	0	0
T48	451	0	0	0
T49	526	0	0	0
T67	0	19	0	0
T69	0	2	0	0
T87	0	2	0	0
T89	0	5	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	46672	0	0
T5	18447	80	0	0
T6	566	0	0	0
T7	15844	470	0	0
T8	13312	130	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T27	0	834	0	0
T28	0	342	0	0
T37	0	212	0	0
T48	451	0	0	0
T49	526	0	0	0
T67	0	1173	0	0
T69	0	63	0	0
T87	0	142	0	0
T89	0	252	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5735561	0	0
T1	353536	346575	0	0
T2	599	198	0	0
T3	3608	1604	0	0
T4	522	121	0	0
T5	18447	18013	0	0
T12	15235	14795	0	0
T13	421	20	0	0
T14	403	2	0	0
T15	494	93	0	0
T16	494	93	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	50	0	0
T27	16458	6	0	0
T28	24376	0	0	0
T43	39452	0	0	0
T44	4771	0	0	0
T50	0	1	0	0
T67	25992	0	0	0
T76	6316	0	0	0
T80	0	3	0	0
T87	26992	0	0	0
T103	0	9	0	0
T117	0	1	0	0
T145	0	5	0	0
T146	427	0	0	0
T147	944	0	0	0
T259	625	0	0	0
T265	0	1	0	0
T266	0	5	0	0
T267	0	8	0	0
T268	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	16043	0	0
T5	18447	84	0	0
T6	566	0	0	0
T7	15844	59	0	0
T8	13312	53	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T28	0	60	0	0
T37	0	298	0	0
T48	451	0	0	0
T49	526	0	0	0
T67	0	84	0	0
T69	0	60	0	0
T87	0	14	0	0
T89	0	138	0	0
T118	0	58	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	377	0	0
T5	18447	1	0	0
T6	566	0	0	0
T7	15844	5	0	0
T8	13312	1	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T28	0	3	0	0
T37	0	4	0	0
T48	451	0	0	0
T49	526	0	0	0
T67	0	9	0	0
T69	0	1	0	0
T87	0	1	0	0
T89	0	2	0	0
T118	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5356589	0	0
T1	353536	346575	0	0
T2	599	198	0	0
T3	3608	1604	0	0
T4	522	121	0	0
T5	18447	17312	0	0
T12	15235	14795	0	0
T13	421	20	0	0
T14	403	2	0	0
T15	494	93	0	0
T16	494	93	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5358345	0	0
T1	353536	346596	0	0
T2	599	199	0	0
T3	3608	1608	0	0
T4	522	122	0	0
T5	18447	17316	0	0
T12	15235	14800	0	0
T13	421	21	0	0
T14	403	3	0	0
T15	494	94	0	0
T16	494	94	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	482	0	0
T5	18447	1	0	0
T6	566	0	0	0
T7	15844	5	0	0
T8	13312	1	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T27	0	7	0	0
T28	0	3	0	0
T37	0	4	0	0
T48	451	0	0	0
T49	526	0	0	0
T67	0	10	0	0
T69	0	1	0	0
T87	0	1	0	0
T89	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	431	0	0
T5	18447	1	0	0
T6	566	0	0	0
T7	15844	5	0	0
T8	13312	1	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T27	0	6	0	0
T28	0	3	0	0
T37	0	4	0	0
T48	451	0	0	0
T49	526	0	0	0
T67	0	9	0	0
T69	0	1	0	0
T87	0	1	0	0
T89	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	377	0	0
T5	18447	1	0	0
T6	566	0	0	0
T7	15844	5	0	0
T8	13312	1	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T28	0	3	0	0
T37	0	4	0	0
T48	451	0	0	0
T49	526	0	0	0
T67	0	9	0	0
T69	0	1	0	0
T87	0	1	0	0
T89	0	2	0	0
T118	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	377	0	0
T5	18447	1	0	0
T6	566	0	0	0
T7	15844	5	0	0
T8	13312	1	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T28	0	3	0	0
T37	0	4	0	0
T48	451	0	0	0
T49	526	0	0	0
T67	0	9	0	0
T69	0	1	0	0
T87	0	1	0	0
T89	0	2	0	0
T118	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	15643	0	0
T5	18447	83	0	0
T6	566	0	0	0
T7	15844	54	0	0
T8	13312	52	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T28	0	57	0	0
T37	0	290	0	0
T48	451	0	0	0
T49	526	0	0	0
T67	0	75	0	0
T69	0	59	0	0
T87	0	13	0	0
T89	0	136	0	0
T118	0	57	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5738952	0	0
T1	353536	346596	0	0
T2	599	199	0	0
T3	3608	1608	0	0
T4	522	122	0	0
T5	18447	18020	0	0
T12	15235	14800	0	0
T13	421	21	0	0
T14	403	3	0	0
T15	494	94	0	0
T16	494	94	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	353	0	0
T5	18447	1	0	0
T6	566	0	0	0
T7	15844	5	0	0
T8	13312	1	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T28	0	3	0	0
T48	451	0	0	0
T49	526	0	0	0
T67	0	9	0	0
T69	0	1	0	0
T87	0	1	0	0
T89	0	2	0	0
T118	0	1	0	0
T120	0	8	0	0