Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T12,T5,T23
1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T12,T5,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T12,T5,T23

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T12,T5,T23

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T5,T23
1	0	Covered	T12,T5,T37
1	1	Covered	T12,T5,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T5,T23
0	1	Covered	T38,T42,T88
1	0	Covered	T69,T88,T264

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T5,T23
0	1	Covered	T12,T5,T23
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T5,T23
1	-	Covered	T12,T5,T23

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T12,T5,T23
DetectSt	168	Covered	T12,T5,T23
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T12,T5,T23

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T12,T5,T23
DebounceSt->IdleSt	163	Covered	T23,T44,T50
DetectSt->IdleSt	186	Covered	T38,T42,T69
DetectSt->StableSt	191	Covered	T12,T5,T23
IdleSt->DebounceSt	148	Covered	T12,T5,T23
StableSt->IdleSt	206	Covered	T12,T5,T23

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T12,T5,T23
0	1	Covered	T12,T5,T23
0	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T5,T23
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T12,T5,T23
IdleSt	0	-	-	-	-	-	-	Covered	T12,T5,T23
DebounceSt	-	1	-	-	-	-	-	Covered	T50,T77
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T5,T23
DebounceSt	-	0	1	0	-	-	-	Covered	T23,T44,T50
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T5,T23
DetectSt	-	-	-	-	1	-	-	Covered	T38,T42,T69
DetectSt	-	-	-	-	0	1	-	Covered	T12,T5,T23
DetectSt	-	-	-	-	0	0	-	Covered	T12,T5,T23
StableSt	-	-	-	-	-	-	1	Covered	T12,T5,T23
StableSt	-	-	-	-	-	-	0	Covered	T12,T5,T23
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6431240	2994	0	0
CntIncr_A	6431240	98523	0	0
CntNoWrap_A	6431240	5733478	0	0
DetectStDropOut_A	6431240	379	0	0
DetectedOut_A	6431240	81436	0	0
DetectedPulseOut_A	6431240	888	0	0
DisabledIdleSt_A	6431240	5303722	0	0
DisabledNoDetection_A	6431240	5306023	0	0
EnterDebounceSt_A	6431240	1515	0	0
EnterDetectSt_A	6431240	1479	0	0
EnterStableSt_A	6431240	888	0	0
PulseIsPulse_A	6431240	888	0	0
StayInStableSt	6431240	80460	0	0
gen_high_event_sva.HighLevelEvent_A	6431240	5738952	0	0
gen_high_level_sva.HighLevelEvent_A	6431240	5738952	0	0
gen_not_sticky_sva.StableStDropOut_A	6431240	800	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	2994	0	0
T3	3608	0	0	0
T5	18447	44	0	0
T6	566	0	0	0
T12	15235	8	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T23	0	29	0	0
T30	0	32	0	0
T37	0	8	0	0
T38	0	16	0	0
T42	0	16	0	0
T44	0	18	0	0
T48	451	0	0	0
T69	0	32	0	0
T70	0	32	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	98523	0	0
T3	3608	0	0	0
T5	18447	2068	0	0
T6	566	0	0	0
T12	15235	120	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T23	0	1060	0	0
T30	0	1008	0	0
T37	0	308	0	0
T38	0	394	0	0
T42	0	297	0	0
T44	0	810	0	0
T48	451	0	0	0
T69	0	972	0	0
T70	0	592	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5733478	0	0
T1	353536	346575	0	0
T2	599	198	0	0
T3	3608	1604	0	0
T4	522	121	0	0
T5	18447	17971	0	0
T12	15235	14787	0	0
T13	421	20	0	0
T14	403	2	0	0
T15	494	93	0	0
T16	494	93	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	379	0	0
T36	722	0	0	0
T38	5115	8	0	0
T39	709	0	0	0
T40	50642	0	0	0
T41	2522	0	0	0
T42	0	8	0	0
T53	801	0	0	0
T88	0	12	0	0
T92	0	3	0	0
T93	0	24	0	0
T95	0	25	0	0
T97	0	10	0	0
T98	0	15	0	0
T99	0	2	0	0
T244	0	3	0	0
T245	402	0	0	0
T246	422	0	0	0
T247	402	0	0	0
T248	628	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	81436	0	0
T3	3608	0	0	0
T5	18447	2321	0	0
T6	566	0	0	0
T12	15235	117	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T23	0	117	0	0
T30	0	2089	0	0
T37	0	478	0	0
T48	451	0	0	0
T70	0	622	0	0
T118	0	625	0	0
T249	0	2512	0	0
T250	0	2078	0	0
T253	0	1913	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	888	0	0
T3	3608	0	0	0
T5	18447	22	0	0
T6	566	0	0	0
T12	15235	4	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T23	0	12	0	0
T30	0	16	0	0
T37	0	4	0	0
T48	451	0	0	0
T70	0	16	0	0
T118	0	11	0	0
T249	0	31	0	0
T250	0	22	0	0
T253	0	25	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5303722	0	0
T1	353536	346575	0	0
T2	599	198	0	0
T3	3608	1604	0	0
T4	522	121	0	0
T5	18447	10464	0	0
T12	15235	11711	0	0
T13	421	20	0	0
T14	403	2	0	0
T15	494	93	0	0
T16	494	93	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5306023	0	0
T1	353536	346596	0	0
T2	599	199	0	0
T3	3608	1608	0	0
T4	522	122	0	0
T5	18447	10465	0	0
T12	15235	11715	0	0
T13	421	21	0	0
T14	403	3	0	0
T15	494	94	0	0
T16	494	94	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	1515	0	0
T3	3608	0	0	0
T5	18447	22	0	0
T6	566	0	0	0
T12	15235	4	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T23	0	17	0	0
T30	0	16	0	0
T37	0	4	0	0
T38	0	8	0	0
T42	0	8	0	0
T44	0	18	0	0
T48	451	0	0	0
T69	0	16	0	0
T70	0	16	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	1479	0	0
T3	3608	0	0	0
T5	18447	22	0	0
T6	566	0	0	0
T12	15235	4	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T23	0	12	0	0
T30	0	16	0	0
T37	0	4	0	0
T38	0	8	0	0
T42	0	8	0	0
T48	451	0	0	0
T69	0	16	0	0
T70	0	16	0	0
T88	0	15	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	888	0	0
T3	3608	0	0	0
T5	18447	22	0	0
T6	566	0	0	0
T12	15235	4	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T23	0	12	0	0
T30	0	16	0	0
T37	0	4	0	0
T48	451	0	0	0
T70	0	16	0	0
T118	0	11	0	0
T249	0	31	0	0
T250	0	22	0	0
T253	0	25	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	888	0	0
T3	3608	0	0	0
T5	18447	22	0	0
T6	566	0	0	0
T12	15235	4	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T23	0	12	0	0
T30	0	16	0	0
T37	0	4	0	0
T48	451	0	0	0
T70	0	16	0	0
T118	0	11	0	0
T249	0	31	0	0
T250	0	22	0	0
T253	0	25	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	80460	0	0
T3	3608	0	0	0
T5	18447	2296	0	0
T6	566	0	0	0
T12	15235	113	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T23	0	105	0	0
T30	0	2071	0	0
T37	0	472	0	0
T48	451	0	0	0
T70	0	606	0	0
T118	0	613	0	0
T249	0	2478	0	0
T250	0	2051	0	0
T253	0	1883	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5738952	0	0
T1	353536	346596	0	0
T2	599	199	0	0
T3	3608	1608	0	0
T4	522	122	0	0
T5	18447	18020	0	0
T12	15235	14800	0	0
T13	421	21	0	0
T14	403	3	0	0
T15	494	94	0	0
T16	494	94	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5738952	0	0
T1	353536	346596	0	0
T2	599	199	0	0
T3	3608	1608	0	0
T4	522	122	0	0
T5	18447	18020	0	0
T12	15235	14800	0	0
T13	421	21	0	0
T14	403	3	0	0
T15	494	94	0	0
T16	494	94	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	800	0	0
T3	3608	0	0	0
T5	18447	19	0	0
T6	566	0	0	0
T12	15235	4	0	0
T13	421	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T23	0	12	0	0
T30	0	14	0	0
T37	0	2	0	0
T48	451	0	0	0
T70	0	16	0	0
T118	0	10	0	0
T249	0	28	0	0
T250	0	17	0	0
T253	0	20	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T12,T5,T7
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T5,T7
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T5,T7,T37

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T5,T7,T37

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T5,T7,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T5,T7
1	0	Covered	T1,T12,T3
1	1	Covered	T5,T7,T37

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T37
0	1	Covered	T67,T55,T254
1	0	Covered	T50,T77

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T37
0	1	Covered	T5,T7,T30
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T7,T37
1	-	Covered	T5,T7,T30

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T7,T37
DetectSt	168	Covered	T5,T7,T37
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T5,T7,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T7,T37
DebounceSt->IdleSt	163	Covered	T30,T67,T87
DetectSt->IdleSt	186	Covered	T67,T55,T254
DetectSt->StableSt	191	Covered	T5,T7,T37
IdleSt->DebounceSt	148	Covered	T5,T7,T37
StableSt->IdleSt	206	Covered	T5,T7,T37

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T5,T7,T37
0	1	Covered	T5,T7,T37
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T37
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T5,T7,T37
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T50,T77
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T7,T37
DebounceSt	-	0	1	0	-	-	-	Covered	T30,T67,T87
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T7,T37
DetectSt	-	-	-	-	1	-	-	Covered	T67,T55,T254
DetectSt	-	-	-	-	0	1	-	Covered	T5,T7,T37
DetectSt	-	-	-	-	0	0	-	Covered	T5,T7,T37
StableSt	-	-	-	-	-	-	1	Covered	T5,T7,T30
StableSt	-	-	-	-	-	-	0	Covered	T5,T7,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6431240	873	0	0
CntIncr_A	6431240	45642	0	0
CntNoWrap_A	6431240	5735599	0	0
DetectStDropOut_A	6431240	82	0	0
DetectedOut_A	6431240	13925	0	0
DetectedPulseOut_A	6431240	327	0	0
DisabledIdleSt_A	6431240	5328173	0	0
DisabledNoDetection_A	6431240	5329927	0	0
EnterDebounceSt_A	6431240	459	0	0
EnterDetectSt_A	6431240	415	0	0
EnterStableSt_A	6431240	327	0	0
PulseIsPulse_A	6431240	327	0	0
StayInStableSt	6431240	13563	0	0
gen_high_level_sva.HighLevelEvent_A	6431240	5738952	0	0
gen_not_sticky_sva.StableStDropOut_A	6431240	288	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	873	0	0
T5	18447	2	0	0
T6	566	0	0	0
T7	15844	4	0	0
T8	13312	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T27	0	8	0	0
T30	0	3	0	0
T37	0	4	0	0
T48	451	0	0	0
T49	526	0	0	0
T67	0	11	0	0
T87	0	20	0	0
T118	0	2	0	0
T120	0	9	0	0
T249	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	45642	0	0
T5	18447	84	0	0
T6	566	0	0	0
T7	15844	172	0	0
T8	13312	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T27	0	352	0	0
T30	0	106	0	0
T37	0	106	0	0
T48	451	0	0	0
T49	526	0	0	0
T67	0	725	0	0
T87	0	1031	0	0
T118	0	80	0	0
T120	0	527	0	0
T249	0	171	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5735599	0	0
T1	353536	346575	0	0
T2	599	198	0	0
T3	3608	1604	0	0
T4	522	121	0	0
T5	18447	18013	0	0
T12	15235	14795	0	0
T13	421	20	0	0
T14	403	2	0	0
T15	494	93	0	0
T16	494	93	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	82	0	0
T28	24376	0	0	0
T55	0	1	0	0
T57	0	1	0	0
T67	25992	5	0	0
T68	524	0	0	0
T69	11286	0	0	0
T76	6316	0	0	0
T87	26992	0	0	0
T94	0	1	0	0
T96	0	1	0	0
T132	0	3	0	0
T146	427	0	0	0
T147	944	0	0	0
T254	0	5	0	0
T256	0	3	0	0
T259	625	0	0	0
T260	406	0	0	0
T265	0	5	0	0
T269	0	5	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	13925	0	0
T5	18447	80	0	0
T6	566	0	0	0
T7	15844	38	0	0
T8	13312	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T27	0	170	0	0
T30	0	81	0	0
T37	0	150	0	0
T48	451	0	0	0
T49	526	0	0	0
T87	0	521	0	0
T118	0	64	0	0
T120	0	209	0	0
T249	0	202	0	0
T250	0	248	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	327	0	0
T5	18447	1	0	0
T6	566	0	0	0
T7	15844	2	0	0
T8	13312	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T27	0	4	0	0
T30	0	1	0	0
T37	0	2	0	0
T48	451	0	0	0
T49	526	0	0	0
T87	0	9	0	0
T118	0	1	0	0
T120	0	4	0	0
T249	0	3	0	0
T250	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5328173	0	0
T1	353536	346575	0	0
T2	599	198	0	0
T3	3608	1604	0	0
T4	522	121	0	0
T5	18447	15697	0	0
T12	15235	14678	0	0
T13	421	20	0	0
T14	403	2	0	0
T15	494	93	0	0
T16	494	93	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5329927	0	0
T1	353536	346596	0	0
T2	599	199	0	0
T3	3608	1608	0	0
T4	522	122	0	0
T5	18447	15699	0	0
T12	15235	14683	0	0
T13	421	21	0	0
T14	403	3	0	0
T15	494	94	0	0
T16	494	94	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	459	0	0
T5	18447	1	0	0
T6	566	0	0	0
T7	15844	2	0	0
T8	13312	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T27	0	4	0	0
T30	0	2	0	0
T37	0	2	0	0
T48	451	0	0	0
T49	526	0	0	0
T67	0	6	0	0
T87	0	11	0	0
T118	0	1	0	0
T120	0	5	0	0
T249	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	415	0	0
T5	18447	1	0	0
T6	566	0	0	0
T7	15844	2	0	0
T8	13312	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T27	0	4	0	0
T30	0	1	0	0
T37	0	2	0	0
T48	451	0	0	0
T49	526	0	0	0
T67	0	5	0	0
T87	0	9	0	0
T118	0	1	0	0
T120	0	4	0	0
T249	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	327	0	0
T5	18447	1	0	0
T6	566	0	0	0
T7	15844	2	0	0
T8	13312	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T27	0	4	0	0
T30	0	1	0	0
T37	0	2	0	0
T48	451	0	0	0
T49	526	0	0	0
T87	0	9	0	0
T118	0	1	0	0
T120	0	4	0	0
T249	0	3	0	0
T250	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	327	0	0
T5	18447	1	0	0
T6	566	0	0	0
T7	15844	2	0	0
T8	13312	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T27	0	4	0	0
T30	0	1	0	0
T37	0	2	0	0
T48	451	0	0	0
T49	526	0	0	0
T87	0	9	0	0
T118	0	1	0	0
T120	0	4	0	0
T249	0	3	0	0
T250	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	13563	0	0
T5	18447	79	0	0
T6	566	0	0	0
T7	15844	36	0	0
T8	13312	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T27	0	166	0	0
T30	0	80	0	0
T37	0	146	0	0
T48	451	0	0	0
T49	526	0	0	0
T87	0	512	0	0
T118	0	62	0	0
T120	0	205	0	0
T249	0	199	0	0
T250	0	243	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	5738952	0	0
T1	353536	346596	0	0
T2	599	199	0	0
T3	3608	1608	0	0
T4	522	122	0	0
T5	18447	18020	0	0
T12	15235	14800	0	0
T13	421	21	0	0
T14	403	3	0	0
T15	494	94	0	0
T16	494	94	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6431240	288	0	0
T5	18447	1	0	0
T6	566	0	0	0
T7	15844	2	0	0
T8	13312	0	0	0
T14	403	0	0	0
T15	494	0	0	0
T16	494	0	0	0
T21	494	0	0	0
T27	0	4	0	0
T30	0	1	0	0
T48	451	0	0	0
T49	526	0	0	0
T87	0	9	0	0
T120	0	4	0	0
T249	0	3	0	0
T250	0	1	0	0
T253	0	4	0	0
T270	0	6	0	0