Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1347279588	11901	0	0
auto_block_debounce_ctl_rd_A	1347279588	1753	0	0
auto_block_out_ctl_rd_A	1347279588	2811	0	0
com_det_ctl_0_rd_A	1347279588	3321	0	0
com_det_ctl_1_rd_A	1347279588	3428	0	0
com_det_ctl_2_rd_A	1347279588	3528	0	0
com_det_ctl_3_rd_A	1347279588	3384	0	0
com_out_ctl_0_rd_A	1347279588	4115	0	0
com_out_ctl_1_rd_A	1347279588	4144	0	0
com_out_ctl_2_rd_A	1347279588	4131	0	0
com_out_ctl_3_rd_A	1347279588	4247	0	0
com_pre_det_ctl_0_rd_A	1347279588	1282	0	0
com_pre_det_ctl_1_rd_A	1347279588	1424	0	0
com_pre_det_ctl_2_rd_A	1347279588	1335	0	0
com_pre_det_ctl_3_rd_A	1347279588	1311	0	0
com_pre_sel_ctl_0_rd_A	1347279588	4429	0	0
com_pre_sel_ctl_1_rd_A	1347279588	4467	0	0
com_pre_sel_ctl_2_rd_A	1347279588	4207	0	0
com_pre_sel_ctl_3_rd_A	1347279588	4380	0	0
com_sel_ctl_0_rd_A	1347279588	4431	0	0
com_sel_ctl_1_rd_A	1347279588	4291	0	0
com_sel_ctl_2_rd_A	1347279588	4388	0	0
com_sel_ctl_3_rd_A	1347279588	4310	0	0
ec_rst_ctl_rd_A	1347279588	2135	0	0
intr_enable_rd_A	1347279588	2160	0	0
key_intr_ctl_rd_A	1347279588	4565	0	0
key_intr_debounce_ctl_rd_A	1347279588	1372	0	0
key_invert_ctl_rd_A	1347279588	5125	0	0
pin_allowed_ctl_rd_A	1347279588	6964	0	0
pin_out_ctl_rd_A	1347279588	5108	0	0
pin_out_value_rd_A	1347279588	5550	0	0
regwen_rd_A	1347279588	1591	0	0
ulp_ac_debounce_ctl_rd_A	1347279588	1497	0	0
ulp_ctl_rd_A	1347279588	1467	0	0
ulp_lid_debounce_ctl_rd_A	1347279588	1475	0	0
ulp_pwrb_debounce_ctl_rd_A	1347279588	1482	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1347279588	11901	0	0
T1	238627	8	0	0
T2	222958	0	0	0
T3	246929	0	0	0
T4	253206	0	0	0
T5	230590	0	0	0
T12	182824	0	0	0
T13	202357	0	0	0
T14	183648	0	0	0
T15	247033	0	0	0
T16	247262	0	0	0
T33	0	7	0	0
T55	0	17	0	0
T57	0	10	0	0
T94	0	5	0	0
T185	0	4	0	0
T290	0	8	0	0
T291	0	2	0	0
T292	0	13	0	0
T293	0	7	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1347279588	1753	0	0
T3	246929	7	0	0
T5	230590	0	0	0
T6	251082	0	0	0
T7	205970	0	0	0
T14	183648	0	0	0
T15	247033	0	0	0
T16	247262	0	0	0
T21	242228	0	0	0
T22	0	6	0	0
T41	0	6	0	0
T48	221137	0	0	0
T49	65737	0	0	0
T57	0	7	0	0
T85	0	7	0	0
T94	0	24	0	0
T125	0	3	0	0
T290	0	17	0	0
T294	0	4	0	0
T295	0	10	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1347279588	2811	0	0
T3	246929	8	0	0
T5	230590	0	0	0
T6	251082	0	0	0
T7	205970	0	0	0
T14	183648	0	0	0
T15	247033	0	0	0
T16	247262	0	0	0
T21	242228	0	0	0
T22	0	9	0	0
T41	0	6	0	0
T48	221137	0	0	0
T49	65737	0	0	0
T85	0	14	0	0
T94	0	20	0	0
T167	0	3	0	0
T290	0	14	0	0
T294	0	17	0	0
T295	0	12	0	0
T296	0	5	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1347279588	3321	0	0
T5	230590	51	0	0
T6	251082	0	0	0
T7	205970	66	0	0
T8	638987	0	0	0
T14	183648	0	0	0
T15	247033	0	0	0
T16	247262	0	0	0
T21	242228	0	0	0
T27	0	84	0	0
T48	221137	0	0	0
T49	65737	0	0	0
T57	0	10	0	0
T70	0	31	0	0
T94	0	100	0	0
T255	0	41	0	0
T265	0	78	0	0
T290	0	19	0	0
T293	0	5	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1347279588	3428	0	0
T5	230590	79	0	0
T6	251082	0	0	0
T7	205970	83	0	0
T8	638987	0	0	0
T14	183648	0	0	0
T15	247033	0	0	0
T16	247262	0	0	0
T21	242228	0	0	0
T27	0	64	0	0
T48	221137	0	0	0
T49	65737	0	0	0
T57	0	22	0	0
T70	0	46	0	0
T94	0	90	0	0
T255	0	86	0	0
T265	0	68	0	0
T290	0	14	0	0
T293	0	7	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1347279588	3528	0	0
T5	230590	72	0	0
T6	251082	0	0	0
T7	205970	72	0	0
T8	638987	0	0	0
T14	183648	0	0	0
T15	247033	0	0	0
T16	247262	0	0	0
T21	242228	0	0	0
T27	0	57	0	0
T48	221137	0	0	0
T49	65737	0	0	0
T57	0	2	0	0
T70	0	33	0	0
T94	0	77	0	0
T252	0	39	0	0
T255	0	85	0	0
T265	0	88	0	0
T290	0	30	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1347279588	3384	0	0
T5	230590	49	0	0
T6	251082	0	0	0
T7	205970	58	0	0
T8	638987	0	0	0
T14	183648	0	0	0
T15	247033	0	0	0
T16	247262	0	0	0
T21	242228	0	0	0
T27	0	81	0	0
T48	221137	0	0	0
T49	65737	0	0	0
T57	0	21	0	0
T70	0	14	0	0
T94	0	83	0	0
T255	0	81	0	0
T265	0	76	0	0
T290	0	9	0	0
T293	0	6	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1347279588	4115	0	0
T5	230590	63	0	0
T6	251082	0	0	0
T7	205970	48	0	0
T8	638987	0	0	0
T14	183648	0	0	0
T15	247033	0	0	0
T16	247262	0	0	0
T21	242228	0	0	0
T27	0	81	0	0
T48	221137	0	0	0
T49	65737	0	0	0
T57	0	21	0	0
T70	0	26	0	0
T94	0	86	0	0
T255	0	56	0	0
T265	0	75	0	0
T290	0	22	0	0
T293	0	5	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1347279588	4144	0	0
T5	230590	36	0	0
T6	251082	0	0	0
T7	205970	73	0	0
T8	638987	0	0	0
T14	183648	0	0	0
T15	247033	0	0	0
T16	247262	0	0	0
T21	242228	0	0	0
T27	0	90	0	0
T48	221137	0	0	0
T49	65737	0	0	0
T57	0	13	0	0
T70	0	43	0	0
T94	0	91	0	0
T255	0	87	0	0
T265	0	71	0	0
T290	0	19	0	0
T293	0	7	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1347279588	4131	0	0
T5	230590	58	0	0
T6	251082	0	0	0
T7	205970	76	0	0
T8	638987	0	0	0
T14	183648	0	0	0
T15	247033	0	0	0
T16	247262	0	0	0
T21	242228	0	0	0
T27	0	65	0	0
T48	221137	0	0	0
T49	65737	0	0	0
T57	0	15	0	0
T70	0	33	0	0
T94	0	81	0	0
T255	0	69	0	0
T265	0	55	0	0
T290	0	9	0	0
T293	0	5	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1347279588	4247	0	0
T5	230590	54	0	0
T6	251082	0	0	0
T7	205970	68	0	0
T8	638987	0	0	0
T14	183648	0	0	0
T15	247033	0	0	0
T16	247262	0	0	0
T21	242228	0	0	0
T27	0	87	0	0
T48	221137	0	0	0
T49	65737	0	0	0
T57	0	12	0	0
T70	0	38	0	0
T94	0	93	0	0
T255	0	66	0	0
T265	0	78	0	0
T290	0	17	0	0
T293	0	12	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1347279588	1282	0	0
T75	223510	0	0	0
T94	0	21	0	0
T139	0	23	0	0
T150	69208	0	0	0
T155	0	20	0	0
T166	88982	0	0	0
T167	0	7	0	0
T239	0	11	0	0
T290	211707	10	0	0
T293	0	7	0	0
T294	80072	0	0	0
T297	0	10	0	0
T298	0	21	0	0
T299	0	20	0	0
T300	205170	0	0	0
T301	36494	0	0	0
T302	55193	0	0	0
T303	211438	0	0	0
T304	190923	0	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1347279588	1424	0	0
T57	115895	2	0	0
T94	0	5	0	0
T139	0	26	0	0
T155	0	33	0	0
T167	0	20	0	0
T239	0	4	0	0
T290	0	21	0	0
T293	0	2	0	0
T297	0	11	0	0
T298	0	17	0	0
T305	145607	0	0	0
T306	36933	0	0	0
T307	238811	0	0	0
T308	21540	0	0	0
T309	20807	0	0	0
T310	199288	0	0	0
T311	239414	0	0	0
T312	50636	0	0	0
T313	432294	0	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1347279588	1335	0	0
T57	115895	9	0	0
T94	0	3	0	0
T139	0	13	0	0
T155	0	22	0	0
T167	0	15	0	0
T239	0	27	0	0
T290	0	16	0	0
T293	0	9	0	0
T297	0	5	0	0
T298	0	5	0	0
T305	145607	0	0	0
T306	36933	0	0	0
T307	238811	0	0	0
T308	21540	0	0	0
T309	20807	0	0	0
T310	199288	0	0	0
T311	239414	0	0	0
T312	50636	0	0	0
T313	432294	0	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1347279588	1311	0	0
T57	115895	16	0	0
T94	0	10	0	0
T139	0	33	0	0
T155	0	39	0	0
T167	0	9	0	0
T239	0	13	0	0
T290	0	11	0	0
T297	0	13	0	0
T298	0	19	0	0
T299	0	11	0	0
T305	145607	0	0	0
T306	36933	0	0	0
T307	238811	0	0	0
T308	21540	0	0	0
T309	20807	0	0	0
T310	199288	0	0	0
T311	239414	0	0	0
T312	50636	0	0	0
T313	432294	0	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1347279588	4429	0	0
T5	230590	67	0	0
T6	251082	0	0	0
T7	205970	79	0	0
T8	638987	0	0	0
T14	183648	0	0	0
T15	247033	0	0	0
T16	247262	0	0	0
T21	242228	0	0	0
T27	0	54	0	0
T48	221137	0	0	0
T49	65737	0	0	0
T57	0	11	0	0
T70	0	30	0	0
T94	0	91	0	0
T255	0	91	0	0
T265	0	78	0	0
T290	0	7	0	0
T293	0	4	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1347279588	4467	0	0
T5	230590	40	0	0
T6	251082	0	0	0
T7	205970	67	0	0
T8	638987	0	0	0
T14	183648	0	0	0
T15	247033	0	0	0
T16	247262	0	0	0
T21	242228	0	0	0
T27	0	75	0	0
T48	221137	0	0	0
T49	65737	0	0	0
T57	0	10	0	0
T70	0	45	0	0
T94	0	74	0	0
T255	0	50	0	0
T265	0	58	0	0
T290	0	25	0	0
T293	0	3	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1347279588	4207	0	0
T5	230590	67	0	0
T6	251082	0	0	0
T7	205970	47	0	0
T8	638987	0	0	0
T14	183648	0	0	0
T15	247033	0	0	0
T16	247262	0	0	0
T21	242228	0	0	0
T27	0	55	0	0
T48	221137	0	0	0
T49	65737	0	0	0
T57	0	3	0	0
T70	0	41	0	0
T94	0	82	0	0
T255	0	51	0	0
T265	0	64	0	0
T290	0	11	0	0
T293	0	14	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1347279588	4380	0	0
T5	230590	58	0	0
T6	251082	0	0	0
T7	205970	92	0	0
T8	638987	0	0	0
T14	183648	0	0	0
T15	247033	0	0	0
T16	247262	0	0	0
T21	242228	0	0	0
T27	0	77	0	0
T48	221137	0	0	0
T49	65737	0	0	0
T70	0	38	0	0
T94	0	98	0	0
T252	0	42	0	0
T255	0	70	0	0
T265	0	80	0	0
T290	0	17	0	0
T293	0	3	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1347279588	4431	0	0
T5	230590	50	0	0
T6	251082	0	0	0
T7	205970	75	0	0
T8	638987	0	0	0
T14	183648	0	0	0
T15	247033	0	0	0
T16	247262	0	0	0
T21	242228	0	0	0
T27	0	82	0	0
T48	221137	0	0	0
T49	65737	0	0	0
T57	0	11	0	0
T70	0	35	0	0
T94	0	101	0	0
T255	0	61	0	0
T265	0	63	0	0
T290	0	12	0	0
T293	0	6	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1347279588	4291	0	0
T5	230590	57	0	0
T6	251082	0	0	0
T7	205970	75	0	0
T8	638987	0	0	0
T14	183648	0	0	0
T15	247033	0	0	0
T16	247262	0	0	0
T21	242228	0	0	0
T27	0	77	0	0
T48	221137	0	0	0
T49	65737	0	0	0
T57	0	15	0	0
T70	0	31	0	0
T94	0	89	0	0
T255	0	65	0	0
T265	0	84	0	0
T290	0	23	0	0
T293	0	1	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1347279588	4388	0	0
T5	230590	49	0	0
T6	251082	0	0	0
T7	205970	89	0	0
T8	638987	0	0	0
T14	183648	0	0	0
T15	247033	0	0	0
T16	247262	0	0	0
T21	242228	0	0	0
T27	0	69	0	0
T48	221137	0	0	0
T49	65737	0	0	0
T57	0	13	0	0
T70	0	48	0	0
T94	0	77	0	0
T255	0	89	0	0
T265	0	68	0	0
T290	0	9	0	0
T293	0	3	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1347279588	4310	0	0
T5	230590	44	0	0
T6	251082	0	0	0
T7	205970	75	0	0
T8	638987	0	0	0
T14	183648	0	0	0
T15	247033	0	0	0
T16	247262	0	0	0
T21	242228	0	0	0
T27	0	70	0	0
T48	221137	0	0	0
T49	65737	0	0	0
T57	0	8	0	0
T70	0	30	0	0
T94	0	100	0	0
T255	0	51	0	0
T265	0	97	0	0
T290	0	17	0	0
T293	0	5	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1347279588	2135	0	0
T5	230590	13	0	0
T6	251082	0	0	0
T7	205970	33	0	0
T8	638987	0	0	0
T14	183648	0	0	0
T15	247033	0	0	0
T16	247262	0	0	0
T21	242228	0	0	0
T23	0	1	0	0
T27	0	16	0	0
T48	221137	0	0	0
T49	65737	0	0	0
T57	0	21	0	0
T70	0	2	0	0
T92	0	6	0	0
T265	0	19	0	0
T290	0	22	0	0
T314	0	1	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1347279588	2160	0	0
T57	115895	36	0	0
T94	0	57	0	0
T139	0	40	0	0
T155	0	52	0	0
T167	0	3	0	0
T290	0	49	0	0
T293	0	13	0	0
T297	0	9	0	0
T305	145607	0	0	0
T306	36933	0	0	0
T307	238811	0	0	0
T308	21540	0	0	0
T309	20807	0	0	0
T310	199288	0	0	0
T311	239414	0	0	0
T312	50636	0	0	0
T313	432294	0	0	0
T315	0	9	0	0
T316	0	7	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1347279588	4565	0	0
T57	115895	5	0	0
T94	0	7	0	0
T135	0	1	0	0
T136	0	1	0	0
T149	0	1	0	0
T150	0	4	0	0
T167	0	26	0	0
T182	33584	3	0	0
T290	0	12	0	0
T293	0	10	0	0
T305	145607	0	0	0
T306	36933	0	0	0
T307	238811	0	0	0
T308	21540	0	0	0
T309	20807	0	0	0
T310	199288	0	0	0
T311	239414	0	0	0
T312	50636	0	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1347279588	1372	0	0
T57	115895	6	0	0
T94	0	3	0	0
T139	0	12	0	0
T155	0	25	0	0
T167	0	23	0	0
T239	0	23	0	0
T290	0	14	0	0
T293	0	14	0	0
T297	0	17	0	0
T298	0	22	0	0
T305	145607	0	0	0
T306	36933	0	0	0
T307	238811	0	0	0
T308	21540	0	0	0
T309	20807	0	0	0
T310	199288	0	0	0
T311	239414	0	0	0
T312	50636	0	0	0
T313	432294	0	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1347279588	5125	0	0
T7	205970	0	0	0
T8	638987	0	0	0
T9	325144	0	0	0
T10	68107	0	0	0
T21	242228	87	0	0
T23	108423	0	0	0
T49	65737	0	0	0
T57	0	110	0	0
T58	0	59	0	0
T90	420132	0	0	0
T91	53092	0	0	0
T94	0	224	0	0
T108	53170	0	0	0
T167	0	117	0	0
T290	0	19	0	0
T293	0	69	0	0
T317	0	65	0	0
T318	0	40	0	0
T319	0	53	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1347279588	6964	0	0
T20	116399	0	0	0
T27	197498	0	0	0
T30	401400	0	0	0
T42	110695	0	0	0
T43	187404	0	0	0
T44	453240	0	0	0
T51	49519	0	0	0
T57	0	142	0	0
T66	125839	67	0	0
T67	649820	0	0	0
T146	53403	0	0	0
T290	0	20	0	0
T307	0	74	0	0
T317	0	74	0	0
T320	0	36	0	0
T321	0	89	0	0
T322	0	96	0	0
T323	0	67	0	0
T324	0	67	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1347279588	5108	0	0
T20	116399	0	0	0
T27	197498	0	0	0
T30	401400	0	0	0
T42	110695	0	0	0
T43	187404	0	0	0
T44	453240	0	0	0
T51	49519	0	0	0
T57	0	202	0	0
T66	125839	61	0	0
T67	649820	0	0	0
T146	53403	0	0	0
T290	0	8	0	0
T307	0	56	0	0
T317	0	52	0	0
T320	0	47	0	0
T321	0	35	0	0
T322	0	67	0	0
T323	0	73	0	0
T324	0	69	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1347279588	5550	0	0
T20	116399	0	0	0
T27	197498	0	0	0
T30	401400	0	0	0
T42	110695	0	0	0
T43	187404	0	0	0
T44	453240	0	0	0
T51	49519	0	0	0
T57	0	156	0	0
T66	125839	60	0	0
T67	649820	0	0	0
T146	53403	0	0	0
T290	0	21	0	0
T307	0	68	0	0
T317	0	68	0	0
T320	0	46	0	0
T321	0	35	0	0
T322	0	63	0	0
T323	0	56	0	0
T324	0	71	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1347279588	1591	0	0
T57	115895	8	0	0
T94	0	8	0	0
T139	0	16	0	0
T155	0	17	0	0
T167	0	13	0	0
T239	0	7	0	0
T290	0	11	0	0
T293	0	5	0	0
T297	0	8	0	0
T298	0	24	0	0
T305	145607	0	0	0
T306	36933	0	0	0
T307	238811	0	0	0
T308	21540	0	0	0
T309	20807	0	0	0
T310	199288	0	0	0
T311	239414	0	0	0
T312	50636	0	0	0
T313	432294	0	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1347279588	1497	0	0
T2	222958	7	0	0
T3	246929	0	0	0
T4	253206	0	0	0
T5	230590	0	0	0
T12	182824	0	0	0
T13	202357	0	0	0
T14	183648	0	0	0
T15	247033	0	0	0
T16	247262	0	0	0
T48	221137	0	0	0
T57	0	2	0	0
T85	0	4	0	0
T94	0	20	0	0
T123	0	4	0	0
T167	0	30	0	0
T290	0	15	0	0
T293	0	1	0	0
T325	0	7	0	0
T326	0	1	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1347279588	1467	0	0
T3	246929	9	0	0
T5	230590	0	0	0
T6	251082	0	0	0
T7	205970	0	0	0
T14	183648	0	0	0
T15	247033	0	0	0
T16	247262	0	0	0
T21	242228	0	0	0
T48	221137	0	0	0
T49	65737	0	0	0
T57	0	6	0	0
T85	0	3	0	0
T94	0	7	0	0
T123	0	3	0	0
T167	0	11	0	0
T209	0	4	0	0
T290	0	21	0	0
T293	0	16	0	0
T325	0	1	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1347279588	1475	0	0
T2	222958	4	0	0
T3	246929	0	0	0
T4	253206	0	0	0
T5	230590	0	0	0
T12	182824	0	0	0
T13	202357	0	0	0
T14	183648	0	0	0
T15	247033	0	0	0
T16	247262	0	0	0
T48	221137	0	0	0
T57	0	8	0	0
T75	0	6	0	0
T85	0	3	0	0
T94	0	15	0	0
T123	0	2	0	0
T167	0	14	0	0
T290	0	19	0	0
T293	0	5	0	0
T325	0	3	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1347279588	1482	0	0
T2	222958	4	0	0
T3	246929	2	0	0
T4	253206	0	0	0
T5	230590	0	0	0
T12	182824	0	0	0
T13	202357	0	0	0
T14	183648	0	0	0
T15	247033	0	0	0
T16	247262	0	0	0
T48	221137	0	0	0
T57	0	17	0	0
T75	0	7	0	0
T85	0	8	0	0
T94	0	20	0	0
T123	0	11	0	0
T167	0	5	0	0
T290	0	10	0	0
T293	0	1	0	0