Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
90.24	90.24	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	90.24	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.24	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	8	54	87.10

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	8	23	74.19	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1840

1

T1

22

T3

9

T6

8

auto[1]

672

1

T1

2

T3

3

T6

6

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1871

1

T1

22

T3

9

T6

11

auto[1]

641

1

T1

2

T3

3

T6

3

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1913

1

T1

20

T3

6

T6

9

auto[1]

599

1

T1

4

T3

6

T6

5

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1826

1

T1

22

T3

12

T6

2

auto[1]

686

1

T1

2

T6

12

T7

1

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2294

1

T1

19

T3

12

T6

14

auto[1]

218

1

T1

5

T53

10

T75

13

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2294

1

T1

20

T3

12

T6

14

auto[1]

218

1

T1

4

T9

3

T33

4

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2397

1

T1

24

T3

12

T6

14

auto[1]

115

1

T33

2

T65

3

T117

2

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2328

1

T1

21

T3

9

T6

14

auto[1]

184

1

T1

3

T3

3

T9

2

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2359

1

T1

18

T3

9

T6

14

auto[1]

153

1

T1

6

T3

3

T9

3

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1809

1

T1

21

T3

12

T6

11

auto[1]

703

1

T1

3

T6

3

T7

1

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	8	23	74.19	8
Automatically Generated Cross Bins	31	8	23	74.19	8
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	*	--	--	2
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel

cp_precondition_key1_in_sel

cp_precondition_key2_in_sel

cp_precondition_pwrb_in_sel

cp_precondition_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1017

1

T6

11

T7

5

T8

6

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

67

1

T231

7

T197

2

T213

6

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

54

1

T3

3

T75

3

T348

5

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

20

1

T1

2

T75

3

T213

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

68

1

T3

3

T9

2

T259

8

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

21

1

T1

3

T75

4

T127

6

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

17

1

T308

12

T358

1

T359

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

11

1

T53

3

T231

3

T260

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

24

1

T65

3

T344

3

T103

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

19

1

T360

2

T128

1

T328

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

3

1

T361

2

T362

1

-

-

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

1

1

T363

1

-

-

-

-

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

18

1

T33

2

T76

3

T103

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

3

1

T364

3

-

-

-

-

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

5

1

T365

4

T366

1

-

-

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

90

1

T33

4

T53

7

T231

8

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

36

1

T53

5

T259

1

T344

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

13

1

T1

4

T9

3

T260

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

8

1

T190

4

T327

1

T367

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

21

1

T238

2

T76

3

T354

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

17

1

T117

2

T367

1

T357

4

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

9

1

T127

6

T355

3

-

-

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

2

1

T354

1

T368

1

-

-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

128

1

T1

2

T9

2

T284

9

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

97

1

T1

3

T53

5

T180

11

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

57

1

T72

2

T197

2

T350

4

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

130

1

T6

8

T12

6

T261

6

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

50

1

T258

5

T369

6

T370

6

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

104

1

T10

1

T12

5

T84

5

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

43

1

T180

7

T89

4

T371

19

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

107

1

T1

2

T9

3

T53

7

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

66

1

T3

3

T8

4

T37

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

52

1

T33

4

T180

4

T279

5

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

32

1

T271

3

T34

2

T76

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

35

1

T103

1

T372

3

T213

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

33

1

T34

3

T231

8

T260

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

10

1

T180

5

T346

3

T345

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

17

1

T180

1

T373

2

T372

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

73

1

T75

4

T260

3

T348

5

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

77

1

T308

12

T91

5

T374

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

71

1

T33

2

T65

3

T261

5

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

30

1

T180

4

T261

4

T76

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

52

1

T34

5

T75

3

T375

7

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

32

1

T12

1

T84

3

T284

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

47

1

T8

2

T375

4

T91

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

11

1

T6

1

T7

1

T376

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

57

1

T3

3

T12

5

T53

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

26

1

T7

4

T377

2

T263

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

42

1

T84

3

T238

2

T309

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

13

1

T6

2

T271

1

T378

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

21

1

T1

2

T90

3

T197

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

8

1

T134

3

T357

3

T351

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

18

1

T180

2

T232

3

T378

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

5

1

T162

3

T283

2

-

-

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded