Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.90 99.31 96.76 100.00 96.79 98.74 99.52 94.15


Total tests in report: 913
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
59.98 59.98 79.21 79.21 68.25 68.25 90.75 90.75 20.51 20.51 79.56 79.56 69.27 69.27 12.34 12.34 /workspace/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.2780481492
78.39 18.40 90.37 11.16 83.57 15.32 93.04 2.28 53.21 32.69 90.57 11.02 86.51 17.24 51.44 39.10 /workspace/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.1234342978
85.37 6.98 95.45 5.08 89.33 5.76 95.55 2.51 67.31 14.10 95.23 4.66 93.55 7.03 61.15 9.71 /workspace/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.1968556106
89.02 3.65 96.51 1.06 90.44 1.11 95.55 0.00 75.64 8.33 96.19 0.96 96.34 2.79 72.45 11.30 /workspace/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.3713677128
91.27 2.25 97.72 1.21 92.19 1.74 95.55 0.00 87.18 11.54 97.41 1.22 96.34 0.00 72.50 0.05 /workspace/coverage/default/1.sysrst_ctrl_feature_disable.893994247
92.46 1.19 97.80 0.07 93.38 1.19 96.23 0.68 87.18 0.00 97.52 0.11 96.44 0.10 78.64 6.14 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.3685576854
93.34 0.88 98.23 0.43 93.98 0.61 98.17 1.94 87.18 0.00 97.67 0.15 96.63 0.19 81.52 2.87 /workspace/coverage/default/26.sysrst_ctrl_stress_all_with_rand_reset.2947728050
93.84 0.50 98.41 0.19 94.08 0.10 98.17 0.00 89.74 2.56 97.82 0.15 97.01 0.39 81.62 0.10 /workspace/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.1965550488
94.29 0.45 98.47 0.06 94.19 0.10 98.17 0.00 90.38 0.64 97.89 0.07 97.30 0.29 83.60 1.98 /workspace/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.3819659979
94.60 0.31 98.49 0.02 94.31 0.13 98.17 0.00 90.38 0.00 97.93 0.04 97.30 0.00 85.58 1.98 /workspace/coverage/default/5.sysrst_ctrl_stress_all.2001519849
94.88 0.28 98.49 0.00 94.34 0.03 99.77 1.60 90.38 0.00 97.93 0.00 97.40 0.10 85.83 0.25 /workspace/coverage/default/0.sysrst_ctrl_sec_cm.764742446
95.12 0.24 98.56 0.07 94.39 0.05 99.77 0.00 91.67 1.28 98.00 0.07 97.59 0.19 85.83 0.00 /workspace/coverage/default/17.sysrst_ctrl_ultra_low_pwr.43770775
95.36 0.24 98.64 0.07 94.44 0.05 99.77 0.00 92.95 1.28 98.08 0.07 97.78 0.19 85.83 0.00 /workspace/coverage/default/37.sysrst_ctrl_edge_detect.3972300197
95.57 0.21 98.68 0.04 94.46 0.03 99.77 0.00 93.59 0.64 98.11 0.04 97.88 0.10 86.47 0.64 /workspace/coverage/default/11.sysrst_ctrl_stress_all_with_rand_reset.3420272988
95.76 0.19 98.68 0.00 95.27 0.81 99.77 0.00 93.59 0.00 98.11 0.00 97.98 0.10 86.92 0.45 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.2070644061
95.93 0.17 98.77 0.09 95.30 0.03 99.77 0.00 93.59 0.00 98.11 0.00 97.98 0.00 87.96 1.04 /workspace/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.1599941877
96.09 0.16 98.77 0.00 95.40 0.10 99.77 0.00 93.59 0.00 98.11 0.00 98.55 0.58 88.40 0.45 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.3667814364
96.23 0.15 98.79 0.02 95.42 0.03 99.77 0.00 93.59 0.00 98.11 0.00 98.65 0.10 89.30 0.89 /workspace/coverage/default/47.sysrst_ctrl_combo_detect.4122508486
96.37 0.14 98.86 0.07 95.45 0.03 99.77 0.00 94.23 0.64 98.23 0.11 98.75 0.10 89.30 0.00 /workspace/coverage/default/27.sysrst_ctrl_edge_detect.192791978
96.50 0.13 98.92 0.06 95.48 0.03 99.77 0.00 94.87 0.64 98.30 0.07 98.84 0.10 89.30 0.00 /workspace/coverage/default/9.sysrst_ctrl_edge_detect.3585736883
96.62 0.12 98.96 0.04 95.50 0.03 99.77 0.00 95.51 0.64 98.34 0.04 98.94 0.10 89.30 0.00 /workspace/coverage/default/11.sysrst_ctrl_edge_detect.3386046936
96.74 0.12 98.99 0.04 95.53 0.03 99.77 0.00 96.15 0.64 98.37 0.04 99.04 0.10 89.30 0.00 /workspace/coverage/default/41.sysrst_ctrl_edge_detect.4145719912
96.86 0.12 99.03 0.04 95.55 0.03 99.77 0.00 96.79 0.64 98.41 0.04 99.13 0.10 89.30 0.00 /workspace/coverage/default/48.sysrst_ctrl_edge_detect.798840830
96.94 0.08 99.07 0.04 95.55 0.00 99.77 0.00 96.79 0.00 98.41 0.00 99.13 0.00 89.84 0.55 /workspace/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.2766142100
97.01 0.07 99.09 0.02 95.55 0.00 99.77 0.00 96.79 0.00 98.41 0.00 99.13 0.00 90.34 0.50 /workspace/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.2471447912
97.08 0.07 99.12 0.04 95.70 0.15 99.77 0.00 96.79 0.00 98.48 0.07 99.33 0.19 90.34 0.00 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.3560849930
97.14 0.07 99.14 0.02 96.01 0.30 99.77 0.00 96.79 0.00 98.52 0.04 99.42 0.10 90.34 0.00 /workspace/coverage/default/26.sysrst_ctrl_ultra_low_pwr.2299722482
97.20 0.06 99.14 0.00 96.03 0.03 99.77 0.00 96.79 0.00 98.52 0.00 99.52 0.10 90.63 0.30 /workspace/coverage/default/16.sysrst_ctrl_combo_detect.2428934032
97.26 0.05 99.14 0.00 96.41 0.38 99.77 0.00 96.79 0.00 98.52 0.00 99.52 0.00 90.63 0.00 /workspace/coverage/default/0.sysrst_ctrl_feature_disable.4272959927
97.31 0.05 99.20 0.06 96.49 0.08 100.00 0.23 96.79 0.00 98.52 0.00 99.52 0.00 90.63 0.00 /workspace/coverage/default/1.sysrst_ctrl_alert_test.1326917762
97.36 0.05 99.20 0.00 96.49 0.00 100.00 0.00 96.79 0.00 98.52 0.00 99.52 0.00 90.98 0.35 /workspace/coverage/default/38.sysrst_ctrl_combo_detect_with_pre_cond.4244355637
97.40 0.04 99.20 0.00 96.49 0.00 100.00 0.00 96.79 0.00 98.52 0.00 99.52 0.00 91.28 0.30 /workspace/coverage/default/27.sysrst_ctrl_stress_all.2521303447
97.43 0.04 99.20 0.00 96.49 0.00 100.00 0.00 96.79 0.00 98.52 0.00 99.52 0.00 91.53 0.25 /workspace/coverage/default/21.sysrst_ctrl_combo_detect_with_pre_cond.853818284
97.47 0.04 99.20 0.00 96.49 0.00 100.00 0.00 96.79 0.00 98.52 0.00 99.52 0.00 91.77 0.25 /workspace/coverage/default/29.sysrst_ctrl_stress_all_with_rand_reset.3466331284
97.51 0.04 99.20 0.00 96.49 0.00 100.00 0.00 96.79 0.00 98.52 0.00 99.52 0.00 92.02 0.25 /workspace/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.1362650327
97.53 0.03 99.20 0.00 96.49 0.00 100.00 0.00 96.79 0.00 98.52 0.00 99.52 0.00 92.22 0.20 /workspace/coverage/default/5.sysrst_ctrl_combo_detect.1220901529
97.56 0.03 99.20 0.00 96.49 0.00 100.00 0.00 96.79 0.00 98.52 0.00 99.52 0.00 92.42 0.20 /workspace/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.3686530856
97.59 0.03 99.20 0.00 96.66 0.18 100.00 0.00 96.79 0.00 98.52 0.00 99.52 0.00 92.42 0.00 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.3496523774
97.61 0.02 99.20 0.00 96.66 0.00 100.00 0.00 96.79 0.00 98.52 0.00 99.52 0.00 92.57 0.15 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.1686664830
97.63 0.02 99.20 0.00 96.66 0.00 100.00 0.00 96.79 0.00 98.52 0.00 99.52 0.00 92.72 0.15 /workspace/coverage/default/13.sysrst_ctrl_combo_detect_with_pre_cond.67666891
97.65 0.02 99.20 0.00 96.66 0.00 100.00 0.00 96.79 0.00 98.52 0.00 99.52 0.00 92.86 0.15 /workspace/coverage/default/24.sysrst_ctrl_stress_all_with_rand_reset.272109949
97.67 0.02 99.20 0.00 96.69 0.03 100.00 0.00 96.79 0.00 98.52 0.00 99.52 0.00 92.96 0.10 /workspace/coverage/default/22.sysrst_ctrl_stress_all.119631202
97.69 0.02 99.23 0.04 96.69 0.00 100.00 0.00 96.79 0.00 98.60 0.07 99.52 0.00 92.96 0.00 /workspace/coverage/default/31.sysrst_ctrl_stress_all.2033359508
97.70 0.01 99.23 0.00 96.69 0.00 100.00 0.00 96.79 0.00 98.60 0.00 99.52 0.00 93.06 0.10 /workspace/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.1841208892
97.71 0.01 99.23 0.00 96.69 0.00 100.00 0.00 96.79 0.00 98.60 0.00 99.52 0.00 93.16 0.10 /workspace/coverage/default/10.sysrst_ctrl_stress_all_with_rand_reset.564940375
97.73 0.01 99.23 0.00 96.69 0.00 100.00 0.00 96.79 0.00 98.60 0.00 99.52 0.00 93.26 0.10 /workspace/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.1773337742
97.74 0.01 99.23 0.00 96.69 0.00 100.00 0.00 96.79 0.00 98.60 0.00 99.52 0.00 93.36 0.10 /workspace/coverage/default/15.sysrst_ctrl_combo_detect_with_pre_cond.2287688553
97.76 0.01 99.23 0.00 96.69 0.00 100.00 0.00 96.79 0.00 98.60 0.00 99.52 0.00 93.46 0.10 /workspace/coverage/default/37.sysrst_ctrl_stress_all.145922765
97.77 0.01 99.23 0.00 96.69 0.00 100.00 0.00 96.79 0.00 98.60 0.00 99.52 0.00 93.56 0.10 /workspace/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.1861445443
97.78 0.01 99.23 0.00 96.71 0.03 100.00 0.00 96.79 0.00 98.60 0.00 99.52 0.00 93.61 0.05 /workspace/coverage/default/2.sysrst_ctrl_combo_detect_with_pre_cond.274197135
97.79 0.01 99.25 0.02 96.71 0.00 100.00 0.00 96.79 0.00 98.63 0.04 99.52 0.00 93.61 0.00 /workspace/coverage/default/2.sysrst_ctrl_edge_detect.372148159
97.80 0.01 99.27 0.02 96.71 0.00 100.00 0.00 96.79 0.00 98.67 0.04 99.52 0.00 93.61 0.00 /workspace/coverage/default/25.sysrst_ctrl_stress_all_with_rand_reset.2391431688
97.80 0.01 99.29 0.02 96.71 0.00 100.00 0.00 96.79 0.00 98.71 0.04 99.52 0.00 93.61 0.00 /workspace/coverage/default/34.sysrst_ctrl_stress_all_with_rand_reset.2053188177
97.81 0.01 99.31 0.02 96.71 0.00 100.00 0.00 96.79 0.00 98.74 0.04 99.52 0.00 93.61 0.00 /workspace/coverage/default/36.sysrst_ctrl_stress_all_with_rand_reset.1370584249
97.82 0.01 99.31 0.00 96.71 0.00 100.00 0.00 96.79 0.00 98.74 0.00 99.52 0.00 93.66 0.05 /workspace/coverage/default/10.sysrst_ctrl_combo_detect.980818712
97.83 0.01 99.31 0.00 96.71 0.00 100.00 0.00 96.79 0.00 98.74 0.00 99.52 0.00 93.71 0.05 /workspace/coverage/default/14.sysrst_ctrl_pin_override_test.4267244326
97.83 0.01 99.31 0.00 96.71 0.00 100.00 0.00 96.79 0.00 98.74 0.00 99.52 0.00 93.76 0.05 /workspace/coverage/default/15.sysrst_ctrl_combo_detect.3337187235
97.84 0.01 99.31 0.00 96.71 0.00 100.00 0.00 96.79 0.00 98.74 0.00 99.52 0.00 93.81 0.05 /workspace/coverage/default/30.sysrst_ctrl_combo_detect.2507050694
97.85 0.01 99.31 0.00 96.71 0.00 100.00 0.00 96.79 0.00 98.74 0.00 99.52 0.00 93.86 0.05 /workspace/coverage/default/30.sysrst_ctrl_combo_detect_with_pre_cond.3126522653
97.85 0.01 99.31 0.00 96.71 0.00 100.00 0.00 96.79 0.00 98.74 0.00 99.52 0.00 93.90 0.05 /workspace/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.3002826357
97.86 0.01 99.31 0.00 96.71 0.00 100.00 0.00 96.79 0.00 98.74 0.00 99.52 0.00 93.95 0.05 /workspace/coverage/default/36.sysrst_ctrl_combo_detect_with_pre_cond.3918494063
97.87 0.01 99.31 0.00 96.71 0.00 100.00 0.00 96.79 0.00 98.74 0.00 99.52 0.00 94.00 0.05 /workspace/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.2809952768
97.88 0.01 99.31 0.00 96.71 0.00 100.00 0.00 96.79 0.00 98.74 0.00 99.52 0.00 94.05 0.05 /workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.2504946396
97.88 0.01 99.31 0.00 96.71 0.00 100.00 0.00 96.79 0.00 98.74 0.00 99.52 0.00 94.10 0.05 /workspace/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.995728413
97.89 0.01 99.31 0.00 96.71 0.00 100.00 0.00 96.79 0.00 98.74 0.00 99.52 0.00 94.15 0.05 /workspace/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.571687613
97.89 0.01 99.31 0.00 96.74 0.03 100.00 0.00 96.79 0.00 98.74 0.00 99.52 0.00 94.15 0.00 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.1483184668

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.201298654
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.2725644627
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.1618714414
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.3089080850
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.1523016346
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.609541509
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.4159942419
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.1749502729
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.2475321709
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.4064815649
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.1267178012
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.307593770
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.401410742
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.4018848405
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.3808834750
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.3395243798
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.604327542
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.2023329216
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.333448546
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.3320835554
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.3205524924
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.184073401
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.1625066530
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.1843525963
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.1787600562
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.3488077419
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.1528833376
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.3272299922
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.1616571577
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.2000183995
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.510566738
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.3037668644
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.2384413940
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.1266359192
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.4215654387
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.2704322283
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.650404788
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.2269776956
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.1442711410
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.3388301939
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.1190612103
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.152149117
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.1752869931
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.1792174166
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.1292724650
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.3112040123
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.288416010
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.3835479158
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.2849868224
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.4079868814
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.950085426
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.3958750353
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.1362344697
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.2626270838
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.2608891036
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.3278560299
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.3012453496
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.3386296898
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.412395224
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.1187004259
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.1026878106
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.2133862709
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.664908867
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.3730625346
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.727842922
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.3497154297
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.158492030
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.101836931
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.1681583452
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.2726761702
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.2405146166
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.1201514103
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.3288457430
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.749467772
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.2604260131
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.3794569692
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.3965946654
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.3128087219
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.3676431122
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.1225111007
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.3643928379
/workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.874394788
/workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.921696390
/workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.3553326349
/workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.1988357017
/workspace/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.2133853988
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/workspace/coverage/default/42.sysrst_ctrl_alert_test.828000557
/workspace/coverage/default/42.sysrst_ctrl_auto_blk_key_output.2130755911
/workspace/coverage/default/42.sysrst_ctrl_combo_detect.2150652231
/workspace/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.3790710701
/workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.2390355681
/workspace/coverage/default/42.sysrst_ctrl_edge_detect.3258389597
/workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.3311291934
/workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.3634775575
/workspace/coverage/default/42.sysrst_ctrl_pin_access_test.3287005297
/workspace/coverage/default/42.sysrst_ctrl_pin_override_test.1762746968
/workspace/coverage/default/42.sysrst_ctrl_smoke.774935008
/workspace/coverage/default/42.sysrst_ctrl_stress_all.239537840
/workspace/coverage/default/42.sysrst_ctrl_ultra_low_pwr.1149306156
/workspace/coverage/default/43.sysrst_ctrl_alert_test.2732225578
/workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.1808227595
/workspace/coverage/default/43.sysrst_ctrl_combo_detect.807388042
/workspace/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.3867818173
/workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.2407044799
/workspace/coverage/default/43.sysrst_ctrl_edge_detect.2796354132
/workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.4029492072
/workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.3594993233
/workspace/coverage/default/43.sysrst_ctrl_pin_access_test.2122881509
/workspace/coverage/default/43.sysrst_ctrl_pin_override_test.2971602129
/workspace/coverage/default/43.sysrst_ctrl_smoke.2863432323
/workspace/coverage/default/43.sysrst_ctrl_stress_all.2684281917
/workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.2732999630
/workspace/coverage/default/44.sysrst_ctrl_alert_test.3543490740
/workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.1629165987
/workspace/coverage/default/44.sysrst_ctrl_combo_detect.3326902258
/workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.2363452730
/workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.605344934
/workspace/coverage/default/44.sysrst_ctrl_edge_detect.133062787
/workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.1399961590
/workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.96750658
/workspace/coverage/default/44.sysrst_ctrl_pin_access_test.2724007007
/workspace/coverage/default/44.sysrst_ctrl_pin_override_test.1131406801
/workspace/coverage/default/44.sysrst_ctrl_smoke.3711888375
/workspace/coverage/default/44.sysrst_ctrl_stress_all.865094568
/workspace/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.2536726462
/workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.410459503
/workspace/coverage/default/45.sysrst_ctrl_alert_test.3896224708
/workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.3801114038
/workspace/coverage/default/45.sysrst_ctrl_combo_detect.2023697673
/workspace/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.1768498243
/workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.3004100894
/workspace/coverage/default/45.sysrst_ctrl_edge_detect.2197771591
/workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.1322628163
/workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.2062367340
/workspace/coverage/default/45.sysrst_ctrl_pin_access_test.1738284187
/workspace/coverage/default/45.sysrst_ctrl_pin_override_test.3517745781
/workspace/coverage/default/45.sysrst_ctrl_smoke.2983136854
/workspace/coverage/default/45.sysrst_ctrl_stress_all.1867283038
/workspace/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.3030596769
/workspace/coverage/default/45.sysrst_ctrl_ultra_low_pwr.3477561428
/workspace/coverage/default/46.sysrst_ctrl_alert_test.1983389153
/workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.858564187
/workspace/coverage/default/46.sysrst_ctrl_combo_detect.2376989912
/workspace/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.418504702
/workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.2692418615
/workspace/coverage/default/46.sysrst_ctrl_edge_detect.1506263558
/workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.1684109698
/workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.2063239001
/workspace/coverage/default/46.sysrst_ctrl_pin_access_test.2266844291
/workspace/coverage/default/46.sysrst_ctrl_pin_override_test.1921054517
/workspace/coverage/default/46.sysrst_ctrl_smoke.2003290015
/workspace/coverage/default/46.sysrst_ctrl_stress_all.2676236545
/workspace/coverage/default/47.sysrst_ctrl_alert_test.3734477378
/workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.2285257288
/workspace/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.877711521
/workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.3795936459
/workspace/coverage/default/47.sysrst_ctrl_edge_detect.2539702348
/workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.3002012650
/workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.2298754960
/workspace/coverage/default/47.sysrst_ctrl_pin_access_test.3004530083
/workspace/coverage/default/47.sysrst_ctrl_pin_override_test.2905305091
/workspace/coverage/default/47.sysrst_ctrl_smoke.2777549592
/workspace/coverage/default/47.sysrst_ctrl_stress_all.3787872382
/workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.3885300282
/workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.3617001809
/workspace/coverage/default/48.sysrst_ctrl_alert_test.3374168800
/workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.2670086751
/workspace/coverage/default/48.sysrst_ctrl_combo_detect.1298795839
/workspace/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.4183589191
/workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.2702682674
/workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.3585976682
/workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.158326068
/workspace/coverage/default/48.sysrst_ctrl_pin_access_test.1587430315
/workspace/coverage/default/48.sysrst_ctrl_pin_override_test.344071169
/workspace/coverage/default/48.sysrst_ctrl_smoke.1352144166
/workspace/coverage/default/48.sysrst_ctrl_stress_all.1051278951
/workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.2867846748
/workspace/coverage/default/49.sysrst_ctrl_alert_test.745379735
/workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.2145237459
/workspace/coverage/default/49.sysrst_ctrl_combo_detect.3586673400
/workspace/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.4198832479
/workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.3184196200
/workspace/coverage/default/49.sysrst_ctrl_edge_detect.2332684705
/workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.3262026639
/workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.1665366674
/workspace/coverage/default/49.sysrst_ctrl_pin_access_test.3199141772
/workspace/coverage/default/49.sysrst_ctrl_pin_override_test.2595987871
/workspace/coverage/default/49.sysrst_ctrl_smoke.4207751915
/workspace/coverage/default/49.sysrst_ctrl_stress_all.1201484767
/workspace/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.316501691
/workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.2966482275
/workspace/coverage/default/5.sysrst_ctrl_alert_test.4078762048
/workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.2360167923
/workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.946270256
/workspace/coverage/default/5.sysrst_ctrl_edge_detect.1219138189
/workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.2558645656
/workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.3440207316
/workspace/coverage/default/5.sysrst_ctrl_pin_access_test.3566978206
/workspace/coverage/default/5.sysrst_ctrl_pin_override_test.2407173345
/workspace/coverage/default/5.sysrst_ctrl_smoke.1517440035
/workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.2234591942
/workspace/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.354987096
/workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.1129652900
/workspace/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.3626845589
/workspace/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.4281435236
/workspace/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.4286201344
/workspace/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.1230866829
/workspace/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.3067468435
/workspace/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.2874962101
/workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.3013237310
/workspace/coverage/default/6.sysrst_ctrl_alert_test.2038353616
/workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.3460447520
/workspace/coverage/default/6.sysrst_ctrl_combo_detect.1148276290
/workspace/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.1994055573
/workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.2177001843
/workspace/coverage/default/6.sysrst_ctrl_edge_detect.2488884437
/workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.162636499
/workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.254612843
/workspace/coverage/default/6.sysrst_ctrl_pin_access_test.2308497631
/workspace/coverage/default/6.sysrst_ctrl_pin_override_test.3838721095
/workspace/coverage/default/6.sysrst_ctrl_smoke.2729453275
/workspace/coverage/default/6.sysrst_ctrl_stress_all.3596202370
/workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.132677757
/workspace/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.2542523192
/workspace/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.3361377935
/workspace/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.3202590880
/workspace/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.1449740771
/workspace/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.2764984250
/workspace/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.1202553794
/workspace/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.1338058115
/workspace/coverage/default/7.sysrst_ctrl_alert_test.1673922635
/workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.1162067936
/workspace/coverage/default/7.sysrst_ctrl_combo_detect.1839009319
/workspace/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.3552974929
/workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.404637185
/workspace/coverage/default/7.sysrst_ctrl_edge_detect.3732737697
/workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.788967219
/workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.2378628722
/workspace/coverage/default/7.sysrst_ctrl_pin_access_test.1692181288
/workspace/coverage/default/7.sysrst_ctrl_pin_override_test.1450942411
/workspace/coverage/default/7.sysrst_ctrl_smoke.1948351377
/workspace/coverage/default/7.sysrst_ctrl_stress_all.2266843949
/workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.4032986293
/workspace/coverage/default/7.sysrst_ctrl_ultra_low_pwr.3885417043
/workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.1864580676
/workspace/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.109234845
/workspace/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.1882857443
/workspace/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.859049699
/workspace/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.215059423
/workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.2304417612
/workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.1654111243
/workspace/coverage/default/8.sysrst_ctrl_alert_test.330669147
/workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.2158284759
/workspace/coverage/default/8.sysrst_ctrl_combo_detect.3728004909
/workspace/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.2685907459
/workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.3461632095
/workspace/coverage/default/8.sysrst_ctrl_edge_detect.1438394425
/workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.328813400
/workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.4242225943
/workspace/coverage/default/8.sysrst_ctrl_pin_access_test.4010241194
/workspace/coverage/default/8.sysrst_ctrl_pin_override_test.2010057858
/workspace/coverage/default/8.sysrst_ctrl_smoke.1164488605
/workspace/coverage/default/8.sysrst_ctrl_stress_all.2711155854
/workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.3992389357
/workspace/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.3242291226
/workspace/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.1967040658
/workspace/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.3093255033
/workspace/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.163435358
/workspace/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.4205871055
/workspace/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.3534251130
/workspace/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.1623798373
/workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.1908329448
/workspace/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.3867779806
/workspace/coverage/default/9.sysrst_ctrl_alert_test.259965848
/workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.2602675417
/workspace/coverage/default/9.sysrst_ctrl_combo_detect.1040195236
/workspace/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.3910957127
/workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.687178638
/workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.3136688619
/workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.2362815724
/workspace/coverage/default/9.sysrst_ctrl_pin_access_test.2035141604
/workspace/coverage/default/9.sysrst_ctrl_pin_override_test.1561735957
/workspace/coverage/default/9.sysrst_ctrl_smoke.3995144578
/workspace/coverage/default/9.sysrst_ctrl_stress_all.1841938010
/workspace/coverage/default/9.sysrst_ctrl_ultra_low_pwr.1593425391
/workspace/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.658562111
/workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.1802838334
/workspace/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.1302227843
/workspace/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.3839045264
/workspace/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.3170802208



Total test records in report: 913
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T4 /workspace/coverage/default/38.sysrst_ctrl_auto_blk_key_output.361735770 Mar 31 01:21:16 PM PDT 24 Mar 31 01:22:28 PM PDT 24 26673041948 ps
T1 /workspace/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.2780481492 Mar 31 01:21:48 PM PDT 24 Mar 31 01:22:50 PM PDT 24 84950054489 ps
T5 /workspace/coverage/default/26.sysrst_ctrl_auto_blk_key_output.3382504501 Mar 31 01:20:39 PM PDT 24 Mar 31 01:21:18 PM PDT 24 59788150084 ps
T13 /workspace/coverage/default/1.sysrst_ctrl_in_out_inverted.1505184164 Mar 31 01:19:09 PM PDT 24 Mar 31 01:19:11 PM PDT 24 2464366782 ps
T2 /workspace/coverage/default/26.sysrst_ctrl_ultra_low_pwr.2299722482 Mar 31 01:20:40 PM PDT 24 Mar 31 01:20:47 PM PDT 24 4183918243 ps
T14 /workspace/coverage/default/3.sysrst_ctrl_ec_pwr_on_rst.448399650 Mar 31 01:19:23 PM PDT 24 Mar 31 01:19:33 PM PDT 24 3817598306 ps
T15 /workspace/coverage/default/2.sysrst_ctrl_ec_pwr_on_rst.1771217479 Mar 31 01:19:22 PM PDT 24 Mar 31 01:19:25 PM PDT 24 3536273462 ps
T3 /workspace/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.2766142100 Mar 31 01:21:42 PM PDT 24 Mar 31 01:24:12 PM PDT 24 56145634227 ps
T16 /workspace/coverage/default/21.sysrst_ctrl_alert_test.342087528 Mar 31 01:20:26 PM PDT 24 Mar 31 01:20:32 PM PDT 24 2013921120 ps
T17 /workspace/coverage/default/10.sysrst_ctrl_pin_access_test.3542745577 Mar 31 01:19:54 PM PDT 24 Mar 31 01:19:56 PM PDT 24 2128437917 ps
T6 /workspace/coverage/default/26.sysrst_ctrl_stress_all_with_rand_reset.2947728050 Mar 31 01:20:40 PM PDT 24 Mar 31 01:22:12 PM PDT 24 142131688890 ps
T22 /workspace/coverage/default/25.sysrst_ctrl_in_out_inverted.1480934459 Mar 31 01:20:37 PM PDT 24 Mar 31 01:20:39 PM PDT 24 2484597640 ps
T23 /workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.162636499 Mar 31 01:19:40 PM PDT 24 Mar 31 01:19:42 PM PDT 24 2627191592 ps
T61 /workspace/coverage/default/48.sysrst_ctrl_smoke.1352144166 Mar 31 01:21:35 PM PDT 24 Mar 31 01:21:37 PM PDT 24 2149759797 ps
T27 /workspace/coverage/default/10.sysrst_ctrl_combo_detect_with_pre_cond.2336262844 Mar 31 01:19:56 PM PDT 24 Mar 31 01:21:07 PM PDT 24 26832130458 ps
T32 /workspace/coverage/default/34.sysrst_ctrl_ultra_low_pwr.4225263755 Mar 31 01:21:03 PM PDT 24 Mar 31 01:21:07 PM PDT 24 5553962592 ps
T26 /workspace/coverage/default/22.sysrst_ctrl_auto_blk_key_output.2017311146 Mar 31 01:20:31 PM PDT 24 Mar 31 01:20:36 PM PDT 24 3710409117 ps
T24 /workspace/coverage/default/46.sysrst_ctrl_pin_override_test.1921054517 Mar 31 01:21:31 PM PDT 24 Mar 31 01:21:39 PM PDT 24 2511025965 ps
T58 /workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.3461632095 Mar 31 01:19:46 PM PDT 24 Mar 31 01:19:54 PM PDT 24 3012671143 ps
T48 /workspace/coverage/default/9.sysrst_ctrl_stress_all.1841938010 Mar 31 01:19:46 PM PDT 24 Mar 31 01:20:09 PM PDT 24 8338847470 ps
T62 /workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.2362815724 Mar 31 01:19:48 PM PDT 24 Mar 31 01:19:50 PM PDT 24 2482888902 ps
T49 /workspace/coverage/default/12.sysrst_ctrl_auto_blk_key_output.2113925028 Mar 31 01:20:01 PM PDT 24 Mar 31 01:20:03 PM PDT 24 3273976208 ps
T7 /workspace/coverage/default/36.sysrst_ctrl_combo_detect.2241524468 Mar 31 01:21:07 PM PDT 24 Mar 31 01:24:05 PM PDT 24 66148944564 ps
T8 /workspace/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.1968556106 Mar 31 01:21:23 PM PDT 24 Mar 31 01:23:33 PM PDT 24 197363330210 ps
T54 /workspace/coverage/default/6.sysrst_ctrl_pin_override_test.3838721095 Mar 31 01:19:36 PM PDT 24 Mar 31 01:19:39 PM PDT 24 2526891859 ps
T9 /workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.1908329448 Mar 31 01:21:48 PM PDT 24 Mar 31 01:25:55 PM PDT 24 94166360419 ps
T10 /workspace/coverage/default/27.sysrst_ctrl_combo_detect.3156167913 Mar 31 01:20:40 PM PDT 24 Mar 31 01:21:07 PM PDT 24 42954460389 ps
T50 /workspace/coverage/default/32.sysrst_ctrl_auto_blk_key_output.970761405 Mar 31 01:20:56 PM PDT 24 Mar 31 01:21:05 PM PDT 24 3252077943 ps
T47 /workspace/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.658562111 Mar 31 01:21:48 PM PDT 24 Mar 31 01:22:33 PM PDT 24 34849011232 ps
T55 /workspace/coverage/default/35.sysrst_ctrl_in_out_inverted.1259287801 Mar 31 01:21:03 PM PDT 24 Mar 31 01:21:11 PM PDT 24 2464083101 ps
T11 /workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.2234591942 Mar 31 01:19:35 PM PDT 24 Mar 31 01:19:42 PM PDT 24 5222680281 ps
T56 /workspace/coverage/default/39.sysrst_ctrl_pin_override_test.3706817539 Mar 31 01:21:16 PM PDT 24 Mar 31 01:21:17 PM PDT 24 2673869259 ps
T12 /workspace/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.1234342978 Mar 31 01:21:35 PM PDT 24 Mar 31 01:22:48 PM PDT 24 315183628213 ps
T25 /workspace/coverage/default/24.sysrst_ctrl_stress_all_with_rand_reset.272109949 Mar 31 01:20:36 PM PDT 24 Mar 31 01:22:15 PM PDT 24 38520716597 ps
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T235 /workspace/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.595072111 Mar 31 01:20:00 PM PDT 24 Mar 31 01:20:28 PM PDT 24 22638709035 ps
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T258 /workspace/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.4205871055 Mar 31 01:21:49 PM PDT 24 Mar 31 01:22:54 PM PDT 24 83917629285 ps
T423 /workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.2363452730 Mar 31 01:21:30 PM PDT 24 Mar 31 01:21:56 PM PDT 24 27091058073 ps
T320 /workspace/coverage/default/25.sysrst_ctrl_stress_all.3018466538 Mar 31 01:20:42 PM PDT 24 Mar 31 01:21:08 PM PDT 24 9279301133 ps
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T344 /workspace/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.1861445443 Mar 31 01:21:43 PM PDT 24 Mar 31 01:22:38 PM PDT 24 43684326664 ps
T425 /workspace/coverage/default/37.sysrst_ctrl_pin_override_test.3461705461 Mar 31 01:21:11 PM PDT 24 Mar 31 01:21:19 PM PDT 24 2509720342 ps
T397 /workspace/coverage/default/11.sysrst_ctrl_stress_all.3421391192 Mar 31 01:20:04 PM PDT 24 Mar 31 01:20:53 PM PDT 24 379272976715 ps
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T319 /workspace/coverage/default/26.sysrst_ctrl_in_out_inverted.3064950448 Mar 31 01:20:39 PM PDT 24 Mar 31 01:20:43 PM PDT 24 2474937950 ps
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T433 /workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.3004100894 Mar 31 01:21:27 PM PDT 24 Mar 31 01:21:29 PM PDT 24 4938224363 ps
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T435 /workspace/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.119515911 Mar 31 01:20:47 PM PDT 24 Mar 31 01:20:55 PM PDT 24 2609271159 ps
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T39 /workspace/coverage/default/23.sysrst_ctrl_stress_all.3748000464 Mar 31 01:20:35 PM PDT 24 Mar 31 01:21:25 PM PDT 24 17402901447 ps
T287 /workspace/coverage/default/0.sysrst_ctrl_sec_cm.764742446 Mar 31 01:19:08 PM PDT 24 Mar 31 01:20:01 PM PDT 24 22052163525 ps
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T308 /workspace/coverage/default/30.sysrst_ctrl_combo_detect_with_pre_cond.3126522653 Mar 31 01:20:49 PM PDT 24 Mar 31 01:22:27 PM PDT 24 147722989007 ps
T309 /workspace/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.3093255033 Mar 31 01:21:47 PM PDT 24 Mar 31 01:22:27 PM PDT 24 66450535480 ps
T69 /workspace/coverage/default/1.sysrst_ctrl_feature_disable.893994247 Mar 31 01:19:15 PM PDT 24 Mar 31 01:19:26 PM PDT 24 34785747827 ps
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T189 /workspace/coverage/default/29.sysrst_ctrl_stress_all_with_rand_reset.3466331284 Mar 31 01:20:49 PM PDT 24 Mar 31 01:22:47 PM PDT 24 46551725438 ps
T70 /workspace/coverage/default/3.sysrst_ctrl_ultra_low_pwr.1515486486 Mar 31 01:19:26 PM PDT 24 Mar 31 01:19:29 PM PDT 24 5227536483 ps
T35 /workspace/coverage/default/29.sysrst_ctrl_edge_detect.3687401303 Mar 31 01:20:54 PM PDT 24 Mar 31 01:21:03 PM PDT 24 3657664255 ps
T190 /workspace/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.418504702 Mar 31 01:21:37 PM PDT 24 Mar 31 01:22:08 PM PDT 24 44726884013 ps
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T40 /workspace/coverage/default/18.sysrst_ctrl_stress_all.860412106 Mar 31 01:20:13 PM PDT 24 Mar 31 01:20:22 PM PDT 24 12251214690 ps
T250 /workspace/coverage/default/30.sysrst_ctrl_flash_wr_prot_out.1045019228 Mar 31 01:20:49 PM PDT 24 Mar 31 01:20:54 PM PDT 24 2616391085 ps
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T252 /workspace/coverage/default/40.sysrst_ctrl_combo_detect.942751641 Mar 31 01:21:19 PM PDT 24 Mar 31 01:21:42 PM PDT 24 32752167289 ps
T253 /workspace/coverage/default/21.sysrst_ctrl_pin_access_test.3359541768 Mar 31 01:20:28 PM PDT 24 Mar 31 01:20:34 PM PDT 24 2059073312 ps
T254 /workspace/coverage/default/17.sysrst_ctrl_pin_access_test.3972023878 Mar 31 01:20:15 PM PDT 24 Mar 31 01:20:21 PM PDT 24 2228299511 ps
T118 /workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.3617001809 Mar 31 01:21:33 PM PDT 24 Mar 31 01:21:35 PM PDT 24 5450285392 ps
T437 /workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.1162067936 Mar 31 01:19:41 PM PDT 24 Mar 31 01:19:52 PM PDT 24 3499834282 ps
T438 /workspace/coverage/default/37.sysrst_ctrl_in_out_inverted.2832844282 Mar 31 01:21:08 PM PDT 24 Mar 31 01:21:16 PM PDT 24 2462830504 ps
T36 /workspace/coverage/default/18.sysrst_ctrl_stress_all_with_rand_reset.1847679509 Mar 31 01:20:15 PM PDT 24 Mar 31 01:22:12 PM PDT 24 44731180979 ps
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T102 /workspace/coverage/default/13.sysrst_ctrl_flash_wr_prot_out.2616769196 Mar 31 01:20:01 PM PDT 24 Mar 31 01:20:03 PM PDT 24 2629123335 ps
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T105 /workspace/coverage/default/20.sysrst_ctrl_auto_blk_key_output.1796372293 Mar 31 01:20:22 PM PDT 24 Mar 31 01:20:26 PM PDT 24 3401039246 ps
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T346 /workspace/coverage/default/34.sysrst_ctrl_stress_all.588801397 Mar 31 01:21:01 PM PDT 24 Mar 31 01:22:48 PM PDT 24 149554081858 ps
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T469 /workspace/coverage/default/1.sysrst_ctrl_ec_pwr_on_rst.3973312988 Mar 31 01:19:15 PM PDT 24 Mar 31 01:19:17 PM PDT 24 2908653002 ps
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T395 /workspace/coverage/default/31.sysrst_ctrl_stress_all_with_rand_reset.2412383020 Mar 31 01:20:56 PM PDT 24 Mar 31 01:21:24 PM PDT 24 181944011427 ps
T312 /workspace/coverage/default/35.sysrst_ctrl_auto_blk_key_output.2662684542 Mar 31 01:21:03 PM PDT 24 Mar 31 01:21:12 PM PDT 24 3317407309 ps
T471 /workspace/coverage/default/35.sysrst_ctrl_ec_pwr_on_rst.1998968506 Mar 31 01:21:02 PM PDT 24 Mar 31 01:21:06 PM PDT 24 4364454009 ps
T472 /workspace/coverage/default/3.sysrst_ctrl_flash_wr_prot_out.3967780666 Mar 31 01:19:22 PM PDT 24 Mar 31 01:19:25 PM PDT 24 2635001989 ps
T473 /workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.2158284759 Mar 31 01:19:49 PM PDT 24 Mar 31 01:19:52 PM PDT 24 3269781559 ps
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T391 /workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.2732999630 Mar 31 01:21:24 PM PDT 24 Mar 31 01:21:57 PM PDT 24 493379099228 ps
T474 /workspace/coverage/default/45.sysrst_ctrl_pin_access_test.1738284187 Mar 31 01:21:29 PM PDT 24 Mar 31 01:21:34 PM PDT 24 2232624737 ps
T73 /workspace/coverage/default/27.sysrst_ctrl_edge_detect.192791978 Mar 31 01:20:42 PM PDT 24 Mar 31 01:20:50 PM PDT 24 2819123982 ps
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