Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1134

1

T24

12

T8

3

T54

6

auto[1]

1161

1

T24

8

T8

5

T54

14

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

526

1

T24

5

T8

2

T54

6

from_0to1

537

1

T24

6

T8

1

T54

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1133

1

T24

11

T8

7

T54

11

auto[1]

1162

1

T24

9

T8

1

T54

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1129

1

T24

10

T8

1

T54

12

auto[1]

1166

1

T24

10

T8

7

T54

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

57

1

T24

1

T56

2

T12

3

auto[0]

from_1to0

auto[0]

auto[1]

68

1

T8

1

T54

1

T56

1

auto[0]

from_1to0

auto[1]

auto[0]

66

1

T24

1

T54

2

T56

1

auto[0]

from_1to0

auto[1]

auto[1]

63

1

T12

4

T63

1

T275

1

auto[0]

from_0to1

auto[0]

auto[0]

65

1

T24

1

T12

3

T59

1

auto[0]

from_0to1

auto[0]

auto[1]

80

1

T24

3

T56

1

T12

4

auto[0]

from_0to1

auto[1]

auto[0]

69

1

T54

1

T56

1

T12

3

auto[0]

from_0to1

auto[1]

auto[1]

66

1

T56

1

T12

1

T63

1

auto[1]

from_1to0

auto[0]

auto[0]

63

1

T54

1

T12

3

T59

2

auto[1]

from_1to0

auto[0]

auto[1]

70

1

T24

2

T54

2

T12

5

auto[1]

from_1to0

auto[1]

auto[0]

68

1

T24

1

T56

1

T63

3

auto[1]

from_1to0

auto[1]

auto[1]

71

1

T8

1

T56

1

T12

3

auto[1]

from_0to1

auto[0]

auto[0]

64

1

T54

1

T56

1

T12

2

auto[1]

from_0to1

auto[0]

auto[1]

62

1

T24

1

T8

1

T54

2

auto[1]

from_0to1

auto[1]

auto[0]

66

1

T24

1

T54

2

T56

1

auto[1]

from_0to1

auto[1]

auto[1]

65

1

T56

1

T12

4

T63

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1118

1

T24

9

T8

3

T54

9

auto[1]

1177

1

T24

11

T8

5

T54

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

552

1

T24

5

T8

2

T54

4

from_0to1

548

1

T24

5

T8

1

T54

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1146

1

T24

9

T8

6

T54

14

auto[1]

1149

1

T24

11

T8

2

T54

6

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1134

1

T24

12

T8

2

T54

10

auto[1]

1161

1

T24

8

T8

6

T54

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

70

1

T24

1

T54

2

T12

2

auto[0]

from_1to0

auto[0]

auto[1]

72

1

T54

2

T63

1

T59

1

auto[0]

from_1to0

auto[1]

auto[0]

73

1

T12

1

T63

1

T59

2

auto[0]

from_1to0

auto[1]

auto[1]

73

1

T24

1

T12

4

T63

1

auto[0]

from_0to1

auto[0]

auto[0]

72

1

T56

1

T12

1

T63

1

auto[0]

from_0to1

auto[0]

auto[1]

48

1

T12

1

T59

1

T179

1

auto[0]

from_0to1

auto[1]

auto[0]

73

1

T24

2

T54

1

T56

1

auto[0]

from_0to1

auto[1]

auto[1]

70

1

T12

3

T63

1

T398

2

auto[1]

from_1to0

auto[0]

auto[0]

69

1

T24

1

T12

3

T25

1

auto[1]

from_1to0

auto[0]

auto[1]

61

1

T24

1

T8

2

T56

1

auto[1]

from_1to0

auto[1]

auto[0]

56

1

T24

1

T12

1

T63

1

auto[1]

from_1to0

auto[1]

auto[1]

78

1

T56

2

T12

4

T398

1

auto[1]

from_0to1

auto[0]

auto[0]

65

1

T24

1

T54

1

T12

2

auto[1]

from_0to1

auto[0]

auto[1]

77

1

T24

1

T8

1

T54

1

auto[1]

from_0to1

auto[1]

auto[0]

74

1

T12

1

T25

1

T398

2

auto[1]

from_0to1

auto[1]

auto[1]

69

1

T24

1

T12

2

T174

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1157

1

T24

9

T8

4

T54

9

auto[1]

1138

1

T24

11

T8

4

T54

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

550

1

T24

3

T54

4

T56

2

from_0to1

551

1

T24

4

T54

3

T56

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1192

1

T24

14

T8

5

T54

12

auto[1]

1103

1

T24

6

T8

3

T54

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1154

1

T24

7

T8

3

T54

9

auto[1]

1141

1

T24

13

T8

5

T54

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

69

1

T12

3

T179

2

T275

2

auto[0]

from_1to0

auto[0]

auto[1]

72

1

T24

1

T54

1

T12

2

auto[0]

from_1to0

auto[1]

auto[0]

78

1

T54

1

T12

3

T63

2

auto[0]

from_1to0

auto[1]

auto[1]

69

1

T56

2

T12

2

T25

1

auto[0]

from_0to1

auto[0]

auto[0]

62

1

T63

1

T398

2

T174

1

auto[0]

from_0to1

auto[0]

auto[1]

74

1

T24

1

T12

5

T63

1

auto[0]

from_0to1

auto[1]

auto[0]

58

1

T54

1

T12

2

T25

1

auto[0]

from_0to1

auto[1]

auto[1]

71

1

T54

1

T56

1

T12

2

auto[1]

from_1to0

auto[0]

auto[0]

66

1

T24

1

T12

4

T59

2

auto[1]

from_1to0

auto[0]

auto[1]

65

1

T54

1

T12

3

T234

2

auto[1]

from_1to0

auto[1]

auto[0]

67

1

T54

1

T12

1

T63

2

auto[1]

from_1to0

auto[1]

auto[1]

64

1

T24

1

T12

1

T25

1

auto[1]

from_0to1

auto[0]

auto[0]

90

1

T12

6

T63

1

T59

2

auto[1]

from_0to1

auto[0]

auto[1]

64

1

T24

3

T12

1

T59

1

auto[1]

from_0to1

auto[1]

auto[0]

65

1

T56

1

T12

1

T63

1

auto[1]

from_0to1

auto[1]

auto[1]

67

1

T54

1

T56

1

T12

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1171

1

T24

11

T8

4

T54

9

auto[1]

1124

1

T24

9

T8

4

T54

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

541

1

T24

4

T8

2

T54

2

from_0to1

543

1

T24

3

T8

2

T54

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1153

1

T24

7

T8

6

T54

10

auto[1]

1142

1

T24

13

T8

2

T54

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1155

1

T24

12

T8

7

T54

11

auto[1]

1140

1

T24

8

T8

1

T54

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

70

1

T8

2

T12

6

T63

2

auto[0]

from_1to0

auto[0]

auto[1]

73

1

T56

1

T59

2

T398

1

auto[0]

from_1to0

auto[1]

auto[0]

64

1

T56

1

T12

4

T25

1

auto[0]

from_1to0

auto[1]

auto[1]

72

1

T24

1

T12

3

T63

1

auto[0]

from_0to1

auto[0]

auto[0]

62

1

T24

1

T56

1

T12

4

auto[0]

from_0to1

auto[0]

auto[1]

69

1

T12

3

T63

2

T179

1

auto[0]

from_0to1

auto[1]

auto[0]

73

1

T24

1

T12

1

T25

1

auto[0]

from_0to1

auto[1]

auto[1]

70

1

T24

1

T54

1

T56

1

auto[1]

from_1to0

auto[0]

auto[0]

61

1

T54

1

T12

2

T398

1

auto[1]

from_1to0

auto[0]

auto[1]

66

1

T54

1

T12

2

T398

1

auto[1]

from_1to0

auto[1]

auto[0]

71

1

T24

3

T56

2

T12

4

auto[1]

from_1to0

auto[1]

auto[1]

64

1

T56

1

T12

3

T320

1

auto[1]

from_0to1

auto[0]

auto[0]

71

1

T54

1

T12

4

T63

1

auto[1]

from_0to1

auto[0]

auto[1]

83

1

T54

1

T56

1

T12

5

auto[1]

from_0to1

auto[1]

auto[0]

52

1

T8

2

T56

1

T12

2

auto[1]

from_0to1

auto[1]

auto[1]

63

1

T56

1

T12

1

T59

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1128

1

T24

11

T8

5

T54

10

auto[1]

1167

1

T24

9

T8

3

T54

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

554

1

T24

6

T8

3

T54

4

from_0to1

555

1

T24

6

T8

2

T54

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1150

1

T24

12

T8

4

T54

8

auto[1]

1145

1

T24

8

T8

4

T54

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1122

1

T24

9

T8

2

T54

12

auto[1]

1173

1

T24

11

T8

6

T54

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

78

1

T24

2

T54

1

T12

1

auto[0]

from_1to0

auto[0]

auto[1]

69

1

T24

1

T8

1

T12

2

auto[0]

from_1to0

auto[1]

auto[0]

66

1

T8

1

T25

1

T63

1

auto[0]

from_1to0

auto[1]

auto[1]

62

1

T24

1

T54

1

T12

1

auto[0]

from_0to1

auto[0]

auto[0]

64

1

T24

1

T174

2

T179

1

auto[0]

from_0to1

auto[0]

auto[1]

84

1

T24

1

T8

1

T56

2

auto[0]

from_0to1

auto[1]

auto[0]

57

1

T54

2

T56

1

T12

2

auto[0]

from_0to1

auto[1]

auto[1]

67

1

T56

1

T12

3

T275

1

auto[1]

from_1to0

auto[0]

auto[0]

62

1

T56

1

T63

1

T398

1

auto[1]

from_1to0

auto[0]

auto[1]

66

1

T24

1

T56

1

T12

3

auto[1]

from_1to0

auto[1]

auto[0]

69

1

T24

1

T54

1

T56

1

auto[1]

from_1to0

auto[1]

auto[1]

82

1

T8

1

T54

1

T56

2

auto[1]

from_0to1

auto[0]

auto[0]

74

1

T54

1

T56

1

T12

2

auto[1]

from_0to1

auto[0]

auto[1]

72

1

T24

1

T8

1

T12

1

auto[1]

from_0to1

auto[1]

auto[0]

61

1

T24

1

T54

1

T12

3

auto[1]

from_0to1

auto[1]

auto[1]

76

1

T24

2

T54

1

T12

3

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1119

1

T24

9

T8

3

T54

9

auto[1]

1176

1

T24

11

T8

5

T54

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

543

1

T24

5

T8

2

T54

4

from_0to1

539

1

T24

5

T8

1

T54

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1138

1

T24

12

T8

3

T54

11

auto[1]

1157

1

T24

8

T8

5

T54

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1129

1

T24

11

T8

5

T54

14

auto[1]

1166

1

T24

9

T8

3

T54

6

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

57

1

T24

1

T54

2

T12

4

auto[0]

from_1to0

auto[0]

auto[1]

71

1

T56

2

T12

2

T25

1

auto[0]

from_1to0

auto[1]

auto[0]

58

1

T12

4

T25

1

T63

1

auto[0]

from_1to0

auto[1]

auto[1]

69

1

T56

1

T12

1

T174

1

auto[0]

from_0to1

auto[0]

auto[0]

64

1

T24

2

T54

1

T56

1

auto[0]

from_0to1

auto[0]

auto[1]

62

1

T24

2

T54

1

T56

1

auto[0]

from_0to1

auto[1]

auto[0]

78

1

T56

1

T12

3

T25

1

auto[0]

from_0to1

auto[1]

auto[1]

46

1

T56

1

T12

3

T275

1

auto[1]

from_1to0

auto[0]

auto[0]

72

1

T24

1

T54

1

T12

5

auto[1]

from_1to0

auto[0]

auto[1]

87

1

T24

1

T8

1

T54

1

auto[1]

from_1to0

auto[1]

auto[0]

59

1

T24

1

T56

1

T12

3

auto[1]

from_1to0

auto[1]

auto[1]

70

1

T24

1

T8

1

T56

1

auto[1]

from_0to1

auto[0]

auto[0]

60

1

T12

1

T179

1

T275

1

auto[1]

from_0to1

auto[0]

auto[1]

69

1

T56

2

T12

3

T59

2

auto[1]

from_0to1

auto[1]

auto[0]

71

1

T24

1

T8

1

T54

1

auto[1]

from_0to1

auto[1]

auto[1]

89

1

T54

1

T12

2

T25

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1150

1

T24

10

T8

6

T54

5

auto[1]

1145

1

T24

10

T8

2

T54

15

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

529

1

T24

5

T8

2

T54

4

from_0to1

538

1

T24

5

T8

1

T54

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1178

1

T24

10

T8

5

T54

12

auto[1]

1117

1

T24

10

T8

3

T54

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1143

1

T24

9

T8

2

T54

10

auto[1]

1152

1

T24

11

T8

6

T54

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

64

1

T24

2

T8

1

T56

1

auto[0]

from_1to0

auto[0]

auto[1]

66

1

T8

1

T12

1

T59

1

auto[0]

from_1to0

auto[1]

auto[0]

64

1

T56

1

T12

2

T174

1

auto[0]

from_1to0

auto[1]

auto[1]

78

1

T24

2

T54

1

T56

2

auto[0]

from_0to1

auto[0]

auto[0]

63

1

T24

1

T12

1

T25

1

auto[0]

from_0to1

auto[0]

auto[1]

72

1

T56

1

T12

3

T174

1

auto[0]

from_0to1

auto[1]

auto[0]

74

1

T54

1

T56

2

T12

2

auto[0]

from_0to1

auto[1]

auto[1]

57

1

T56

1

T12

2

T59

1

auto[1]

from_1to0

auto[0]

auto[0]

69

1

T54

1

T56

1

T12

2

auto[1]

from_1to0

auto[0]

auto[1]

66

1

T54

1

T12

2

T63

1

auto[1]

from_1to0

auto[1]

auto[0]

57

1

T24

1

T12

1

T25

2

auto[1]

from_1to0

auto[1]

auto[1]

65

1

T54

1

T56

1

T12

2

auto[1]

from_0to1

auto[0]

auto[0]

77

1

T54

1

T63

1

T59

2

auto[1]

from_0to1

auto[0]

auto[1]

63

1

T8

1

T54

3

T56

2

auto[1]

from_0to1

auto[1]

auto[0]

75

1

T24

2

T56

1

T12

2

auto[1]

from_0to1

auto[1]

auto[1]

57

1

T24

2

T174

1

T275

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1150

1

T24

13

T8

3

T54

14

auto[1]

1145

1

T24

7

T8

5

T54

6

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

560

1

T24

5

T8

3

T54

7

from_0to1

562

1

T24

4

T8

3

T54

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1160

1

T24

9

T8

4

T54

10

auto[1]

1135

1

T24

11

T8

4

T54

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1130

1

T24

9

T8

5

T54

11

auto[1]

1165

1

T24

11

T8

3

T54

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

90

1

T8

1

T54

3

T56

3

auto[0]

from_1to0

auto[0]

auto[1]

65

1

T24

1

T54

2

T56

1

auto[0]

from_1to0

auto[1]

auto[0]

60

1

T24

1

T54

1

T398

2

auto[0]

from_1to0

auto[1]

auto[1]

81

1

T24

2

T12

6

T398

1

auto[0]

from_0to1

auto[0]

auto[0]

61

1

T54

1

T12

2

T59

2

auto[0]

from_0to1

auto[0]

auto[1]

82

1

T24

2

T8

1

T54

1

auto[0]

from_0to1

auto[1]

auto[0]

65

1

T54

1

T12

1

T398

2

auto[0]

from_0to1

auto[1]

auto[1]

58

1

T54

1

T12

1

T25

1

auto[1]

from_1to0

auto[0]

auto[0]

80

1

T24

1

T56

1

T12

3

auto[1]

from_1to0

auto[0]

auto[1]

54

1

T12

3

T63

1

T275

1

auto[1]

from_1to0

auto[1]

auto[0]

61

1

T8

2

T12

2

T59

1

auto[1]

from_1to0

auto[1]

auto[1]

69

1

T54

1

T56

1

T12

3

auto[1]

from_0to1

auto[0]

auto[0]

78

1

T24

1

T8

1

T54

1

auto[1]

from_0to1

auto[0]

auto[1]

65

1

T56

2

T12

1

T63

1

auto[1]

from_0to1

auto[1]

auto[0]

65

1

T54

1

T12

2

T174

1

auto[1]

from_0to1

auto[1]

auto[1]

88

1

T24

1

T8

1

T12

5