Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	154152	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

119453

1

T4

7

T1

347

T5

9

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	141745	1			T4	8		T1	339		T5	8
values[0x0]	65262	1			T4	4		T1	281		T5	1
values[0x1]	66598	1			T4	4		T1	304		T5	8

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	124700	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

148905

1

T4

11

T1

434

T5

13

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	983	1			T3	4		T6	3		T26	1
valid_sources[0x01]	1390	1			T3	3		T6	4		T8	1
valid_sources[0x02]	910	1			T3	3		T24	1		T7	4
valid_sources[0x03]	900	1			T3	4		T6	3		T22	4
valid_sources[0x04]	982	1			T3	4		T6	3		T26	1
valid_sources[0x05]	1209	1			T3	5		T6	3		T22	2
valid_sources[0x06]	949	1			T3	3		T6	6		T26	2
valid_sources[0x07]	2108	1			T3	5		T6	4		T26	1
valid_sources[0x08]	817	1			T3	9		T6	9		T7	2
valid_sources[0x09]	899	1			T3	1		T6	2		T7	2
valid_sources[0x0a]	955	1			T3	11		T6	9		T48	2
valid_sources[0x0b]	845	1			T5	5		T3	1		T6	3
valid_sources[0x0c]	874	1			T6	5		T8	2		T9	7
valid_sources[0x0d]	1730	1			T3	1		T6	3		T7	1
valid_sources[0x0e]	910	1			T14	1		T3	4		T6	2
valid_sources[0x0f]	984	1			T13	2		T3	4		T6	3
valid_sources[0x10]	1032	1			T3	2		T6	2		T24	1
valid_sources[0x11]	722	1			T3	5		T6	9		T32	1
valid_sources[0x12]	918	1			T3	1		T6	3		T8	4
valid_sources[0x13]	788	1			T3	3		T6	2		T22	4
valid_sources[0x14]	1015	1			T13	4		T62	2		T7	1
valid_sources[0x15]	1135	1			T3	5		T6	3		T24	1
valid_sources[0x16]	804	1			T13	2		T3	1		T6	5
valid_sources[0x17]	852	1			T3	2		T6	5		T24	1
valid_sources[0x18]	1949	1			T13	2		T3	4		T62	5
valid_sources[0x19]	2182	1			T2	44		T3	1		T24	2
valid_sources[0x1a]	1106	1			T3	2		T6	6		T24	1
valid_sources[0x1b]	822	1			T3	10		T6	4		T32	1
valid_sources[0x1c]	913	1			T3	1		T6	1		T48	3
valid_sources[0x1d]	1064	1			T3	2		T6	1		T7	2
valid_sources[0x1e]	1666	1			T3	5		T6	6		T24	1
valid_sources[0x1f]	832	1			T3	3		T6	4		T32	1
valid_sources[0x20]	951	1			T3	2		T6	2		T23	63
valid_sources[0x21]	886	1			T3	3		T6	3		T22	2
valid_sources[0x22]	1094	1			T3	5		T6	4		T7	3
valid_sources[0x23]	1435	1			T3	4		T6	3		T24	1
valid_sources[0x24]	929	1			T3	3		T6	7		T24	2
valid_sources[0x25]	1199	1			T3	1		T48	3		T8	3
valid_sources[0x26]	1182	1			T3	9		T6	8		T7	4
valid_sources[0x27]	1127	1			T13	2		T3	2		T6	7
valid_sources[0x28]	1147	1			T3	4		T6	2		T24	1
valid_sources[0x29]	1921	1			T3	3		T6	10		T7	1
valid_sources[0x2a]	941	1			T3	4		T6	3		T7	4
valid_sources[0x2b]	829	1			T3	4		T6	4		T7	1
valid_sources[0x2c]	957	1			T3	4		T6	3		T62	2
valid_sources[0x2d]	1081	1			T3	3		T6	1		T22	1
valid_sources[0x2e]	843	1			T3	5		T6	5		T7	2
valid_sources[0x2f]	906	1			T3	1		T6	1		T7	1
valid_sources[0x30]	1749	1			T3	7		T6	3		T8	5
valid_sources[0x31]	847	1			T3	3		T6	1		T24	2
valid_sources[0x32]	1090	1			T5	2		T3	3		T6	6
valid_sources[0x33]	770	1			T3	3		T6	4		T24	1
valid_sources[0x34]	1071	1			T13	1		T3	9		T6	5
valid_sources[0x35]	945	1			T3	10		T6	1		T8	3
valid_sources[0x36]	958	1			T5	2		T3	1		T6	2
valid_sources[0x37]	1458	1			T3	2		T6	1		T62	2
valid_sources[0x38]	860	1			T3	3		T8	3		T54	1
valid_sources[0x39]	799	1			T3	1		T17	8		T6	3
valid_sources[0x3a]	908	1			T6	7		T24	1		T7	4
valid_sources[0x3b]	948	1			T3	6		T6	2		T7	2
valid_sources[0x3c]	1070	1			T3	5		T6	3		T22	1
valid_sources[0x3d]	1292	1			T3	5		T7	1		T9	1
valid_sources[0x3e]	772	1			T6	7		T7	2		T8	8
valid_sources[0x3f]	793	1			T4	2		T3	3		T6	1
valid_sources[0x40]	1081	1			T3	6		T6	3		T22	2
valid_sources[0x41]	977	1			T3	3		T6	5		T62	5
valid_sources[0x42]	787	1			T13	3		T3	4		T6	1
valid_sources[0x43]	1530	1			T4	8		T3	6		T6	4
valid_sources[0x44]	804	1			T3	2		T6	1		T7	2
valid_sources[0x45]	1017	1			T3	2		T6	6		T62	5
valid_sources[0x46]	1079	1			T14	1		T3	5		T6	6
valid_sources[0x47]	998	1			T3	7		T6	2		T48	1
valid_sources[0x48]	1344	1			T3	6		T6	5		T7	5
valid_sources[0x49]	883	1			T4	4		T3	6		T6	3
valid_sources[0x4a]	1944	1			T1	924		T3	5		T6	5
valid_sources[0x4b]	807	1			T14	1		T3	4		T6	5
valid_sources[0x4c]	876	1			T3	4		T6	7		T24	1
valid_sources[0x4d]	1247	1			T3	9		T24	1		T7	3
valid_sources[0x4e]	1121	1			T3	5		T6	1		T24	1
valid_sources[0x4f]	1271	1			T6	1		T7	1		T9	13
valid_sources[0x50]	769	1			T13	2		T3	3		T6	3
valid_sources[0x51]	747	1			T3	2		T6	5		T7	1
valid_sources[0x52]	950	1			T3	1		T6	1		T24	2
valid_sources[0x53]	1316	1			T3	5		T6	4		T24	2
valid_sources[0x54]	793	1			T3	2		T6	5		T22	1
valid_sources[0x55]	906	1			T3	3		T6	6		T7	1
valid_sources[0x56]	920	1			T3	2		T6	2		T24	1
valid_sources[0x57]	1781	1			T3	6		T6	4		T8	6
valid_sources[0x58]	808	1			T6	6		T7	2		T8	1
valid_sources[0x59]	985	1			T3	2		T6	1		T7	5
valid_sources[0x5a]	902	1			T3	3		T6	6		T24	1
valid_sources[0x5b]	1095	1			T3	10		T6	2		T24	1
valid_sources[0x5c]	959	1			T3	2		T6	2		T24	3
valid_sources[0x5d]	902	1			T3	3		T6	2		T24	1
valid_sources[0x5e]	794	1			T3	3		T6	3		T24	1
valid_sources[0x5f]	853	1			T3	6		T17	3		T6	3
valid_sources[0x60]	799	1			T3	5		T6	9		T24	1
valid_sources[0x61]	1125	1			T3	3		T6	3		T24	2
valid_sources[0x62]	802	1			T3	3		T6	6		T7	1
valid_sources[0x63]	1120	1			T3	2		T6	1		T22	1
valid_sources[0x64]	683	1			T6	2		T24	3		T7	2
valid_sources[0x65]	976	1			T3	3		T6	5		T7	2
valid_sources[0x66]	1940	1			T6	1		T7	4		T8	2
valid_sources[0x67]	1204	1			T3	7		T6	5		T22	1
valid_sources[0x68]	856	1			T3	6		T7	2		T8	8
valid_sources[0x69]	800	1			T3	4		T6	5		T24	1
valid_sources[0x6a]	756	1			T13	4		T3	5		T6	3
valid_sources[0x6b]	1824	1			T3	2		T6	4		T24	1
valid_sources[0x6c]	816	1			T3	2		T6	3		T22	1
valid_sources[0x6d]	917	1			T3	5		T7	3		T8	10
valid_sources[0x6e]	763	1			T5	1		T3	3		T6	3
valid_sources[0x6f]	943	1			T3	9		T6	2		T7	5
valid_sources[0x70]	936	1			T3	1		T7	2		T9	5
valid_sources[0x71]	943	1			T3	4		T6	6		T24	1
valid_sources[0x72]	1030	1			T5	1		T3	4		T6	1
valid_sources[0x73]	826	1			T13	1		T3	3		T6	7
valid_sources[0x74]	1003	1			T3	1		T6	2		T24	1
valid_sources[0x75]	905	1			T3	1		T6	3		T24	2
valid_sources[0x76]	841	1			T3	7		T6	5		T32	1
valid_sources[0x77]	1030	1			T5	1		T3	2		T6	4
valid_sources[0x78]	865	1			T3	7		T6	4		T26	1
valid_sources[0x79]	1198	1			T3	4		T6	3		T24	1
valid_sources[0x7a]	1332	1			T3	2		T6	2		T7	2
valid_sources[0x7b]	701	1			T3	4		T6	3		T24	1
valid_sources[0x7c]	968	1			T3	4		T6	5		T24	1
valid_sources[0x7d]	868	1			T3	5		T6	11		T8	3
valid_sources[0x7e]	1221	1			T3	6		T6	3		T7	2
valid_sources[0x7f]	925	1			T13	5		T3	4		T6	8
valid_sources[0x80]	861	1			T6	5		T7	1		T8	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

64748

1

T4

4

T1

168

T5

5

values[0x0]

all_enables

biggest_size

31967

1

T4

2

T1

106

T5

1

values[0x1]

all_enables

biggest_size

22738

1

T4

1

T1

73

T5

3