Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1103338054	11143	0	0
auto_block_debounce_ctl_rd_A	1103338054	2115	0	0
auto_block_out_ctl_rd_A	1103338054	2515	0	0
com_det_ctl_0_rd_A	1103338054	3828	0	0
com_det_ctl_1_rd_A	1103338054	3940	0	0
com_det_ctl_2_rd_A	1103338054	4174	0	0
com_det_ctl_3_rd_A	1103338054	3979	0	0
com_out_ctl_0_rd_A	1103338054	4452	0	0
com_out_ctl_1_rd_A	1103338054	4659	0	0
com_out_ctl_2_rd_A	1103338054	4554	0	0
com_out_ctl_3_rd_A	1103338054	4449	0	0
com_pre_det_ctl_0_rd_A	1103338054	1643	0	0
com_pre_det_ctl_1_rd_A	1103338054	1571	0	0
com_pre_det_ctl_2_rd_A	1103338054	1627	0	0
com_pre_det_ctl_3_rd_A	1103338054	1691	0	0
com_pre_sel_ctl_0_rd_A	1103338054	4561	0	0
com_pre_sel_ctl_1_rd_A	1103338054	4665	0	0
com_pre_sel_ctl_2_rd_A	1103338054	4643	0	0
com_pre_sel_ctl_3_rd_A	1103338054	4819	0	0
com_sel_ctl_0_rd_A	1103338054	4415	0	0
com_sel_ctl_1_rd_A	1103338054	4616	0	0
com_sel_ctl_2_rd_A	1103338054	4695	0	0
com_sel_ctl_3_rd_A	1103338054	4721	0	0
ec_rst_ctl_rd_A	1103338054	2729	0	0
intr_enable_rd_A	1103338054	2392	0	0
key_intr_ctl_rd_A	1103338054	4400	0	0
key_intr_debounce_ctl_rd_A	1103338054	1558	0	0
key_invert_ctl_rd_A	1103338054	5790	0	0
pin_allowed_ctl_rd_A	1103338054	5909	0	0
pin_out_ctl_rd_A	1103338054	4168	0	0
pin_out_value_rd_A	1103338054	4151	0	0
regwen_rd_A	1103338054	1996	0	0
ulp_ac_debounce_ctl_rd_A	1103338054	1783	0	0
ulp_ctl_rd_A	1103338054	1720	0	0
ulp_lid_debounce_ctl_rd_A	1103338054	1834	0	0
ulp_pwrb_debounce_ctl_rd_A	1103338054	1950	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1103338054	11143	0	0
T6	342843	17	0	0
T8	0	30	0	0
T12	0	13	0	0
T22	69569	0	0	0
T23	65678	0	0	0
T24	251100	0	0	0
T25	0	11	0	0
T26	185518	0	0	0
T27	252228	0	0	0
T32	87954	0	0	0
T37	0	17	0	0
T38	0	16	0	0
T42	0	11	0	0
T44	0	5	0	0
T48	800501	0	0	0
T52	0	12	0	0
T58	292235	0	0	0
T61	36544	0	0	0
T235	0	12	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1103338054	2115	0	0
T7	635009	0	0	0
T8	472811	0	0	0
T9	922837	0	0	0
T10	987958	0	0	0
T11	232866	0	0	0
T12	0	6	0	0
T36	0	9	0	0
T44	0	18	0	0
T47	174244	0	0	0
T49	78573	6	0	0
T50	325205	0	0	0
T54	48008	0	0	0
T55	239021	0	0	0
T83	0	29	0	0
T84	0	8	0	0
T230	0	8	0	0
T235	0	19	0	0
T275	0	12	0	0
T312	0	19	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1103338054	2515	0	0
T7	635009	0	0	0
T8	472811	0	0	0
T9	922837	0	0	0
T10	987958	0	0	0
T11	232866	0	0	0
T12	0	21	0	0
T36	0	27	0	0
T44	0	19	0	0
T47	174244	0	0	0
T49	78573	10	0	0
T50	325205	0	0	0
T54	48008	0	0	0
T55	239021	0	0	0
T83	0	22	0	0
T84	0	5	0	0
T230	0	4	0	0
T235	0	18	0	0
T312	0	6	0	0
T313	0	9	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1103338054	3828	0	0
T7	635009	55	0	0
T8	472811	0	0	0
T9	922837	0	0	0
T10	987958	0	0	0
T11	232866	0	0	0
T12	0	48	0	0
T34	0	47	0	0
T44	0	19	0	0
T47	174244	38	0	0
T50	325205	0	0	0
T54	48008	0	0	0
T55	239021	0	0	0
T56	13367	0	0	0
T84	0	28	0	0
T232	0	62	0	0
T235	0	22	0	0
T261	0	66	0	0
T271	0	61	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1103338054	3940	0	0
T7	635009	90	0	0
T8	472811	0	0	0
T9	922837	0	0	0
T10	987958	0	0	0
T11	232866	0	0	0
T12	0	50	0	0
T34	0	58	0	0
T44	0	18	0	0
T47	174244	38	0	0
T50	325205	0	0	0
T54	48008	0	0	0
T55	239021	0	0	0
T56	13367	0	0	0
T84	0	30	0	0
T232	0	65	0	0
T235	0	8	0	0
T261	0	76	0	0
T271	0	32	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1103338054	4174	0	0
T7	635009	75	0	0
T8	472811	0	0	0
T9	922837	0	0	0
T10	987958	0	0	0
T11	232866	0	0	0
T12	0	64	0	0
T34	0	47	0	0
T44	0	26	0	0
T47	174244	43	0	0
T50	325205	0	0	0
T54	48008	0	0	0
T55	239021	0	0	0
T56	13367	0	0	0
T84	0	29	0	0
T232	0	70	0	0
T235	0	10	0	0
T261	0	97	0	0
T271	0	39	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1103338054	3979	0	0
T7	635009	71	0	0
T8	472811	0	0	0
T9	922837	0	0	0
T10	987958	0	0	0
T11	232866	0	0	0
T12	0	34	0	0
T34	0	26	0	0
T44	0	18	0	0
T47	174244	32	0	0
T50	325205	0	0	0
T54	48008	0	0	0
T55	239021	0	0	0
T56	13367	0	0	0
T84	0	44	0	0
T232	0	53	0	0
T235	0	22	0	0
T261	0	71	0	0
T271	0	65	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1103338054	4452	0	0
T7	635009	75	0	0
T8	472811	0	0	0
T9	922837	0	0	0
T10	987958	0	0	0
T11	232866	0	0	0
T12	0	21	0	0
T34	0	35	0	0
T44	0	23	0	0
T47	174244	35	0	0
T50	325205	0	0	0
T54	48008	0	0	0
T55	239021	0	0	0
T56	13367	0	0	0
T84	0	60	0	0
T232	0	62	0	0
T235	0	36	0	0
T261	0	85	0	0
T271	0	42	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1103338054	4659	0	0
T7	635009	87	0	0
T8	472811	0	0	0
T9	922837	0	0	0
T10	987958	0	0	0
T11	232866	0	0	0
T12	0	31	0	0
T34	0	32	0	0
T44	0	16	0	0
T47	174244	52	0	0
T50	325205	0	0	0
T54	48008	0	0	0
T55	239021	0	0	0
T56	13367	0	0	0
T84	0	29	0	0
T232	0	63	0	0
T235	0	21	0	0
T261	0	59	0	0
T271	0	60	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1103338054	4554	0	0
T7	635009	71	0	0
T8	472811	0	0	0
T9	922837	0	0	0
T10	987958	0	0	0
T11	232866	0	0	0
T12	0	37	0	0
T34	0	53	0	0
T44	0	20	0	0
T47	174244	29	0	0
T50	325205	0	0	0
T54	48008	0	0	0
T55	239021	0	0	0
T56	13367	0	0	0
T84	0	29	0	0
T232	0	73	0	0
T235	0	26	0	0
T261	0	74	0	0
T271	0	42	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1103338054	4449	0	0
T7	635009	63	0	0
T8	472811	0	0	0
T9	922837	0	0	0
T10	987958	0	0	0
T11	232866	0	0	0
T12	0	33	0	0
T34	0	19	0	0
T44	0	13	0	0
T47	174244	28	0	0
T50	325205	0	0	0
T54	48008	0	0	0
T55	239021	0	0	0
T56	13367	0	0	0
T84	0	34	0	0
T232	0	94	0	0
T235	0	14	0	0
T261	0	45	0	0
T271	0	65	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1103338054	1643	0	0
T12	249857	5	0	0
T25	374026	0	0	0
T29	0	163	0	0
T33	357853	0	0	0
T36	0	29	0	0
T41	20346	0	0	0
T44	0	20	0	0
T51	633926	0	0	0
T59	424447	0	0	0
T63	75521	0	0	0
T64	63200	0	0	0
T83	0	50	0	0
T85	272422	0	0	0
T86	55217	0	0	0
T152	0	21	0	0
T235	0	27	0	0
T247	0	26	0	0
T314	0	29	0	0
T315	0	6	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1103338054	1571	0	0
T12	249857	15	0	0
T25	374026	0	0	0
T29	0	126	0	0
T33	357853	0	0	0
T36	0	23	0	0
T41	20346	0	0	0
T44	0	12	0	0
T51	633926	0	0	0
T59	424447	0	0	0
T63	75521	0	0	0
T64	63200	0	0	0
T83	0	28	0	0
T85	272422	0	0	0
T86	55217	0	0	0
T152	0	10	0	0
T235	0	10	0	0
T247	0	17	0	0
T314	0	35	0	0
T315	0	3	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1103338054	1627	0	0
T12	249857	13	0	0
T25	374026	0	0	0
T29	0	163	0	0
T33	357853	0	0	0
T36	0	24	0	0
T41	20346	0	0	0
T44	0	9	0	0
T51	633926	0	0	0
T59	424447	0	0	0
T63	75521	0	0	0
T64	63200	0	0	0
T83	0	21	0	0
T85	272422	0	0	0
T86	55217	0	0	0
T152	0	19	0	0
T235	0	12	0	0
T247	0	8	0	0
T314	0	15	0	0
T315	0	6	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1103338054	1691	0	0
T12	249857	17	0	0
T25	374026	0	0	0
T29	0	179	0	0
T33	357853	0	0	0
T36	0	15	0	0
T41	20346	0	0	0
T44	0	11	0	0
T51	633926	0	0	0
T59	424447	0	0	0
T63	75521	0	0	0
T64	63200	0	0	0
T83	0	36	0	0
T85	272422	0	0	0
T86	55217	0	0	0
T152	0	9	0	0
T235	0	24	0	0
T247	0	15	0	0
T314	0	38	0	0
T315	0	6	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1103338054	4561	0	0
T7	635009	69	0	0
T8	472811	0	0	0
T9	922837	0	0	0
T10	987958	0	0	0
T11	232866	0	0	0
T12	0	37	0	0
T34	0	42	0	0
T44	0	11	0	0
T47	174244	36	0	0
T50	325205	0	0	0
T54	48008	0	0	0
T55	239021	0	0	0
T56	13367	0	0	0
T84	0	50	0	0
T232	0	53	0	0
T235	0	27	0	0
T261	0	50	0	0
T271	0	32	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1103338054	4665	0	0
T7	635009	89	0	0
T8	472811	0	0	0
T9	922837	0	0	0
T10	987958	0	0	0
T11	232866	0	0	0
T12	0	48	0	0
T34	0	19	0	0
T44	0	20	0	0
T47	174244	44	0	0
T50	325205	0	0	0
T54	48008	0	0	0
T55	239021	0	0	0
T56	13367	0	0	0
T84	0	71	0	0
T232	0	61	0	0
T235	0	23	0	0
T261	0	62	0	0
T271	0	39	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1103338054	4643	0	0
T7	635009	83	0	0
T8	472811	0	0	0
T9	922837	0	0	0
T10	987958	0	0	0
T11	232866	0	0	0
T12	0	49	0	0
T34	0	46	0	0
T44	0	12	0	0
T47	174244	41	0	0
T50	325205	0	0	0
T54	48008	0	0	0
T55	239021	0	0	0
T56	13367	0	0	0
T84	0	44	0	0
T232	0	63	0	0
T235	0	15	0	0
T261	0	79	0	0
T271	0	70	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1103338054	4819	0	0
T7	635009	64	0	0
T8	472811	0	0	0
T9	922837	0	0	0
T10	987958	0	0	0
T11	232866	0	0	0
T12	0	18	0	0
T34	0	48	0	0
T44	0	9	0	0
T47	174244	15	0	0
T50	325205	0	0	0
T54	48008	0	0	0
T55	239021	0	0	0
T56	13367	0	0	0
T84	0	58	0	0
T232	0	83	0	0
T235	0	22	0	0
T261	0	86	0	0
T271	0	37	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1103338054	4415	0	0
T7	635009	63	0	0
T8	472811	0	0	0
T9	922837	0	0	0
T10	987958	0	0	0
T11	232866	0	0	0
T12	0	36	0	0
T34	0	40	0	0
T44	0	11	0	0
T47	174244	30	0	0
T50	325205	0	0	0
T54	48008	0	0	0
T55	239021	0	0	0
T56	13367	0	0	0
T84	0	45	0	0
T232	0	77	0	0
T235	0	23	0	0
T261	0	60	0	0
T271	0	40	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1103338054	4616	0	0
T7	635009	62	0	0
T8	472811	0	0	0
T9	922837	0	0	0
T10	987958	0	0	0
T11	232866	0	0	0
T12	0	42	0	0
T34	0	29	0	0
T44	0	10	0	0
T47	174244	25	0	0
T50	325205	0	0	0
T54	48008	0	0	0
T55	239021	0	0	0
T56	13367	0	0	0
T84	0	60	0	0
T232	0	60	0	0
T235	0	36	0	0
T261	0	65	0	0
T271	0	34	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1103338054	4695	0	0
T7	635009	60	0	0
T8	472811	0	0	0
T9	922837	0	0	0
T10	987958	0	0	0
T11	232866	0	0	0
T12	0	35	0	0
T34	0	32	0	0
T44	0	19	0	0
T47	174244	25	0	0
T50	325205	0	0	0
T54	48008	0	0	0
T55	239021	0	0	0
T56	13367	0	0	0
T84	0	42	0	0
T232	0	87	0	0
T235	0	17	0	0
T261	0	80	0	0
T271	0	24	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1103338054	4721	0	0
T7	635009	61	0	0
T8	472811	0	0	0
T9	922837	0	0	0
T10	987958	0	0	0
T11	232866	0	0	0
T12	0	42	0	0
T34	0	42	0	0
T44	0	12	0	0
T47	174244	40	0	0
T50	325205	0	0	0
T54	48008	0	0	0
T55	239021	0	0	0
T56	13367	0	0	0
T84	0	44	0	0
T232	0	54	0	0
T235	0	21	0	0
T261	0	73	0	0
T271	0	34	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1103338054	2729	0	0
T3	544627	0	0	0
T6	342843	0	0	0
T7	0	18	0	0
T12	0	41	0	0
T14	374126	4	0	0
T15	88404	0	0	0
T16	197364	0	0	0
T17	59595	0	0	0
T22	69569	0	0	0
T23	65678	0	0	0
T27	252228	2	0	0
T44	0	21	0	0
T47	0	5	0	0
T51	0	3	0	0
T61	36544	0	0	0
T63	0	2	0	0
T84	0	25	0	0
T316	0	6	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1103338054	2392	0	0
T12	249857	18	0	0
T25	374026	0	0	0
T33	357853	0	0	0
T36	0	28	0	0
T41	20346	0	0	0
T43	0	40	0	0
T44	0	10	0	0
T51	633926	0	0	0
T59	424447	0	0	0
T63	75521	0	0	0
T64	63200	0	0	0
T83	0	43	0	0
T84	0	16	0	0
T85	272422	0	0	0
T86	55217	0	0	0
T152	0	28	0	0
T235	0	23	0	0
T247	0	24	0	0
T314	0	49	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1103338054	4400	0	0
T12	249857	13	0	0
T25	374026	0	0	0
T33	357853	0	0	0
T36	0	18	0	0
T41	20346	0	0	0
T43	0	1	0	0
T44	0	28	0	0
T51	633926	0	0	0
T59	424447	0	0	0
T63	75521	0	0	0
T64	63200	0	0	0
T82	0	1	0	0
T83	0	30	0	0
T85	272422	0	0	0
T86	55217	0	0	0
T111	0	6	0	0
T194	0	10	0	0
T235	0	15	0	0
T247	0	10	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1103338054	1558	0	0
T12	249857	5	0	0
T18	0	21	0	0
T25	374026	0	0	0
T29	0	159	0	0
T33	357853	0	0	0
T36	0	12	0	0
T41	20346	0	0	0
T44	0	10	0	0
T51	633926	0	0	0
T59	424447	0	0	0
T63	75521	0	0	0
T64	63200	0	0	0
T83	0	11	0	0
T85	272422	0	0	0
T86	55217	0	0	0
T152	0	7	0	0
T235	0	14	0	0
T247	0	14	0	0
T314	0	25	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1103338054	5790	0	0
T12	249857	189	0	0
T25	374026	0	0	0
T33	357853	0	0	0
T41	20346	0	0	0
T44	0	64	0	0
T51	633926	0	0	0
T59	424447	0	0	0
T63	75521	0	0	0
T64	63200	0	0	0
T84	0	30	0	0
T85	272422	0	0	0
T86	55217	0	0	0
T210	0	28	0	0
T233	0	61	0	0
T235	0	11	0	0
T278	0	33	0	0
T317	0	67	0	0
T318	0	22	0	0
T319	0	78	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1103338054	5909	0	0
T12	249857	240	0	0
T25	374026	0	0	0
T33	357853	0	0	0
T36	0	121	0	0
T39	0	33	0	0
T41	20346	0	0	0
T44	0	26	0	0
T51	633926	0	0	0
T59	424447	0	0	0
T63	75521	40	0	0
T64	63200	0	0	0
T85	272422	0	0	0
T86	55217	0	0	0
T187	0	69	0	0
T235	0	15	0	0
T275	0	107	0	0
T320	0	63	0	0
T321	0	55	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1103338054	4168	0	0
T12	249857	178	0	0
T25	374026	0	0	0
T33	357853	0	0	0
T36	0	97	0	0
T39	0	35	0	0
T41	20346	0	0	0
T44	0	13	0	0
T51	633926	0	0	0
T59	424447	0	0	0
T63	75521	37	0	0
T64	63200	0	0	0
T85	272422	0	0	0
T86	55217	0	0	0
T187	0	54	0	0
T235	0	18	0	0
T275	0	94	0	0
T320	0	45	0	0
T321	0	49	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1103338054	4151	0	0
T12	249857	256	0	0
T25	374026	0	0	0
T33	357853	0	0	0
T36	0	73	0	0
T39	0	62	0	0
T41	20346	0	0	0
T44	0	8	0	0
T51	633926	0	0	0
T59	424447	0	0	0
T63	75521	67	0	0
T64	63200	0	0	0
T85	272422	0	0	0
T86	55217	0	0	0
T187	0	69	0	0
T235	0	13	0	0
T275	0	63	0	0
T320	0	57	0	0
T321	0	59	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1103338054	1996	0	0
T12	249857	12	0	0
T25	374026	0	0	0
T29	0	148	0	0
T33	357853	0	0	0
T36	0	22	0	0
T41	20346	0	0	0
T44	0	7	0	0
T51	633926	0	0	0
T59	424447	0	0	0
T63	75521	0	0	0
T64	63200	0	0	0
T83	0	26	0	0
T85	272422	0	0	0
T86	55217	0	0	0
T152	0	11	0	0
T235	0	14	0	0
T247	0	10	0	0
T314	0	23	0	0
T315	0	6	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1103338054	1783	0	0
T11	232866	9	0	0
T12	249857	12	0	0
T25	374026	0	0	0
T36	0	24	0	0
T41	20346	0	0	0
T44	0	34	0	0
T51	633926	0	0	0
T56	13367	0	0	0
T59	424447	0	0	0
T63	75521	0	0	0
T64	63200	0	0	0
T67	0	2	0	0
T70	0	7	0	0
T77	0	4	0	0
T82	0	7	0	0
T85	272422	0	0	0
T235	0	13	0	0
T322	0	2	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1103338054	1720	0	0
T2	239883	6	0	0
T3	544627	0	0	0
T6	342843	0	0	0
T11	0	5	0	0
T12	0	2	0	0
T14	374126	0	0	0
T15	88404	0	0	0
T16	197364	0	0	0
T17	59595	0	0	0
T22	69569	0	0	0
T23	65678	0	0	0
T36	0	15	0	0
T44	0	20	0	0
T61	36544	0	0	0
T67	0	2	0	0
T70	0	5	0	0
T233	0	4	0	0
T235	0	24	0	0
T322	0	1	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1103338054	1834	0	0
T2	239883	9	0	0
T3	544627	0	0	0
T6	342843	0	0	0
T11	0	9	0	0
T12	0	23	0	0
T14	374126	0	0	0
T15	88404	0	0	0
T16	197364	0	0	0
T17	59595	0	0	0
T22	69569	0	0	0
T23	65678	0	0	0
T36	0	8	0	0
T44	0	17	0	0
T61	36544	0	0	0
T67	0	3	0	0
T70	0	1	0	0
T233	0	4	0	0
T235	0	28	0	0
T322	0	4	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1103338054	1950	0	0
T2	239883	9	0	0
T3	544627	0	0	0
T6	342843	0	0	0
T11	0	12	0	0
T12	0	19	0	0
T14	374126	0	0	0
T15	88404	0	0	0
T16	197364	0	0	0
T17	59595	0	0	0
T22	69569	0	0	0
T23	65678	0	0	0
T36	0	11	0	0
T44	0	21	0	0
T61	36544	0	0	0
T67	0	1	0	0
T70	0	6	0	0
T233	0	6	0	0
T235	0	15	0	0
T322	0	7	0	0