Unified Coverage Report :: Module

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T2,T14
1	0	Covered	T1,T2,T14
1	1	Covered	T2,T6,T32

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T2,T14
1	0	Covered	T2,T6,T32
1	1	Covered	T1,T2,T14

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2147483647	227239	0	0
SrcPulseCheck_M	2147483647	228607	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2147483647	227239
T1	5275372	68
T2	5536560	0
T3	12784665	51
T4	544128	16
T5	3437810	16
T6	7796628	152
T7	0	80
T8	472811	156
T9	922837	102
T10	987958	32
T11	232866	0
T12	249857	152
T13	1428323	0
T14	8622447	0
T15	2049553	0
T16	4548618	0
T17	1380460	0
T25	0	16
T26	0	16
T27	0	17
T33	0	7
T47	174244	17
T48	0	34
T49	0	14
T50	325205	16
T51	0	1
T52	0	24
T53	0	8
T54	48008	0
T55	239021	0
T56	13367	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2147483647	228607
T1	5275372	68
T2	5536560	0
T3	12784665	51
T4	544128	16
T5	3437810	16
T6	7796628	152
T7	0	80
T8	39472	156
T9	18832	102
T10	8590	32
T11	1044	0
T12	63037	152
T13	1428323	0
T14	8622447	0
T15	2049553	0
T16	4548618	0
T17	1380460	0
T25	0	16
T26	0	16
T27	0	17
T33	0	7
T47	6969	17
T48	0	34
T49	0	14
T50	650	16
T51	0	1
T52	0	24
T53	0	8
T54	505	0
T55	492	0
T56	535	0

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T14,T15
1	0	Covered	T1,T14,T15
1	1	Covered	T30,T18,T21

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T14,T15
1	0	Covered	T30,T18,T21
1	1	Covered	T1,T14,T15

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8139393	1990	0	0
SrcPulseCheck_M	1103338054	2025	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8139393	1990
T1	16990	4
T2	837	0
T3	11228	3
T5	11957	0
T6	28425	12
T7	0	5
T8	0	14
T9	0	6
T13	493	0
T14	763	1
T15	707	1
T16	402	0
T17	425	0
T27	0	1
T58	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1103338054	2025
T1	212374	4
T2	239883	0
T3	544627	3
T5	137513	0
T6	342843	12
T7	0	5
T8	0	14
T9	0	6
T13	61608	0
T14	374126	1
T15	88404	1
T16	197364	0
T17	59595	0
T27	0	1
T58	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T14,T15
1	0	Covered	T1,T14,T15
1	1	Covered	T30,T18,T21

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T14,T15
1	0	Covered	T30,T18,T21
1	1	Covered	T1,T14,T15

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1103338054	2014	0	0
SrcPulseCheck_M	8139393	2014	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1103338054	2014
T1	212374	4
T2	239883	0
T3	544627	3
T5	137513	0
T6	342843	12
T7	0	5
T8	0	14
T9	0	6
T13	61608	0
T14	374126	1
T15	88404	1
T16	197364	0
T17	59595	0
T27	0	1
T58	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8139393	2014
T1	16990	4
T2	837	0
T3	11228	3
T5	11957	0
T6	28425	12
T7	0	5
T8	0	14
T9	0	6
T13	493	0
T14	763	1
T15	707	1
T16	402	0
T17	425	0
T27	0	1
T58	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T2,T6,T32
1	0	Covered	T2,T6,T32
1	1	Covered	T2,T32,T11

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T2,T6,T32
1	0	Covered	T2,T32,T11
1	1	Covered	T2,T6,T32

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8139393	935	0	0
SrcPulseCheck_M	1103338054	971	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8139393	935
T2	837	3
T3	11228	0
T6	28425	2
T8	0	3
T11	0	2
T14	763	0
T15	707	0
T16	402	0
T17	425	0
T22	497	0
T23	525	0
T32	0	2
T37	0	2
T42	0	1
T44	0	1
T59	0	1
T60	0	1
T61	429	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1103338054	971
T2	239883	3
T3	544627	0
T6	342843	2
T8	0	3
T11	0	2
T14	374126	0
T15	88404	0
T16	197364	0
T17	59595	0
T22	69569	0
T23	65678	0
T32	0	2
T37	0	2
T42	0	1
T44	0	1
T59	0	1
T60	0	1
T61	36544	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T2,T6,T32
1	0	Covered	T2,T6,T32
1	1	Covered	T2,T32,T11

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T2,T6,T32
1	0	Covered	T2,T32,T11
1	1	Covered	T2,T6,T32

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1103338054	961	0	0
SrcPulseCheck_M	8139393	961	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1103338054	961
T2	239883	3
T3	544627	0
T6	342843	2
T8	0	3
T11	0	2
T14	374126	0
T15	88404	0
T16	197364	0
T17	59595	0
T22	69569	0
T23	65678	0
T32	0	2
T37	0	2
T42	0	1
T44	0	1
T59	0	1
T60	0	1
T61	36544	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8139393	961
T2	837	3
T3	11228	0
T6	28425	2
T8	0	3
T11	0	2
T14	763	0
T15	707	0
T16	402	0
T17	425	0
T22	497	0
T23	525	0
T32	0	2
T37	0	2
T42	0	1
T44	0	1
T59	0	1
T60	0	1
T61	429	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T2,T6,T32
1	0	Covered	T2,T6,T32
1	1	Covered	T2,T32,T11

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T2,T6,T32
1	0	Covered	T2,T32,T11
1	1	Covered	T2,T6,T32

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8139393	948	0	0
SrcPulseCheck_M	1103338054	988	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8139393	948
T2	837	3
T3	11228	0
T6	28425	2
T8	0	3
T11	0	2
T14	763	0
T15	707	0
T16	402	0
T17	425	0
T22	497	0
T23	525	0
T32	0	2
T37	0	2
T42	0	1
T44	0	1
T59	0	1
T60	0	1
T61	429	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1103338054	988
T2	239883	3
T3	544627	0
T6	342843	2
T8	0	3
T11	0	2
T14	374126	0
T15	88404	0
T16	197364	0
T17	59595	0
T22	69569	0
T23	65678	0
T32	0	2
T37	0	2
T42	0	1
T44	0	1
T59	0	1
T60	0	1
T61	36544	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T2,T6,T32
1	0	Covered	T2,T6,T32
1	1	Covered	T2,T32,T11

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T2,T6,T32
1	0	Covered	T2,T32,T11
1	1	Covered	T2,T6,T32

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1103338054	976	0	0
SrcPulseCheck_M	8139393	976	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1103338054	976
T2	239883	3
T3	544627	0
T6	342843	2
T8	0	3
T11	0	2
T14	374126	0
T15	88404	0
T16	197364	0
T17	59595	0
T22	69569	0
T23	65678	0
T32	0	2
T37	0	2
T42	0	1
T44	0	1
T59	0	1
T60	0	1
T61	36544	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8139393	976
T2	837	3
T3	11228	0
T6	28425	2
T8	0	3
T11	0	2
T14	763	0
T15	707	0
T16	402	0
T17	425	0
T22	497	0
T23	525	0
T32	0	2
T37	0	2
T42	0	1
T44	0	1
T59	0	1
T60	0	1
T61	429	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T2,T6,T32
1	0	Covered	T2,T6,T32
1	1	Covered	T2,T32,T11

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T2,T6,T32
1	0	Covered	T2,T32,T11
1	1	Covered	T2,T6,T32

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8139393	975	0	0
SrcPulseCheck_M	1103338054	1019	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8139393	975
T2	837	3
T3	11228	0
T6	28425	2
T8	0	3
T11	0	2
T14	763	0
T15	707	0
T16	402	0
T17	425	0
T22	497	0
T23	525	0
T32	0	2
T37	0	2
T42	0	1
T44	0	1
T59	0	1
T60	0	1
T61	429	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1103338054	1019
T2	239883	3
T3	544627	0
T6	342843	2
T8	0	3
T11	0	2
T14	374126	0
T15	88404	0
T16	197364	0
T17	59595	0
T22	69569	0
T23	65678	0
T32	0	2
T37	0	2
T42	0	1
T44	0	1
T59	0	1
T60	0	1
T61	36544	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T2,T6,T32
1	0	Covered	T2,T6,T32
1	1	Covered	T2,T32,T11

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T2,T6,T32
1	0	Covered	T2,T32,T11
1	1	Covered	T2,T6,T32

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1103338054	1007	0	0
SrcPulseCheck_M	8139393	1007	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1103338054	1007
T2	239883	3
T3	544627	0
T6	342843	2
T8	0	3
T11	0	2
T14	374126	0
T15	88404	0
T16	197364	0
T17	59595	0
T22	69569	0
T23	65678	0
T32	0	2
T37	0	2
T42	0	1
T44	0	1
T59	0	1
T60	0	1
T61	36544	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8139393	1007
T2	837	3
T3	11228	0
T6	28425	2
T8	0	3
T11	0	2
T14	763	0
T15	707	0
T16	402	0
T17	425	0
T22	497	0
T23	525	0
T32	0	2
T37	0	2
T42	0	1
T44	0	1
T59	0	1
T60	0	1
T61	429	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T2,T6,T8
1	0	Covered	T2,T6,T8
1	1	Covered	T2,T6,T8

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T2,T6,T8
1	0	Covered	T2,T6,T8
1	1	Covered	T2,T6,T8

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8139393	954	0	0
SrcPulseCheck_M	1103338054	994	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8139393	954
T2	837	4
T3	11228	0
T6	28425	2
T8	0	4
T11	0	2
T14	763	0
T15	707	0
T16	402	0
T17	425	0
T22	497	0
T23	525	0
T37	0	2
T60	0	1
T61	429	0
T67	0	4
T68	0	2
T69	0	4
T70	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1103338054	994
T2	239883	4
T3	544627	0
T6	342843	2
T8	0	4
T11	0	2
T14	374126	0
T15	88404	0
T16	197364	0
T17	59595	0
T22	69569	0
T23	65678	0
T37	0	2
T60	0	1
T61	36544	0
T67	0	4
T68	0	2
T69	0	4
T70	0	2

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T2,T6,T8
1	0	Covered	T2,T6,T8
1	1	Covered	T2,T6,T8

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T2,T6,T8
1	0	Covered	T2,T6,T8
1	1	Covered	T2,T6,T8

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1103338054	981	0	0
SrcPulseCheck_M	8139393	981	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1103338054	981
T2	239883	4
T3	544627	0
T6	342843	2
T8	0	4
T11	0	2
T14	374126	0
T15	88404	0
T16	197364	0
T17	59595	0
T22	69569	0
T23	65678	0
T37	0	2
T60	0	1
T61	36544	0
T67	0	4
T68	0	2
T69	0	4
T70	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8139393	981
T2	837	4
T3	11228	0
T6	28425	2
T8	0	4
T11	0	2
T14	763	0
T15	707	0
T16	402	0
T17	425	0
T22	497	0
T23	525	0
T37	0	2
T60	0	1
T61	429	0
T67	0	4
T68	0	2
T69	0	4
T70	0	2

Line Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T65

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T65
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8139393	1144	0	0
SrcPulseCheck_M	1103338054	1181	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8139393	1144
T1	16990	3
T2	837	2
T3	11228	2
T5	11957	0
T6	28425	2
T7	0	4
T8	0	2
T9	0	5
T10	0	1
T11	0	1
T12	0	6
T13	493	0
T14	763	0
T15	707	0
T16	402	0
T17	425	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1103338054	1181
T1	212374	3
T2	239883	2
T3	544627	2
T5	137513	0
T6	342843	2
T7	0	4
T8	0	2
T9	0	5
T10	0	1
T11	0	1
T12	0	6
T13	61608	0
T14	374126	0
T15	88404	0
T16	197364	0
T17	59595	0

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T13,T6,T22
1	0	Covered	T13,T6,T22
1	1	Covered	T13,T6,T22

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T13,T6,T22
1	0	Covered	T13,T6,T22
1	1	Covered	T13,T6,T22

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8139393	3022	0	0
SrcPulseCheck_M	1103338054	3059	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8139393	3022
T2	837	0
T3	11228	0
T6	28425	20
T8	0	20
T12	0	80
T13	493	20
T14	763	0
T15	707	0
T16	402	0
T17	425	0
T22	497	20
T23	525	0
T25	0	20
T44	0	20
T52	0	20
T55	0	20
T62	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1103338054	3059
T2	239883	0
T3	544627	0
T6	342843	20
T8	0	20
T12	0	80
T13	61608	20
T14	374126	0
T15	88404	0
T16	197364	0
T17	59595	0
T22	69569	20
T23	65678	0
T25	0	20
T44	0	20
T52	0	20
T55	0	20
T62	0	20

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T13,T6,T22
1	0	Covered	T13,T6,T22
1	1	Covered	T13,T6,T22

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T13,T6,T22
1	0	Covered	T13,T6,T22
1	1	Covered	T13,T6,T22

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1103338054	3049	0	0
SrcPulseCheck_M	8139393	3049	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1103338054	3049
T2	239883	0
T3	544627	0
T6	342843	20
T8	0	20
T12	0	80
T13	61608	20
T14	374126	0
T15	88404	0
T16	197364	0
T17	59595	0
T22	69569	20
T23	65678	0
T25	0	20
T44	0	20
T52	0	20
T55	0	20
T62	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8139393	3049
T2	837	0
T3	11228	0
T6	28425	20
T8	0	20
T12	0	80
T13	493	20
T14	763	0
T15	707	0
T16	402	0
T17	425	0
T22	497	20
T23	525	0
T25	0	20
T44	0	20
T52	0	20
T55	0	20
T62	0	20

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T13,T6,T22
1	0	Covered	T13,T6,T22
1	1	Covered	T6,T23,T24

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T13,T6,T22
1	0	Covered	T6,T23,T24
1	1	Covered	T13,T6,T22

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8139393	6446	0	0
SrcPulseCheck_M	1103338054	6489	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8139393	6446
T2	837	0
T3	11228	0
T6	28425	61
T8	0	28
T13	493	1
T14	763	0
T15	707	0
T16	402	0
T17	425	0
T22	497	1
T23	525	20
T24	0	20
T54	0	20
T55	0	1
T56	0	20
T62	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1103338054	6489
T2	239883	0
T3	544627	0
T6	342843	61
T8	0	29
T13	61608	1
T14	374126	0
T15	88404	0
T16	197364	0
T17	59595	0
T22	69569	1
T23	65678	20
T24	0	20
T54	0	20
T55	0	1
T56	0	20
T62	0	1

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T13,T6,T22
1	0	Covered	T13,T6,T22
1	1	Covered	T6,T23,T24

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T13,T6,T22
1	0	Covered	T6,T23,T24
1	1	Covered	T13,T6,T22

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1103338054	6475	0	0
SrcPulseCheck_M	8139393	6475	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1103338054	6475
T2	239883	0
T3	544627	0
T6	342843	61
T8	0	28
T13	61608	1
T14	374126	0
T15	88404	0
T16	197364	0
T17	59595	0
T22	69569	1
T23	65678	20
T24	0	20
T54	0	20
T55	0	1
T56	0	20
T62	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8139393	6475
T2	837	0
T3	11228	0
T6	28425	61
T8	0	28
T13	493	1
T14	763	0
T15	707	0
T16	402	0
T17	425	0
T22	497	1
T23	525	20
T24	0	20
T54	0	20
T55	0	1
T56	0	20
T62	0	1

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T13,T14
1	0	Covered	T1,T13,T14
1	1	Covered	T6,T23,T24

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T13,T14
1	0	Covered	T6,T23,T24
1	1	Covered	T1,T13,T14

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8139393	7616	0	0
SrcPulseCheck_M	1103338054	7662	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8139393	7616
T1	16990	4
T2	837	0
T3	11228	3
T5	11957	0
T6	28425	74
T13	493	1
T14	763	1
T15	707	1
T16	402	0
T17	425	0
T22	0	1
T23	0	20
T24	0	20
T27	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1103338054	7662
T1	212374	4
T2	239883	0
T3	544627	3
T5	137513	0
T6	342843	74
T13	61608	1
T14	374126	1
T15	88404	1
T16	197364	0
T17	59595	0
T22	0	1
T23	0	20
T24	0	20
T27	0	1

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T13,T14
1	0	Covered	T1,T13,T14
1	1	Covered	T6,T23,T24

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T13,T14
1	0	Covered	T6,T23,T24
1	1	Covered	T1,T13,T14

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1103338054	7648	0	0
SrcPulseCheck_M	8139393	7648	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1103338054	7648
T1	212374	4
T2	239883	0
T3	544627	3
T5	137513	0
T6	342843	74
T13	61608	1
T14	374126	1
T15	88404	1
T16	197364	0
T17	59595	0
T22	0	1
T23	0	20
T24	0	20
T27	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8139393	7648
T1	16990	4
T2	837	0
T3	11228	3
T5	11957	0
T6	28425	74
T13	493	1
T14	763	1
T15	707	1
T16	402	0
T17	425	0
T22	0	1
T23	0	20
T24	0	20
T27	0	1

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T6,T23,T24
1	0	Covered	T6,T23,T24
1	1	Covered	T6,T23,T24

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T6,T23,T24
1	0	Covered	T6,T23,T24
1	1	Covered	T6,T23,T24

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8139393	6310	0	0
SrcPulseCheck_M	1103338054	6355	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8139393	6310
T6	28425	60
T8	0	27
T12	0	140
T22	497	0
T23	525	20
T24	502	20
T25	0	31
T26	741	0
T27	5366	0
T32	1111	0
T48	1667	0
T54	0	20
T56	0	20
T58	603	0
T61	429	0
T63	0	60
T64	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1103338054	6355
T6	342843	60
T8	0	28
T12	0	140
T22	69569	0
T23	65678	20
T24	251100	20
T25	0	32
T26	185518	0
T27	252228	0
T32	87954	0
T48	800501	0
T54	0	20
T56	0	20
T58	292235	0
T61	36544	0
T63	0	60
T64	0	20

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T6,T23,T24
1	0	Covered	T6,T23,T24
1	1	Covered	T6,T23,T24

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T6,T23,T24
1	0	Covered	T6,T23,T24
1	1	Covered	T6,T23,T24

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1103338054	6341	0	0
SrcPulseCheck_M	8139393	6341	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1103338054	6341
T6	342843	60
T8	0	27
T12	0	140
T22	69569	0
T23	65678	20
T24	251100	20
T25	0	31
T26	185518	0
T27	252228	0
T32	87954	0
T48	800501	0
T54	0	20
T56	0	20
T58	292235	0
T61	36544	0
T63	0	60
T64	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8139393	6341
T6	28425	60
T8	0	27
T12	0	140
T22	497	0
T23	525	20
T24	502	20
T25	0	31
T26	741	0
T27	5366	0
T32	1111	0
T48	1667	0
T54	0	20
T56	0	20
T58	603	0
T61	429	0
T63	0	60
T64	0	20

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T8,T12,T25
1	0	Covered	T8,T12,T25
1	1	Covered	T69,T57,T30

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T8,T12,T25
1	0	Covered	T69,T57,T30
1	1	Covered	T8,T12,T25

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8139393	995	0	0
SrcPulseCheck_M	1103338054	1037	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8139393	995
T8	39472	2
T9	18832	0
T10	8590	0
T11	1044	0
T12	63037	3
T25	0	1
T37	0	1
T41	0	1
T42	0	1
T43	0	1
T44	0	1
T45	0	1
T46	0	1
T47	6969	0
T50	650	0
T54	505	0
T55	492	0
T56	535	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1103338054	1037
T8	472811	2
T9	922837	0
T10	987958	0
T11	232866	0
T12	249857	3
T25	0	1
T37	0	1
T41	0	1
T42	0	1
T43	0	1
T44	0	1
T45	0	1
T46	0	1
T47	174244	0
T50	325205	0
T54	48008	0
T55	239021	0
T56	13367	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T8,T12,T25
1	0	Covered	T8,T12,T25
1	1	Covered	T69,T57,T30

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T8,T12,T25
1	0	Covered	T69,T57,T30
1	1	Covered	T8,T12,T25

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1103338054	1024	0	0
SrcPulseCheck_M	8139393	1024	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1103338054	1024
T8	472811	2
T9	922837	0
T10	987958	0
T11	232866	0
T12	249857	3
T25	0	1
T37	0	1
T41	0	1
T42	0	1
T43	0	1
T44	0	1
T45	0	1
T46	0	1
T47	174244	0
T50	325205	0
T54	48008	0
T55	239021	0
T56	13367	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8139393	1024
T8	39472	2
T9	18832	0
T10	8590	0
T11	1044	0
T12	63037	3
T25	0	1
T37	0	1
T41	0	1
T42	0	1
T43	0	1
T44	0	1
T45	0	1
T46	0	1
T47	6969	0
T50	650	0
T54	505	0
T55	492	0
T56	535	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T3,T6
1	1	Covered	T69,T57,T30

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T6
1	0	Covered	T69,T57,T30
1	1	Covered	T1,T3,T6

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8139393	1947	0	0
SrcPulseCheck_M	1103338054	1987	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8139393	1947
T1	16990	4
T2	837	0
T3	11228	3
T5	11957	0
T6	28425	11
T7	0	5
T8	0	12
T9	0	6
T10	0	2
T12	0	12
T13	493	0
T14	763	0
T15	707	0
T16	402	0
T17	425	0
T27	0	1
T47	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1103338054	1987
T1	212374	4
T2	239883	0
T3	544627	3
T5	137513	0
T6	342843	11
T7	0	5
T8	0	12
T9	0	6
T10	0	2
T12	0	12
T13	61608	0
T14	374126	0
T15	88404	0
T16	197364	0
T17	59595	0
T27	0	1
T47	0	1

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T3,T6
1	1	Covered	T69,T57,T30

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T6
1	0	Covered	T69,T57,T30
1	1	Covered	T1,T3,T6

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1103338054	1975	0	0
SrcPulseCheck_M	8139393	1975	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1103338054	1975
T1	212374	4
T2	239883	0
T3	544627	3
T5	137513	0
T6	342843	11
T7	0	5
T8	0	12
T9	0	6
T10	0	2
T12	0	12
T13	61608	0
T14	374126	0
T15	88404	0
T16	197364	0
T17	59595	0
T27	0	1
T47	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8139393	1975
T1	16990	4
T2	837	0
T3	11228	3
T5	11957	0
T6	28425	11
T7	0	5
T8	0	12
T9	0	6
T10	0	2
T12	0	12
T13	493	0
T14	763	0
T15	707	0
T16	402	0
T17	425	0
T27	0	1
T47	0	1

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T4,T5,T26
1	0	Covered	T4,T5,T26
1	1	Covered	T4,T5,T26

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T4,T5,T26
1	0	Covered	T4,T5,T26
1	1	Covered	T4,T5,T26

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8139393	1300	0	0
SrcPulseCheck_M	1103338054	1334	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8139393	1300
T1	16990	0
T2	837	0
T3	11228	0
T4	5334	5
T5	11957	5
T8	0	10
T12	0	6
T13	493	0
T14	763	0
T15	707	0
T16	402	0
T17	425	0
T25	0	5
T26	0	5
T48	0	11
T49	0	5
T50	0	5
T52	0	7

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1103338054	1334
T1	212374	0
T2	239883	0
T3	544627	0
T4	266730	5
T5	137513	5
T8	0	10
T12	0	6
T13	61608	0
T14	374126	0
T15	88404	0
T16	197364	0
T17	59595	0
T25	0	5
T26	0	5
T48	0	11
T49	0	5
T50	0	5
T52	0	7

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T4,T5,T26
1	0	Covered	T4,T5,T26
1	1	Covered	T4,T5,T26

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T4,T5,T26
1	0	Covered	T4,T5,T26
1	1	Covered	T4,T5,T26

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1103338054	1324	0	0
SrcPulseCheck_M	8139393	1324	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1103338054	1324
T1	212374	0
T2	239883	0
T3	544627	0
T4	266730	5
T5	137513	5
T8	0	10
T12	0	6
T13	61608	0
T14	374126	0
T15	88404	0
T16	197364	0
T17	59595	0
T25	0	5
T26	0	5
T48	0	11
T49	0	5
T50	0	5
T52	0	7

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8139393	1324
T1	16990	0
T2	837	0
T3	11228	0
T4	5334	5
T5	11957	5
T8	0	10
T12	0	6
T13	493	0
T14	763	0
T15	707	0
T16	402	0
T17	425	0
T25	0	5
T26	0	5
T48	0	11
T49	0	5
T50	0	5
T52	0	7

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T4,T5,T26
1	0	Covered	T4,T5,T26
1	1	Covered	T4,T5,T26

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T4,T5,T26
1	0	Covered	T4,T5,T26
1	1	Covered	T4,T5,T26

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8139393	1150	0	0
SrcPulseCheck_M	1103338054	1187	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8139393	1150
T1	16990	0
T2	837	0
T3	11228	0
T4	5334	3
T5	11957	3
T8	0	6
T12	0	4
T13	493	0
T14	763	0
T15	707	0
T16	402	0
T17	425	0
T25	0	3
T26	0	3
T48	0	6
T49	0	2
T50	0	3
T52	0	5

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1103338054	1187
T1	212374	0
T2	239883	0
T3	544627	0
T4	266730	3
T5	137513	3
T8	0	6
T12	0	4
T13	61608	0
T14	374126	0
T15	88404	0
T16	197364	0
T17	59595	0
T25	0	3
T26	0	3
T48	0	6
T49	0	2
T50	0	3
T52	0	5

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T4,T5,T26
1	0	Covered	T4,T5,T26
1	1	Covered	T4,T5,T26

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T4,T5,T26
1	0	Covered	T4,T5,T26
1	1	Covered	T4,T5,T26

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1103338054	1176	0	0
SrcPulseCheck_M	8139393	1176	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1103338054	1176
T1	212374	0
T2	239883	0
T3	544627	0
T4	266730	3
T5	137513	3
T8	0	6
T12	0	4
T13	61608	0
T14	374126	0
T15	88404	0
T16	197364	0
T17	59595	0
T25	0	3
T26	0	3
T48	0	6
T49	0	2
T50	0	3
T52	0	5

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8139393	1176
T1	16990	0
T2	837	0
T3	11228	0
T4	5334	3
T5	11957	3
T8	0	6
T12	0	4
T13	493	0
T14	763	0
T15	707	0
T16	402	0
T17	425	0
T25	0	3
T26	0	3
T48	0	6
T49	0	2
T50	0	3
T52	0	5

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T27
1	0	Covered	T1,T3,T27
1	1	Covered	T1,T3,T27

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T27
1	0	Covered	T1,T3,T27
1	1	Covered	T1,T3,T27

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8139393	7014	0	0
SrcPulseCheck_M	1103338054	7057	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8139393	7014
T1	16990	65
T2	837	0
T3	11228	92
T5	11957	0
T6	28425	0
T9	0	92
T13	493	0
T14	763	0
T15	707	0
T16	402	0
T17	425	0
T27	0	51
T33	0	82
T47	0	51
T51	0	51
T53	0	82
T65	0	79
T66	0	51

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1103338054	7057
T1	212374	65
T2	239883	0
T3	544627	93
T5	137513	0
T6	342843	0
T9	0	92
T13	61608	0
T14	374126	0
T15	88404	0
T16	197364	0
T17	59595	0
T27	0	51
T33	0	82
T47	0	51
T51	0	51
T53	0	82
T65	0	79
T66	0	51

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T27
1	0	Covered	T1,T3,T27
1	1	Covered	T1,T3,T27

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T27
1	0	Covered	T1,T3,T27
1	1	Covered	T1,T3,T27

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1103338054	7046	0	0
SrcPulseCheck_M	8139393	7046	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1103338054	7046
T1	212374	65
T2	239883	0
T3	544627	93
T5	137513	0
T6	342843	0
T9	0	92
T13	61608	0
T14	374126	0
T15	88404	0
T16	197364	0
T17	59595	0
T27	0	51
T33	0	82
T47	0	51
T51	0	51
T53	0	82
T65	0	79
T66	0	51

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8139393	7046
T1	16990	65
T2	837	0
T3	11228	93
T5	11957	0
T6	28425	0
T9	0	92
T13	493	0
T14	763	0
T15	707	0
T16	402	0
T17	425	0
T27	0	51
T33	0	82
T47	0	51
T51	0	51
T53	0	82
T65	0	79
T66	0	51

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T27
1	0	Covered	T1,T3,T27
1	1	Covered	T1,T3,T27

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T27
1	0	Covered	T1,T3,T27
1	1	Covered	T1,T3,T27

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8139393	7105	0	0
SrcPulseCheck_M	1103338054	7152	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8139393	7105
T1	16990	64
T2	837	0
T3	11228	68
T5	11957	0
T6	28425	0
T9	0	85
T13	493	0
T14	763	0
T15	707	0
T16	402	0
T17	425	0
T27	0	51
T33	0	67
T47	0	75
T51	0	51
T53	0	60
T65	0	69
T66	0	51

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1103338054	7152
T1	212374	64
T2	239883	0
T3	544627	68
T5	137513	0
T6	342843	0
T9	0	86
T13	61608	0
T14	374126	0
T15	88404	0
T16	197364	0
T17	59595	0
T27	0	51
T33	0	67
T47	0	75
T51	0	51
T53	0	60
T65	0	69
T66	0	51

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T27
1	0	Covered	T1,T3,T27
1	1	Covered	T1,T3,T27

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T27
1	0	Covered	T1,T3,T27
1	1	Covered	T1,T3,T27

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1103338054	7140	0	0
SrcPulseCheck_M	8139393	7140	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1103338054	7140
T1	212374	64
T2	239883	0
T3	544627	68
T5	137513	0
T6	342843	0
T9	0	86
T13	61608	0
T14	374126	0
T15	88404	0
T16	197364	0
T17	59595	0
T27	0	51
T33	0	67
T47	0	75
T51	0	51
T53	0	60
T65	0	69
T66	0	51

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8139393	7140
T1	16990	64
T2	837	0
T3	11228	68
T5	11957	0
T6	28425	0
T9	0	86
T13	493	0
T14	763	0
T15	707	0
T16	402	0
T17	425	0
T27	0	51
T33	0	67
T47	0	75
T51	0	51
T53	0	60
T65	0	69
T66	0	51

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T27
1	0	Covered	T1,T3,T27
1	1	Covered	T1,T3,T27

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T27
1	0	Covered	T1,T3,T27
1	1	Covered	T1,T3,T27

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8139393	7011	0	0
SrcPulseCheck_M	1103338054	7056	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8139393	7011
T1	16990	65
T2	837	0
T3	11228	92
T5	11957	0
T6	28425	0
T9	0	77
T13	493	0
T14	763	0
T15	707	0
T16	402	0
T17	425	0
T27	0	51
T33	0	87
T47	0	75
T51	0	51
T53	0	76
T65	0	58
T66	0	51

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1103338054	7056
T1	212374	65
T2	239883	0
T3	544627	93
T5	137513	0
T6	342843	0
T9	0	78
T13	61608	0
T14	374126	0
T15	88404	0
T16	197364	0
T17	59595	0
T27	0	51
T33	0	87
T47	0	75
T51	0	51
T53	0	76
T65	0	58
T66	0	51

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T27
1	0	Covered	T1,T3,T27
1	1	Covered	T1,T3,T27

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T27
1	0	Covered	T1,T3,T27
1	1	Covered	T1,T3,T27

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1103338054	7047	0	0
SrcPulseCheck_M	8139393	7047	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1103338054	7047
T1	212374	65
T2	239883	0
T3	544627	93
T5	137513	0
T6	342843	0
T9	0	78
T13	61608	0
T14	374126	0
T15	88404	0
T16	197364	0
T17	59595	0
T27	0	51
T33	0	87
T47	0	75
T51	0	51
T53	0	76
T65	0	58
T66	0	51

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8139393	7047
T1	16990	65
T2	837	0
T3	11228	93
T5	11957	0
T6	28425	0
T9	0	78
T13	493	0
T14	763	0
T15	707	0
T16	402	0
T17	425	0
T27	0	51
T33	0	87
T47	0	75
T51	0	51
T53	0	76
T65	0	58
T66	0	51

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T27
1	0	Covered	T1,T3,T27
1	1	Covered	T1,T3,T27

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T27
1	0	Covered	T1,T3,T27
1	1	Covered	T1,T3,T27

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8139393	6943	0	0
SrcPulseCheck_M	1103338054	6980	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8139393	6943
T1	16990	64
T2	837	0
T3	11228	63
T5	11957	0
T6	28425	0
T9	0	67
T13	493	0
T14	763	0
T15	707	0
T16	402	0
T17	425	0
T27	0	51
T33	0	87
T47	0	75
T51	0	51
T53	0	68
T65	0	85
T66	0	51

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1103338054	6980
T1	212374	64
T2	239883	0
T3	544627	63
T5	137513	0
T6	342843	0
T9	0	67
T13	61608	0
T14	374126	0
T15	88404	0
T16	197364	0
T17	59595	0
T27	0	51
T33	0	87
T47	0	75
T51	0	51
T53	0	68
T65	0	85
T66	0	51

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T27
1	0	Covered	T1,T3,T27
1	1	Covered	T1,T3,T27

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T27
1	0	Covered	T1,T3,T27
1	1	Covered	T1,T3,T27

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1103338054	6969	0	0
SrcPulseCheck_M	8139393	6969	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1103338054	6969
T1	212374	64
T2	239883	0
T3	544627	63
T5	137513	0
T6	342843	0
T9	0	67
T13	61608	0
T14	374126	0
T15	88404	0
T16	197364	0
T17	59595	0
T27	0	51
T33	0	87
T47	0	75
T51	0	51
T53	0	68
T65	0	85
T66	0	51

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8139393	6969
T1	16990	64
T2	837	0
T3	11228	63
T5	11957	0
T6	28425	0
T9	0	67
T13	493	0
T14	763	0
T15	707	0
T16	402	0
T17	425	0
T27	0	51
T33	0	87
T47	0	75
T51	0	51
T53	0	68
T65	0	85
T66	0	51

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T27
1	0	Covered	T1,T3,T27
1	1	Covered	T69,T57,T30

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T27
1	0	Covered	T69,T57,T30
1	1	Covered	T1,T3,T27

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8139393	1169	0	0
SrcPulseCheck_M	1103338054	1208	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8139393	1169
T1	16990	4
T2	837	0
T3	11228	3
T5	11957	0
T6	28425	0
T9	0	6
T13	493	0
T14	763	0
T15	707	0
T16	402	0
T17	425	0
T27	0	1
T33	0	7
T47	0	1
T51	0	1
T53	0	8
T65	0	1
T66	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1103338054	1208
T1	212374	4
T2	239883	0
T3	544627	3
T5	137513	0
T6	342843	0
T9	0	6
T13	61608	0
T14	374126	0
T15	88404	0
T16	197364	0
T17	59595	0
T27	0	1
T33	0	7
T47	0	1
T51	0	1
T53	0	8
T65	0	1
T66	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T27
1	0	Covered	T1,T3,T27
1	1	Covered	T69,T57,T30

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T27
1	0	Covered	T69,T57,T30
1	1	Covered	T1,T3,T27

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1103338054	1196	0	0
SrcPulseCheck_M	8139393	1196	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1103338054	1196
T1	212374	4
T2	239883	0
T3	544627	3
T5	137513	0
T6	342843	0
T9	0	6
T13	61608	0
T14	374126	0
T15	88404	0
T16	197364	0
T17	59595	0
T27	0	1
T33	0	7
T47	0	1
T51	0	1
T53	0	8
T65	0	1
T66	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8139393	1196
T1	16990	4
T2	837	0
T3	11228	3
T5	11957	0
T6	28425	0
T9	0	6
T13	493	0
T14	763	0
T15	707	0
T16	402	0
T17	425	0
T27	0	1
T33	0	7
T47	0	1
T51	0	1
T53	0	8
T65	0	1
T66	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T27
1	0	Covered	T1,T3,T27
1	1	Covered	T69,T57,T30

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T27
1	0	Covered	T69,T57,T30
1	1	Covered	T1,T3,T27

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8139393	1136	0	0
SrcPulseCheck_M	1103338054	1175	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8139393	1136
T1	16990	4
T2	837	0
T3	11228	3
T5	11957	0
T6	28425	0
T9	0	6
T13	493	0
T14	763	0
T15	707	0
T16	402	0
T17	425	0
T27	0	1
T33	0	7
T47	0	1
T51	0	1
T53	0	8
T65	0	1
T66	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1103338054	1175
T1	212374	4
T2	239883	0
T3	544627	3
T5	137513	0
T6	342843	0
T9	0	6
T13	61608	0
T14	374126	0
T15	88404	0
T16	197364	0
T17	59595	0
T27	0	1
T33	0	7
T47	0	1
T51	0	1
T53	0	8
T65	0	1
T66	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T27
1	0	Covered	T1,T3,T27
1	1	Covered	T69,T57,T30

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T27
1	0	Covered	T69,T57,T30
1	1	Covered	T1,T3,T27

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1103338054	1164	0	0
SrcPulseCheck_M	8139393	1164	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1103338054	1164
T1	212374	4
T2	239883	0
T3	544627	3
T5	137513	0
T6	342843	0
T9	0	6
T13	61608	0
T14	374126	0
T15	88404	0
T16	197364	0
T17	59595	0
T27	0	1
T33	0	7
T47	0	1
T51	0	1
T53	0	8
T65	0	1
T66	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8139393	1164
T1	16990	4
T2	837	0
T3	11228	3
T5	11957	0
T6	28425	0
T9	0	6
T13	493	0
T14	763	0
T15	707	0
T16	402	0
T17	425	0
T27	0	1
T33	0	7
T47	0	1
T51	0	1
T53	0	8
T65	0	1
T66	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T27
1	0	Covered	T1,T3,T27
1	1	Covered	T69,T57,T30

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T27
1	0	Covered	T69,T57,T30
1	1	Covered	T1,T3,T27

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8139393	1148	0	0
SrcPulseCheck_M	1103338054	1187	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8139393	1148
T1	16990	4
T2	837	0
T3	11228	3
T5	11957	0
T6	28425	0
T9	0	6
T13	493	0
T14	763	0
T15	707	0
T16	402	0
T17	425	0
T27	0	1
T33	0	7
T47	0	1
T51	0	1
T53	0	8
T65	0	1
T66	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1103338054	1187
T1	212374	4
T2	239883	0
T3	544627	3
T5	137513	0
T6	342843	0
T9	0	6
T13	61608	0
T14	374126	0
T15	88404	0
T16	197364	0
T17	59595	0
T27	0	1
T33	0	7
T47	0	1
T51	0	1
T53	0	8
T65	0	1
T66	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T27
1	0	Covered	T1,T3,T27
1	1	Covered	T69,T57,T30

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T27
1	0	Covered	T69,T57,T30
1	1	Covered	T1,T3,T27

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1103338054	1176	0	0
SrcPulseCheck_M	8139393	1176	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1103338054	1176
T1	212374	4
T2	239883	0
T3	544627	3
T5	137513	0
T6	342843	0
T9	0	6
T13	61608	0
T14	374126	0
T15	88404	0
T16	197364	0
T17	59595	0
T27	0	1
T33	0	7
T47	0	1
T51	0	1
T53	0	8
T65	0	1
T66	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8139393	1176
T1	16990	4
T2	837	0
T3	11228	3
T5	11957	0
T6	28425	0
T9	0	6
T13	493	0
T14	763	0
T15	707	0
T16	402	0
T17	425	0
T27	0	1
T33	0	7
T47	0	1
T51	0	1
T53	0	8
T65	0	1
T66	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T27
1	0	Covered	T1,T3,T27
1	1	Covered	T69,T57,T30

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T27
1	0	Covered	T69,T57,T30
1	1	Covered	T1,T3,T27

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8139393	1153	0	0
SrcPulseCheck_M	1103338054	1193	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8139393	1153
T1	16990	4
T2	837	0
T3	11228	3
T5	11957	0
T6	28425	0
T9	0	6
T13	493	0
T14	763	0
T15	707	0
T16	402	0
T17	425	0
T27	0	1
T33	0	7
T47	0	1
T51	0	1
T53	0	8
T65	0	1
T66	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1103338054	1193
T1	212374	4
T2	239883	0
T3	544627	3
T5	137513	0
T6	342843	0
T9	0	6
T13	61608	0
T14	374126	0
T15	88404	0
T16	197364	0
T17	59595	0
T27	0	1
T33	0	7
T47	0	1
T51	0	1
T53	0	8
T65	0	1
T66	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T27
1	0	Covered	T1,T3,T27
1	1	Covered	T69,T57,T30

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T27
1	0	Covered	T69,T57,T30
1	1	Covered	T1,T3,T27

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1103338054	1182	0	0
SrcPulseCheck_M	8139393	1182	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1103338054	1182
T1	212374	4
T2	239883	0
T3	544627	3
T5	137513	0
T6	342843	0
T9	0	6
T13	61608	0
T14	374126	0
T15	88404	0
T16	197364	0
T17	59595	0
T27	0	1
T33	0	7
T47	0	1
T51	0	1
T53	0	8
T65	0	1
T66	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8139393	1182
T1	16990	4
T2	837	0
T3	11228	3
T5	11957	0
T6	28425	0
T9	0	6
T13	493	0
T14	763	0
T15	707	0
T16	402	0
T17	425	0
T27	0	1
T33	0	7
T47	0	1
T51	0	1
T53	0	8
T65	0	1
T66	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T3,T27

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T3,T27
1	1	Covered	T1,T3,T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8139393	7711	0	0
SrcPulseCheck_M	1103338054	7755	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8139393	7711
T1	16990	65
T2	837	0
T3	11228	92
T5	11957	0
T6	28425	11
T7	0	5
T8	0	10
T9	0	92
T10	0	2
T12	0	9
T13	493	0
T14	763	0
T15	707	0
T16	402	0
T17	425	0
T27	0	51
T47	0	51

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1103338054	7755
T1	212374	65
T2	239883	0
T3	544627	93
T5	137513	0
T6	342843	11
T7	0	5
T8	0	10
T9	0	92
T10	0	2
T12	0	9
T13	61608	0
T14	374126	0
T15	88404	0
T16	197364	0
T17	59595	0
T27	0	51
T47	0	51

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T3,T27

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T3,T27
1	1	Covered	T1,T3,T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1103338054	7744	0	0
SrcPulseCheck_M	8139393	7744	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1103338054	7744
T1	212374	65
T2	239883	0
T3	544627	93
T5	137513	0
T6	342843	11
T7	0	5
T8	0	10
T9	0	92
T10	0	2
T12	0	9
T13	61608	0
T14	374126	0
T15	88404	0
T16	197364	0
T17	59595	0
T27	0	51
T47	0	51

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8139393	7744
T1	16990	65
T2	837	0
T3	11228	93
T5	11957	0
T6	28425	11
T7	0	5
T8	0	10
T9	0	92
T10	0	2
T12	0	9
T13	493	0
T14	763	0
T15	707	0
T16	402	0
T17	425	0
T27	0	51
T47	0	51

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T3,T27

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T3,T27
1	1	Covered	T1,T3,T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8139393	7741	0	0
SrcPulseCheck_M	1103338054	7786	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8139393	7741
T1	16990	64
T2	837	0
T3	11228	68
T5	11957	0
T6	28425	9
T7	0	5
T8	0	7
T9	0	85
T10	0	2
T12	0	8
T13	493	0
T14	763	0
T15	707	0
T16	402	0
T17	425	0
T27	0	51
T47	0	75

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1103338054	7786
T1	212374	64
T2	239883	0
T3	544627	68
T5	137513	0
T6	342843	9
T7	0	5
T8	0	7
T9	0	86
T10	0	2
T12	0	8
T13	61608	0
T14	374126	0
T15	88404	0
T16	197364	0
T17	59595	0
T27	0	51
T47	0	75

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T3,T27

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T3,T27
1	1	Covered	T1,T3,T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1103338054	7777	0	0
SrcPulseCheck_M	8139393	7777	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1103338054	7777
T1	212374	64
T2	239883	0
T3	544627	68
T5	137513	0
T6	342843	9
T7	0	5
T8	0	7
T9	0	86
T10	0	2
T12	0	8
T13	61608	0
T14	374126	0
T15	88404	0
T16	197364	0
T17	59595	0
T27	0	51
T47	0	75

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8139393	7777
T1	16990	64
T2	837	0
T3	11228	68
T5	11957	0
T6	28425	9
T7	0	5
T8	0	7
T9	0	86
T10	0	2
T12	0	8
T13	493	0
T14	763	0
T15	707	0
T16	402	0
T17	425	0
T27	0	51
T47	0	75

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T3,T27

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T3,T27
1	1	Covered	T1,T3,T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8139393	7677	0	0
SrcPulseCheck_M	1103338054	7719	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8139393	7677
T1	16990	65
T2	837	0
T3	11228	92
T5	11957	0
T6	28425	9
T7	0	5
T8	0	7
T9	0	77
T10	0	2
T12	0	8
T13	493	0
T14	763	0
T15	707	0
T16	402	0
T17	425	0
T27	0	51
T47	0	75

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1103338054	7719
T1	212374	65
T2	239883	0
T3	544627	93
T5	137513	0
T6	342843	9
T7	0	5
T8	0	7
T9	0	78
T10	0	2
T12	0	8
T13	61608	0
T14	374126	0
T15	88404	0
T16	197364	0
T17	59595	0
T27	0	51
T47	0	75

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T3,T27

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T3,T27
1	1	Covered	T1,T3,T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1103338054	7709	0	0
SrcPulseCheck_M	8139393	7709	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1103338054	7709
T1	212374	65
T2	239883	0
T3	544627	93
T5	137513	0
T6	342843	9
T7	0	5
T8	0	7
T9	0	78
T10	0	2
T12	0	8
T13	61608	0
T14	374126	0
T15	88404	0
T16	197364	0
T17	59595	0
T27	0	51
T47	0	75

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8139393	7709
T1	16990	65
T2	837	0
T3	11228	93
T5	11957	0
T6	28425	9
T7	0	5
T8	0	7
T9	0	78
T10	0	2
T12	0	8
T13	493	0
T14	763	0
T15	707	0
T16	402	0
T17	425	0
T27	0	51
T47	0	75

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T3,T27

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T3,T27
1	1	Covered	T1,T3,T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8139393	7640	0	0
SrcPulseCheck_M	1103338054	7683	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8139393	7640
T1	16990	64
T2	837	0
T3	11228	63
T5	11957	0
T6	28425	9
T7	0	5
T8	0	7
T9	0	67
T10	0	2
T12	0	8
T13	493	0
T14	763	0
T15	707	0
T16	402	0
T17	425	0
T27	0	51
T47	0	75

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1103338054	7683
T1	212374	64
T2	239883	0
T3	544627	63
T5	137513	0
T6	342843	9
T7	0	5
T8	0	7
T9	0	67
T10	0	2
T12	0	8
T13	61608	0
T14	374126	0
T15	88404	0
T16	197364	0
T17	59595	0
T27	0	51
T47	0	75

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T3,T27

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T3,T27
1	1	Covered	T1,T3,T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1103338054	7672	0	0
SrcPulseCheck_M	8139393	7672	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1103338054	7672
T1	212374	64
T2	239883	0
T3	544627	63
T5	137513	0
T6	342843	9
T7	0	5
T8	0	7
T9	0	67
T10	0	2
T12	0	8
T13	61608	0
T14	374126	0
T15	88404	0
T16	197364	0
T17	59595	0
T27	0	51
T47	0	75

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8139393	7672
T1	16990	64
T2	837	0
T3	11228	63
T5	11957	0
T6	28425	9
T7	0	5
T8	0	7
T9	0	67
T10	0	2
T12	0	8
T13	493	0
T14	763	0
T15	707	0
T16	402	0
T17	425	0
T27	0	51
T47	0	75

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T3,T6
1	1	Covered	T69,T57,T30

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T6
1	0	Covered	T69,T57,T30
1	1	Covered	T1,T3,T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8139393	1867	0	0
SrcPulseCheck_M	1103338054	1904	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8139393	1867
T1	16990	4
T2	837	0
T3	11228	3
T5	11957	0
T6	28425	11
T7	0	5
T8	0	10
T9	0	6
T10	0	2
T12	0	9
T13	493	0
T14	763	0
T15	707	0
T16	402	0
T17	425	0
T27	0	1
T47	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1103338054	1904
T1	212374	4
T2	239883	0
T3	544627	3
T5	137513	0
T6	342843	11
T7	0	5
T8	0	10
T9	0	6
T10	0	2
T12	0	9
T13	61608	0
T14	374126	0
T15	88404	0
T16	197364	0
T17	59595	0
T27	0	1
T47	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T3,T6
1	1	Covered	T69,T57,T30

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T6
1	0	Covered	T69,T57,T30
1	1	Covered	T1,T3,T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1103338054	1894	0	0
SrcPulseCheck_M	8139393	1894	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1103338054	1894
T1	212374	4
T2	239883	0
T3	544627	3
T5	137513	0
T6	342843	11
T7	0	5
T8	0	10
T9	0	6
T10	0	2
T12	0	9
T13	61608	0
T14	374126	0
T15	88404	0
T16	197364	0
T17	59595	0
T27	0	1
T47	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8139393	1894
T1	16990	4
T2	837	0
T3	11228	3
T5	11957	0
T6	28425	11
T7	0	5
T8	0	10
T9	0	6
T10	0	2
T12	0	9
T13	493	0
T14	763	0
T15	707	0
T16	402	0
T17	425	0
T27	0	1
T47	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T3,T6
1	1	Covered	T69,T57,T30

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T6
1	0	Covered	T69,T57,T30
1	1	Covered	T1,T3,T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8139393	1784	0	0
SrcPulseCheck_M	1103338054	1817	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8139393	1784
T1	16990	4
T2	837	0
T3	11228	3
T5	11957	0
T6	28425	9
T7	0	5
T8	0	7
T9	0	6
T10	0	2
T12	0	8
T13	493	0
T14	763	0
T15	707	0
T16	402	0
T17	425	0
T27	0	1
T47	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1103338054	1817
T1	212374	4
T2	239883	0
T3	544627	3
T5	137513	0
T6	342843	9
T7	0	5
T8	0	7
T9	0	6
T10	0	2
T12	0	8
T13	61608	0
T14	374126	0
T15	88404	0
T16	197364	0
T17	59595	0
T27	0	1
T47	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T3,T6
1	1	Covered	T69,T57,T30

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T6
1	0	Covered	T69,T57,T30
1	1	Covered	T1,T3,T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1103338054	1810	0	0
SrcPulseCheck_M	8139393	1810	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1103338054	1810
T1	212374	4
T2	239883	0
T3	544627	3
T5	137513	0
T6	342843	9
T7	0	5
T8	0	7
T9	0	6
T10	0	2
T12	0	8
T13	61608	0
T14	374126	0
T15	88404	0
T16	197364	0
T17	59595	0
T27	0	1
T47	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8139393	1810
T1	16990	4
T2	837	0
T3	11228	3
T5	11957	0
T6	28425	9
T7	0	5
T8	0	7
T9	0	6
T10	0	2
T12	0	8
T13	493	0
T14	763	0
T15	707	0
T16	402	0
T17	425	0
T27	0	1
T47	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T3,T6
1	1	Covered	T69,T57,T30

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T6
1	0	Covered	T69,T57,T30
1	1	Covered	T1,T3,T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8139393	1812	0	0
SrcPulseCheck_M	1103338054	1851	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8139393	1812
T1	16990	4
T2	837	0
T3	11228	3
T5	11957	0
T6	28425	9
T7	0	5
T8	0	7
T9	0	6
T10	0	2
T12	0	8
T13	493	0
T14	763	0
T15	707	0
T16	402	0
T17	425	0
T27	0	1
T47	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1103338054	1851
T1	212374	4
T2	239883	0
T3	544627	3
T5	137513	0
T6	342843	9
T7	0	5
T8	0	7
T9	0	6
T10	0	2
T12	0	8
T13	61608	0
T14	374126	0
T15	88404	0
T16	197364	0
T17	59595	0
T27	0	1
T47	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T3,T6
1	1	Covered	T69,T57,T30

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T6
1	0	Covered	T69,T57,T30
1	1	Covered	T1,T3,T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1103338054	1841	0	0
SrcPulseCheck_M	8139393	1841	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1103338054	1841
T1	212374	4
T2	239883	0
T3	544627	3
T5	137513	0
T6	342843	9
T7	0	5
T8	0	7
T9	0	6
T10	0	2
T12	0	8
T13	61608	0
T14	374126	0
T15	88404	0
T16	197364	0
T17	59595	0
T27	0	1
T47	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8139393	1841
T1	16990	4
T2	837	0
T3	11228	3
T5	11957	0
T6	28425	9
T7	0	5
T8	0	7
T9	0	6
T10	0	2
T12	0	8
T13	493	0
T14	763	0
T15	707	0
T16	402	0
T17	425	0
T27	0	1
T47	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T3,T6
1	1	Covered	T69,T57,T30

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T6
1	0	Covered	T69,T57,T30
1	1	Covered	T1,T3,T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8139393	1794	0	0
SrcPulseCheck_M	1103338054	1831	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8139393	1794
T1	16990	4
T2	837	0
T3	11228	3
T5	11957	0
T6	28425	9
T7	0	5
T8	0	7
T9	0	6
T10	0	2
T12	0	8
T13	493	0
T14	763	0
T15	707	0
T16	402	0
T17	425	0
T27	0	1
T47	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1103338054	1831
T1	212374	4
T2	239883	0
T3	544627	3
T5	137513	0
T6	342843	9
T7	0	5
T8	0	7
T9	0	6
T10	0	2
T12	0	8
T13	61608	0
T14	374126	0
T15	88404	0
T16	197364	0
T17	59595	0
T27	0	1
T47	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T3,T6
1	1	Covered	T69,T57,T30

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T6
1	0	Covered	T69,T57,T30
1	1	Covered	T1,T3,T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1103338054	1821	0	0
SrcPulseCheck_M	8139393	1821	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1103338054	1821
T1	212374	4
T2	239883	0
T3	544627	3
T5	137513	0
T6	342843	9
T7	0	5
T8	0	7
T9	0	6
T10	0	2
T12	0	8
T13	61608	0
T14	374126	0
T15	88404	0
T16	197364	0
T17	59595	0
T27	0	1
T47	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8139393	1821
T1	16990	4
T2	837	0
T3	11228	3
T5	11957	0
T6	28425	9
T7	0	5
T8	0	7
T9	0	6
T10	0	2
T12	0	8
T13	493	0
T14	763	0
T15	707	0
T16	402	0
T17	425	0
T27	0	1
T47	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T3,T6
1	1	Covered	T69,T57,T30

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T6
1	0	Covered	T69,T57,T30
1	1	Covered	T1,T3,T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8139393	1871	0	0
SrcPulseCheck_M	1103338054	1911	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8139393	1871
T1	16990	4
T2	837	0
T3	11228	3
T5	11957	0
T6	28425	11
T7	0	5
T8	0	10
T9	0	6
T10	0	2
T12	0	9
T13	493	0
T14	763	0
T15	707	0
T16	402	0
T17	425	0
T27	0	1
T47	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1103338054	1911
T1	212374	4
T2	239883	0
T3	544627	3
T5	137513	0
T6	342843	11
T7	0	5
T8	0	10
T9	0	6
T10	0	2
T12	0	9
T13	61608	0
T14	374126	0
T15	88404	0
T16	197364	0
T17	59595	0
T27	0	1
T47	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T3,T6
1	1	Covered	T69,T57,T30

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T6
1	0	Covered	T69,T57,T30
1	1	Covered	T1,T3,T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1103338054	1898	0	0
SrcPulseCheck_M	8139393	1898	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1103338054	1898
T1	212374	4
T2	239883	0
T3	544627	3
T5	137513	0
T6	342843	11
T7	0	5
T8	0	10
T9	0	6
T10	0	2
T12	0	9
T13	61608	0
T14	374126	0
T15	88404	0
T16	197364	0
T17	59595	0
T27	0	1
T47	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8139393	1898
T1	16990	4
T2	837	0
T3	11228	3
T5	11957	0
T6	28425	11
T7	0	5
T8	0	10
T9	0	6
T10	0	2
T12	0	9
T13	493	0
T14	763	0
T15	707	0
T16	402	0
T17	425	0
T27	0	1
T47	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T3,T6
1	1	Covered	T69,T57,T30

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T6
1	0	Covered	T69,T57,T30
1	1	Covered	T1,T3,T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8139393	1793	0	0
SrcPulseCheck_M	1103338054	1834	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8139393	1793
T1	16990	4
T2	837	0
T3	11228	3
T5	11957	0
T6	28425	9
T7	0	5
T8	0	7
T9	0	6
T10	0	2
T12	0	8
T13	493	0
T14	763	0
T15	707	0
T16	402	0
T17	425	0
T27	0	1
T47	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1103338054	1834
T1	212374	4
T2	239883	0
T3	544627	3
T5	137513	0
T6	342843	9
T7	0	5
T8	0	7
T9	0	6
T10	0	2
T12	0	8
T13	61608	0
T14	374126	0
T15	88404	0
T16	197364	0
T17	59595	0
T27	0	1
T47	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T3,T6
1	1	Covered	T69,T57,T30

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T6
1	0	Covered	T69,T57,T30
1	1	Covered	T1,T3,T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1103338054	1824	0	0
SrcPulseCheck_M	8139393	1824	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1103338054	1824
T1	212374	4
T2	239883	0
T3	544627	3
T5	137513	0
T6	342843	9
T7	0	5
T8	0	7
T9	0	6
T10	0	2
T12	0	8
T13	61608	0
T14	374126	0
T15	88404	0
T16	197364	0
T17	59595	0
T27	0	1
T47	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8139393	1824
T1	16990	4
T2	837	0
T3	11228	3
T5	11957	0
T6	28425	9
T7	0	5
T8	0	7
T9	0	6
T10	0	2
T12	0	8
T13	493	0
T14	763	0
T15	707	0
T16	402	0
T17	425	0
T27	0	1
T47	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T3,T6
1	1	Covered	T69,T57,T30

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T6
1	0	Covered	T69,T57,T30
1	1	Covered	T1,T3,T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8139393	1822	0	0
SrcPulseCheck_M	1103338054	1864	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8139393	1822
T1	16990	4
T2	837	0
T3	11228	3
T5	11957	0
T6	28425	9
T7	0	5
T8	0	7
T9	0	6
T10	0	2
T12	0	8
T13	493	0
T14	763	0
T15	707	0
T16	402	0
T17	425	0
T27	0	1
T47	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1103338054	1864
T1	212374	4
T2	239883	0
T3	544627	3
T5	137513	0
T6	342843	9
T7	0	5
T8	0	7
T9	0	6
T10	0	2
T12	0	8
T13	61608	0
T14	374126	0
T15	88404	0
T16	197364	0
T17	59595	0
T27	0	1
T47	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T3,T6
1	1	Covered	T69,T57,T30

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T6
1	0	Covered	T69,T57,T30
1	1	Covered	T1,T3,T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1103338054	1852	0	0
SrcPulseCheck_M	8139393	1852	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1103338054	1852
T1	212374	4
T2	239883	0
T3	544627	3
T5	137513	0
T6	342843	9
T7	0	5
T8	0	7
T9	0	6
T10	0	2
T12	0	8
T13	61608	0
T14	374126	0
T15	88404	0
T16	197364	0
T17	59595	0
T27	0	1
T47	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8139393	1852
T1	16990	4
T2	837	0
T3	11228	3
T5	11957	0
T6	28425	9
T7	0	5
T8	0	7
T9	0	6
T10	0	2
T12	0	8
T13	493	0
T14	763	0
T15	707	0
T16	402	0
T17	425	0
T27	0	1
T47	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T3,T6
1	1	Covered	T69,T57,T30

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T6
1	0	Covered	T69,T57,T30
1	1	Covered	T1,T3,T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8139393	1787	0	0
SrcPulseCheck_M	1103338054	1827	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8139393	1787
T1	16990	4
T2	837	0
T3	11228	3
T5	11957	0
T6	28425	9
T7	0	5
T8	0	7
T9	0	6
T10	0	2
T12	0	8
T13	493	0
T14	763	0
T15	707	0
T16	402	0
T17	425	0
T27	0	1
T47	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1103338054	1827
T1	212374	4
T2	239883	0
T3	544627	3
T5	137513	0
T6	342843	9
T7	0	5
T8	0	7
T9	0	6
T10	0	2
T12	0	8
T13	61608	0
T14	374126	0
T15	88404	0
T16	197364	0
T17	59595	0
T27	0	1
T47	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T3,T6
1	1	Covered	T69,T57,T30

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T3,T6
1	0	Covered	T69,T57,T30
1	1	Covered	T1,T3,T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1103338054	1816	0	0
SrcPulseCheck_M	8139393	1816	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1103338054	1816
T1	212374	4
T2	239883	0
T3	544627	3
T5	137513	0
T6	342843	9
T7	0	5
T8	0	7
T9	0	6
T10	0	2
T12	0	8
T13	61608	0
T14	374126	0
T15	88404	0
T16	197364	0
T17	59595	0
T27	0	1
T47	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8139393	1816
T1	16990	4
T2	837	0
T3	11228	3
T5	11957	0
T6	28425	9
T7	0	5
T8	0	7
T9	0	6
T10	0	2
T12	0	8
T13	493	0
T14	763	0
T15	707	0
T16	402	0
T17	425	0
T27	0	1
T47	0	1

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_ec_rst_ctl_cdc

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arb

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_ulp_ac_debounce_ctl_cdc