T163 |
/workspace/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.3050486256 |
|
|
Mar 31 01:20:27 PM PDT 24 |
Mar 31 01:20:30 PM PDT 24 |
2454302526 ps |
T164 |
/workspace/coverage/default/24.sysrst_ctrl_ultra_low_pwr.835317957 |
|
|
Mar 31 01:20:34 PM PDT 24 |
Mar 31 01:20:38 PM PDT 24 |
8255777694 ps |
T135 |
/workspace/coverage/default/4.sysrst_ctrl_ultra_low_pwr.3333597230 |
|
|
Mar 31 01:19:27 PM PDT 24 |
Mar 31 01:19:30 PM PDT 24 |
3590937936 ps |
T165 |
/workspace/coverage/default/18.sysrst_ctrl_smoke.3622670754 |
|
|
Mar 31 01:20:13 PM PDT 24 |
Mar 31 01:20:16 PM PDT 24 |
2119686151 ps |
T166 |
/workspace/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.967478178 |
|
|
Mar 31 01:19:53 PM PDT 24 |
Mar 31 01:19:55 PM PDT 24 |
2700294061 ps |
T353 |
/workspace/coverage/default/20.sysrst_ctrl_stress_all.1394550341 |
|
|
Mar 31 01:20:24 PM PDT 24 |
Mar 31 01:25:50 PM PDT 24 |
136342155695 ps |
T605 |
/workspace/coverage/default/4.sysrst_ctrl_auto_blk_key_output.3842782565 |
|
|
Mar 31 01:19:30 PM PDT 24 |
Mar 31 01:19:36 PM PDT 24 |
3591019282 ps |
T273 |
/workspace/coverage/default/0.sysrst_ctrl_combo_detect.497568798 |
|
|
Mar 31 01:19:09 PM PDT 24 |
Mar 31 01:25:23 PM PDT 24 |
148640355718 ps |
T266 |
/workspace/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.3660760764 |
|
|
Mar 31 01:21:26 PM PDT 24 |
Mar 31 01:23:30 PM PDT 24 |
88814877100 ps |
T606 |
/workspace/coverage/default/7.sysrst_ctrl_ultra_low_pwr.3885417043 |
|
|
Mar 31 01:19:41 PM PDT 24 |
Mar 31 01:19:56 PM PDT 24 |
547087898347 ps |
T607 |
/workspace/coverage/default/33.sysrst_ctrl_in_out_inverted.935715353 |
|
|
Mar 31 01:20:56 PM PDT 24 |
Mar 31 01:21:04 PM PDT 24 |
2489943516 ps |
T608 |
/workspace/coverage/default/12.sysrst_ctrl_pin_override_test.3358905742 |
|
|
Mar 31 01:20:03 PM PDT 24 |
Mar 31 01:20:10 PM PDT 24 |
2511072873 ps |
T136 |
/workspace/coverage/default/12.sysrst_ctrl_ultra_low_pwr.3247000677 |
|
|
Mar 31 01:20:02 PM PDT 24 |
Mar 31 01:20:10 PM PDT 24 |
4549638808 ps |
T609 |
/workspace/coverage/default/21.sysrst_ctrl_smoke.928295984 |
|
|
Mar 31 01:20:26 PM PDT 24 |
Mar 31 01:20:29 PM PDT 24 |
2112542639 ps |
T610 |
/workspace/coverage/default/9.sysrst_ctrl_smoke.3995144578 |
|
|
Mar 31 01:19:47 PM PDT 24 |
Mar 31 01:19:48 PM PDT 24 |
2175747416 ps |
T611 |
/workspace/coverage/default/26.sysrst_ctrl_alert_test.3957300516 |
|
|
Mar 31 01:20:41 PM PDT 24 |
Mar 31 01:20:47 PM PDT 24 |
2011723192 ps |
T612 |
/workspace/coverage/default/0.sysrst_ctrl_stress_all.3668024792 |
|
|
Mar 31 01:19:10 PM PDT 24 |
Mar 31 01:19:39 PM PDT 24 |
10287989756 ps |
T396 |
/workspace/coverage/default/32.sysrst_ctrl_ultra_low_pwr.4187484729 |
|
|
Mar 31 01:20:54 PM PDT 24 |
Mar 31 01:29:41 PM PDT 24 |
1780146057369 ps |
T613 |
/workspace/coverage/default/3.sysrst_ctrl_alert_test.3075737245 |
|
|
Mar 31 01:19:27 PM PDT 24 |
Mar 31 01:19:33 PM PDT 24 |
2012576181 ps |
T283 |
/workspace/coverage/default/27.sysrst_ctrl_stress_all.2521303447 |
|
|
Mar 31 01:20:44 PM PDT 24 |
Mar 31 01:26:34 PM PDT 24 |
264345899341 ps |
T389 |
/workspace/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.4198832479 |
|
|
Mar 31 01:21:43 PM PDT 24 |
Mar 31 01:22:50 PM PDT 24 |
27082554354 ps |
T614 |
/workspace/coverage/default/11.sysrst_ctrl_pin_access_test.1499097503 |
|
|
Mar 31 01:19:52 PM PDT 24 |
Mar 31 01:19:59 PM PDT 24 |
2148097823 ps |
T615 |
/workspace/coverage/default/33.sysrst_ctrl_ultra_low_pwr.3314073160 |
|
|
Mar 31 01:21:01 PM PDT 24 |
Mar 31 01:21:44 PM PDT 24 |
2803262728415 ps |
T99 |
/workspace/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.3819659979 |
|
|
Mar 31 01:20:01 PM PDT 24 |
Mar 31 01:21:28 PM PDT 24 |
438582612915 ps |
T221 |
/workspace/coverage/default/14.sysrst_ctrl_in_out_inverted.3050346659 |
|
|
Mar 31 01:20:03 PM PDT 24 |
Mar 31 01:20:11 PM PDT 24 |
2460549853 ps |
T222 |
/workspace/coverage/default/31.sysrst_ctrl_auto_blk_key_output.186211067 |
|
|
Mar 31 01:20:54 PM PDT 24 |
Mar 31 01:20:58 PM PDT 24 |
3820954313 ps |
T223 |
/workspace/coverage/default/27.sysrst_ctrl_ultra_low_pwr.3715556526 |
|
|
Mar 31 01:20:40 PM PDT 24 |
Mar 31 01:20:44 PM PDT 24 |
7656573532 ps |
T224 |
/workspace/coverage/default/34.sysrst_ctrl_edge_detect.1715072578 |
|
|
Mar 31 01:21:03 PM PDT 24 |
Mar 31 01:21:15 PM PDT 24 |
3801589378 ps |
T225 |
/workspace/coverage/default/3.sysrst_ctrl_smoke.196068334 |
|
|
Mar 31 01:19:21 PM PDT 24 |
Mar 31 01:19:22 PM PDT 24 |
2196291239 ps |
T226 |
/workspace/coverage/default/18.sysrst_ctrl_auto_blk_key_output.3040587837 |
|
|
Mar 31 01:20:14 PM PDT 24 |
Mar 31 01:20:17 PM PDT 24 |
3483634962 ps |
T227 |
/workspace/coverage/default/34.sysrst_ctrl_auto_blk_key_output.2929638731 |
|
|
Mar 31 01:21:02 PM PDT 24 |
Mar 31 01:21:12 PM PDT 24 |
3429981461 ps |
T228 |
/workspace/coverage/default/7.sysrst_ctrl_combo_detect.1839009319 |
|
|
Mar 31 01:19:42 PM PDT 24 |
Mar 31 01:25:41 PM PDT 24 |
128252392021 ps |
T100 |
/workspace/coverage/default/15.sysrst_ctrl_combo_detect.3337187235 |
|
|
Mar 31 01:20:08 PM PDT 24 |
Mar 31 01:22:33 PM PDT 24 |
101149592803 ps |
T616 |
/workspace/coverage/default/30.sysrst_ctrl_alert_test.356830469 |
|
|
Mar 31 01:20:53 PM PDT 24 |
Mar 31 01:20:56 PM PDT 24 |
2036197545 ps |
T617 |
/workspace/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.2716178601 |
|
|
Mar 31 01:20:08 PM PDT 24 |
Mar 31 01:20:19 PM PDT 24 |
4489115364 ps |
T618 |
/workspace/coverage/default/36.sysrst_ctrl_in_out_inverted.512513967 |
|
|
Mar 31 01:21:10 PM PDT 24 |
Mar 31 01:21:12 PM PDT 24 |
2500003613 ps |
T619 |
/workspace/coverage/default/48.sysrst_ctrl_pin_override_test.344071169 |
|
|
Mar 31 01:21:35 PM PDT 24 |
Mar 31 01:21:37 PM PDT 24 |
2525886538 ps |
T101 |
/workspace/coverage/default/28.sysrst_ctrl_combo_detect.2977203220 |
|
|
Mar 31 01:20:47 PM PDT 24 |
Mar 31 01:22:37 PM PDT 24 |
158401498458 ps |
T620 |
/workspace/coverage/default/47.sysrst_ctrl_alert_test.3734477378 |
|
|
Mar 31 01:21:36 PM PDT 24 |
Mar 31 01:21:41 PM PDT 24 |
2016537125 ps |
T621 |
/workspace/coverage/default/18.sysrst_ctrl_ec_pwr_on_rst.2670126539 |
|
|
Mar 31 01:20:15 PM PDT 24 |
Mar 31 01:20:18 PM PDT 24 |
3930227429 ps |
T622 |
/workspace/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.314118609 |
|
|
Mar 31 01:20:10 PM PDT 24 |
Mar 31 01:20:13 PM PDT 24 |
3703344967 ps |
T623 |
/workspace/coverage/default/12.sysrst_ctrl_in_out_inverted.967111781 |
|
|
Mar 31 01:20:09 PM PDT 24 |
Mar 31 01:20:12 PM PDT 24 |
2488924884 ps |
T138 |
/workspace/coverage/default/2.sysrst_ctrl_edge_detect.372148159 |
|
|
Mar 31 01:19:22 PM PDT 24 |
Mar 31 01:19:25 PM PDT 24 |
4633663233 ps |
T624 |
/workspace/coverage/default/45.sysrst_ctrl_smoke.2983136854 |
|
|
Mar 31 01:21:42 PM PDT 24 |
Mar 31 01:21:48 PM PDT 24 |
2112820968 ps |
T625 |
/workspace/coverage/default/31.sysrst_ctrl_combo_detect.227888877 |
|
|
Mar 31 01:20:55 PM PDT 24 |
Mar 31 01:27:49 PM PDT 24 |
150152939794 ps |
T626 |
/workspace/coverage/default/2.sysrst_ctrl_pin_override_test.3155272599 |
|
|
Mar 31 01:19:22 PM PDT 24 |
Mar 31 01:19:30 PM PDT 24 |
2510898113 ps |
T627 |
/workspace/coverage/default/39.sysrst_ctrl_auto_blk_key_output.1204884020 |
|
|
Mar 31 01:21:18 PM PDT 24 |
Mar 31 01:21:27 PM PDT 24 |
3060342879 ps |
T628 |
/workspace/coverage/default/18.sysrst_ctrl_combo_detect.2760570015 |
|
|
Mar 31 01:20:14 PM PDT 24 |
Mar 31 01:21:01 PM PDT 24 |
149103234195 ps |
T629 |
/workspace/coverage/default/36.sysrst_ctrl_ec_pwr_on_rst.3665795666 |
|
|
Mar 31 01:21:08 PM PDT 24 |
Mar 31 01:21:12 PM PDT 24 |
3521443524 ps |
T630 |
/workspace/coverage/default/20.sysrst_ctrl_combo_detect_with_pre_cond.1076146414 |
|
|
Mar 31 01:20:21 PM PDT 24 |
Mar 31 01:21:40 PM PDT 24 |
116037269677 ps |
T631 |
/workspace/coverage/default/43.sysrst_ctrl_alert_test.2732225578 |
|
|
Mar 31 01:21:22 PM PDT 24 |
Mar 31 01:21:25 PM PDT 24 |
2018181120 ps |
T268 |
/workspace/coverage/default/39.sysrst_ctrl_combo_detect_with_pre_cond.179198407 |
|
|
Mar 31 01:21:17 PM PDT 24 |
Mar 31 01:21:44 PM PDT 24 |
37515347420 ps |
T632 |
/workspace/coverage/default/1.sysrst_ctrl_pin_override_test.4187482805 |
|
|
Mar 31 01:19:17 PM PDT 24 |
Mar 31 01:19:20 PM PDT 24 |
2535351140 ps |
T633 |
/workspace/coverage/default/14.sysrst_ctrl_auto_blk_key_output.3617133335 |
|
|
Mar 31 01:20:08 PM PDT 24 |
Mar 31 01:20:18 PM PDT 24 |
3693811539 ps |
T634 |
/workspace/coverage/default/7.sysrst_ctrl_alert_test.1673922635 |
|
|
Mar 31 01:19:47 PM PDT 24 |
Mar 31 01:19:49 PM PDT 24 |
2057666777 ps |
T635 |
/workspace/coverage/default/20.sysrst_ctrl_pin_access_test.2659418512 |
|
|
Mar 31 01:20:21 PM PDT 24 |
Mar 31 01:20:24 PM PDT 24 |
2211862145 ps |
T636 |
/workspace/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.2893997978 |
|
|
Mar 31 01:21:07 PM PDT 24 |
Mar 31 01:21:29 PM PDT 24 |
30101983339 ps |
T637 |
/workspace/coverage/default/23.sysrst_ctrl_pin_access_test.791264886 |
|
|
Mar 31 01:20:31 PM PDT 24 |
Mar 31 01:20:33 PM PDT 24 |
2270321519 ps |
T638 |
/workspace/coverage/default/1.sysrst_ctrl_flash_wr_prot_out.418248889 |
|
|
Mar 31 01:19:16 PM PDT 24 |
Mar 31 01:19:18 PM PDT 24 |
2661334390 ps |
T220 |
/workspace/coverage/default/24.sysrst_ctrl_edge_detect.3039554427 |
|
|
Mar 31 01:20:34 PM PDT 24 |
Mar 31 01:20:36 PM PDT 24 |
2736855360 ps |
T639 |
/workspace/coverage/default/13.sysrst_ctrl_edge_detect.2385692915 |
|
|
Mar 31 01:20:06 PM PDT 24 |
Mar 31 01:20:07 PM PDT 24 |
2516256115 ps |
T640 |
/workspace/coverage/default/26.sysrst_ctrl_pin_access_test.4086265754 |
|
|
Mar 31 01:20:43 PM PDT 24 |
Mar 31 01:20:45 PM PDT 24 |
2092938986 ps |
T641 |
/workspace/coverage/default/12.sysrst_ctrl_alert_test.389842641 |
|
|
Mar 31 01:20:00 PM PDT 24 |
Mar 31 01:20:06 PM PDT 24 |
2011513183 ps |
T267 |
/workspace/coverage/default/1.sysrst_ctrl_combo_detect.3949102225 |
|
|
Mar 31 01:19:18 PM PDT 24 |
Mar 31 01:20:41 PM PDT 24 |
111828840738 ps |
T642 |
/workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.3795936459 |
|
|
Mar 31 01:21:36 PM PDT 24 |
Mar 31 01:21:37 PM PDT 24 |
3607420924 ps |
T643 |
/workspace/coverage/default/15.sysrst_ctrl_auto_blk_key_output.2013835029 |
|
|
Mar 31 01:20:09 PM PDT 24 |
Mar 31 01:20:18 PM PDT 24 |
3398112268 ps |
T644 |
/workspace/coverage/default/30.sysrst_ctrl_pin_access_test.2755156039 |
|
|
Mar 31 01:20:53 PM PDT 24 |
Mar 31 01:20:59 PM PDT 24 |
2139118362 ps |
T645 |
/workspace/coverage/default/37.sysrst_ctrl_pin_access_test.1222277939 |
|
|
Mar 31 01:21:09 PM PDT 24 |
Mar 31 01:21:11 PM PDT 24 |
2086381843 ps |
T646 |
/workspace/coverage/default/31.sysrst_ctrl_pin_override_test.1080780673 |
|
|
Mar 31 01:20:54 PM PDT 24 |
Mar 31 01:20:57 PM PDT 24 |
2531847714 ps |
T647 |
/workspace/coverage/default/17.sysrst_ctrl_edge_detect.3370603125 |
|
|
Mar 31 01:20:13 PM PDT 24 |
Mar 31 01:20:22 PM PDT 24 |
2958953361 ps |
T199 |
/workspace/coverage/default/12.sysrst_ctrl_edge_detect.144545656 |
|
|
Mar 31 01:20:06 PM PDT 24 |
Mar 31 01:20:09 PM PDT 24 |
3761175260 ps |
T274 |
/workspace/coverage/default/9.sysrst_ctrl_combo_detect.1040195236 |
|
|
Mar 31 01:19:46 PM PDT 24 |
Mar 31 01:20:16 PM PDT 24 |
42437586040 ps |
T648 |
/workspace/coverage/default/2.sysrst_ctrl_alert_test.1283423121 |
|
|
Mar 31 01:19:22 PM PDT 24 |
Mar 31 01:19:24 PM PDT 24 |
2027957509 ps |
T649 |
/workspace/coverage/default/31.sysrst_ctrl_alert_test.4153074357 |
|
|
Mar 31 01:20:55 PM PDT 24 |
Mar 31 01:21:01 PM PDT 24 |
2013848200 ps |
T650 |
/workspace/coverage/default/29.sysrst_ctrl_auto_blk_key_output.708998535 |
|
|
Mar 31 01:20:46 PM PDT 24 |
Mar 31 01:20:48 PM PDT 24 |
3150784025 ps |
T211 |
/workspace/coverage/default/39.sysrst_ctrl_edge_detect.3825828721 |
|
|
Mar 31 01:21:20 PM PDT 24 |
Mar 31 01:21:24 PM PDT 24 |
4237531662 ps |
T358 |
/workspace/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.3839045264 |
|
|
Mar 31 01:21:49 PM PDT 24 |
Mar 31 01:24:23 PM PDT 24 |
59074405509 ps |
T651 |
/workspace/coverage/default/16.sysrst_ctrl_pin_access_test.1669538002 |
|
|
Mar 31 01:20:09 PM PDT 24 |
Mar 31 01:20:12 PM PDT 24 |
2141059984 ps |
T652 |
/workspace/coverage/default/26.sysrst_ctrl_combo_detect_with_pre_cond.1576955449 |
|
|
Mar 31 01:20:39 PM PDT 24 |
Mar 31 01:22:05 PM PDT 24 |
31822516927 ps |
T653 |
/workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.698007483 |
|
|
Mar 31 01:19:24 PM PDT 24 |
Mar 31 01:19:31 PM PDT 24 |
2333837585 ps |
T654 |
/workspace/coverage/default/41.sysrst_ctrl_stress_all.2563430027 |
|
|
Mar 31 01:21:20 PM PDT 24 |
Mar 31 01:21:45 PM PDT 24 |
9178142202 ps |
T262 |
/workspace/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.3573917871 |
|
|
Mar 31 01:20:09 PM PDT 24 |
Mar 31 01:23:14 PM PDT 24 |
71841267889 ps |
T655 |
/workspace/coverage/default/48.sysrst_ctrl_pin_access_test.1587430315 |
|
|
Mar 31 01:21:34 PM PDT 24 |
Mar 31 01:21:38 PM PDT 24 |
2030918286 ps |
T656 |
/workspace/coverage/default/31.sysrst_ctrl_ec_pwr_on_rst.68550905 |
|
|
Mar 31 01:20:55 PM PDT 24 |
Mar 31 01:21:01 PM PDT 24 |
3437696686 ps |
T657 |
/workspace/coverage/default/37.sysrst_ctrl_combo_detect.2966444548 |
|
|
Mar 31 01:21:10 PM PDT 24 |
Mar 31 01:21:54 PM PDT 24 |
106304236704 ps |
T658 |
/workspace/coverage/default/31.sysrst_ctrl_pin_access_test.1876321321 |
|
|
Mar 31 01:20:54 PM PDT 24 |
Mar 31 01:20:56 PM PDT 24 |
2152267123 ps |
T365 |
/workspace/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.1449740771 |
|
|
Mar 31 01:21:40 PM PDT 24 |
Mar 31 01:22:04 PM PDT 24 |
80464333072 ps |
T175 |
/workspace/coverage/default/43.sysrst_ctrl_stress_all.2684281917 |
|
|
Mar 31 01:21:22 PM PDT 24 |
Mar 31 01:21:29 PM PDT 24 |
9747093523 ps |
T659 |
/workspace/coverage/default/8.sysrst_ctrl_pin_access_test.4010241194 |
|
|
Mar 31 01:19:47 PM PDT 24 |
Mar 31 01:19:49 PM PDT 24 |
2269253344 ps |
T660 |
/workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.1654111243 |
|
|
Mar 31 01:21:44 PM PDT 24 |
Mar 31 01:29:05 PM PDT 24 |
170257544441 ps |
T290 |
/workspace/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.1752863517 |
|
|
Mar 31 01:20:11 PM PDT 24 |
Mar 31 01:20:40 PM PDT 24 |
10881112603 ps |
T661 |
/workspace/coverage/default/0.sysrst_ctrl_ec_pwr_on_rst.3045672843 |
|
|
Mar 31 01:19:10 PM PDT 24 |
Mar 31 01:19:12 PM PDT 24 |
2833654904 ps |
T176 |
/workspace/coverage/default/23.sysrst_ctrl_edge_detect.206538083 |
|
|
Mar 31 01:20:37 PM PDT 24 |
Mar 31 01:20:46 PM PDT 24 |
3361195776 ps |
T662 |
/workspace/coverage/default/27.sysrst_ctrl_flash_wr_prot_out.2309183809 |
|
|
Mar 31 01:20:41 PM PDT 24 |
Mar 31 01:20:46 PM PDT 24 |
2613520768 ps |
T663 |
/workspace/coverage/default/45.sysrst_ctrl_stress_all.1867283038 |
|
|
Mar 31 01:21:27 PM PDT 24 |
Mar 31 01:21:52 PM PDT 24 |
9425843846 ps |
T664 |
/workspace/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.3867818173 |
|
|
Mar 31 01:21:25 PM PDT 24 |
Mar 31 01:22:40 PM PDT 24 |
56023141391 ps |
T665 |
/workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.3440207316 |
|
|
Mar 31 01:19:34 PM PDT 24 |
Mar 31 01:19:42 PM PDT 24 |
2468765687 ps |
T666 |
/workspace/coverage/default/33.sysrst_ctrl_stress_all.1540211107 |
|
|
Mar 31 01:21:01 PM PDT 24 |
Mar 31 01:21:23 PM PDT 24 |
8348679027 ps |
T667 |
/workspace/coverage/default/13.sysrst_ctrl_alert_test.3423300056 |
|
|
Mar 31 01:20:03 PM PDT 24 |
Mar 31 01:20:08 PM PDT 24 |
2013809473 ps |
T668 |
/workspace/coverage/default/30.sysrst_ctrl_ultra_low_pwr.2371565579 |
|
|
Mar 31 01:20:49 PM PDT 24 |
Mar 31 01:22:17 PM PDT 24 |
2037415302797 ps |
T669 |
/workspace/coverage/default/13.sysrst_ctrl_pin_override_test.4113469885 |
|
|
Mar 31 01:20:00 PM PDT 24 |
Mar 31 01:20:05 PM PDT 24 |
2515479969 ps |
T670 |
/workspace/coverage/default/40.sysrst_ctrl_alert_test.2711804319 |
|
|
Mar 31 01:21:16 PM PDT 24 |
Mar 31 01:21:23 PM PDT 24 |
2011246595 ps |
T671 |
/workspace/coverage/default/27.sysrst_ctrl_smoke.2826235931 |
|
|
Mar 31 01:20:42 PM PDT 24 |
Mar 31 01:20:44 PM PDT 24 |
2124516592 ps |
T672 |
/workspace/coverage/default/2.sysrst_ctrl_ultra_low_pwr.3733910107 |
|
|
Mar 31 01:19:21 PM PDT 24 |
Mar 31 01:19:23 PM PDT 24 |
5631830511 ps |
T673 |
/workspace/coverage/default/24.sysrst_ctrl_smoke.3930201263 |
|
|
Mar 31 01:20:34 PM PDT 24 |
Mar 31 01:20:39 PM PDT 24 |
2112426661 ps |
T315 |
/workspace/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.1362650327 |
|
|
Mar 31 01:19:35 PM PDT 24 |
Mar 31 01:20:05 PM PDT 24 |
41790187984 ps |
T674 |
/workspace/coverage/default/35.sysrst_ctrl_alert_test.3157060642 |
|
|
Mar 31 01:21:09 PM PDT 24 |
Mar 31 01:21:11 PM PDT 24 |
2041161705 ps |
T351 |
/workspace/coverage/default/39.sysrst_ctrl_combo_detect.2487544481 |
|
|
Mar 31 01:21:16 PM PDT 24 |
Mar 31 01:25:27 PM PDT 24 |
186956311008 ps |
T675 |
/workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.991217687 |
|
|
Mar 31 01:19:03 PM PDT 24 |
Mar 31 01:19:05 PM PDT 24 |
2545149475 ps |
T676 |
/workspace/coverage/default/4.sysrst_ctrl_pin_access_test.2444911426 |
|
|
Mar 31 01:19:40 PM PDT 24 |
Mar 31 01:19:46 PM PDT 24 |
2231426305 ps |
T677 |
/workspace/coverage/default/2.sysrst_ctrl_flash_wr_prot_out.3078687297 |
|
|
Mar 31 01:19:21 PM PDT 24 |
Mar 31 01:19:28 PM PDT 24 |
2608036068 ps |
T678 |
/workspace/coverage/default/24.sysrst_ctrl_pin_override_test.635437194 |
|
|
Mar 31 01:20:38 PM PDT 24 |
Mar 31 01:20:41 PM PDT 24 |
2530683621 ps |
T679 |
/workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.3992389357 |
|
|
Mar 31 01:19:46 PM PDT 24 |
Mar 31 01:23:58 PM PDT 24 |
1328723475255 ps |
T680 |
/workspace/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.964744817 |
|
|
Mar 31 01:21:21 PM PDT 24 |
Mar 31 01:21:25 PM PDT 24 |
3342797199 ps |
T681 |
/workspace/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.1230866829 |
|
|
Mar 31 01:21:44 PM PDT 24 |
Mar 31 01:26:10 PM PDT 24 |
107759910582 ps |
T682 |
/workspace/coverage/default/30.sysrst_ctrl_pin_override_test.3502877556 |
|
|
Mar 31 01:20:51 PM PDT 24 |
Mar 31 01:21:00 PM PDT 24 |
2510350615 ps |
T683 |
/workspace/coverage/default/40.sysrst_ctrl_in_out_inverted.1416427441 |
|
|
Mar 31 01:21:15 PM PDT 24 |
Mar 31 01:21:22 PM PDT 24 |
2469359927 ps |
T684 |
/workspace/coverage/default/10.sysrst_ctrl_flash_wr_prot_out.355051429 |
|
|
Mar 31 01:19:54 PM PDT 24 |
Mar 31 01:19:56 PM PDT 24 |
2639094197 ps |
T685 |
/workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2919016281 |
|
|
Mar 31 01:19:31 PM PDT 24 |
Mar 31 01:19:35 PM PDT 24 |
2528408684 ps |
T686 |
/workspace/coverage/default/19.sysrst_ctrl_ultra_low_pwr.2887851096 |
|
|
Mar 31 01:20:27 PM PDT 24 |
Mar 31 01:20:29 PM PDT 24 |
3070367791 ps |
T687 |
/workspace/coverage/default/10.sysrst_ctrl_auto_blk_key_output.2013463043 |
|
|
Mar 31 01:19:52 PM PDT 24 |
Mar 31 01:20:02 PM PDT 24 |
3443364524 ps |
T688 |
/workspace/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.1080241287 |
|
|
Mar 31 01:19:23 PM PDT 24 |
Mar 31 01:20:30 PM PDT 24 |
103222216515 ps |
T689 |
/workspace/coverage/default/25.sysrst_ctrl_alert_test.2132227741 |
|
|
Mar 31 01:20:42 PM PDT 24 |
Mar 31 01:20:44 PM PDT 24 |
2028109058 ps |
T690 |
/workspace/coverage/default/46.sysrst_ctrl_stress_all.2676236545 |
|
|
Mar 31 01:21:36 PM PDT 24 |
Mar 31 01:21:47 PM PDT 24 |
13570223495 ps |
T359 |
/workspace/coverage/default/15.sysrst_ctrl_combo_detect_with_pre_cond.2287688553 |
|
|
Mar 31 01:20:12 PM PDT 24 |
Mar 31 01:25:36 PM PDT 24 |
112823261158 ps |
T691 |
/workspace/coverage/default/39.sysrst_ctrl_alert_test.878040631 |
|
|
Mar 31 01:21:19 PM PDT 24 |
Mar 31 01:21:25 PM PDT 24 |
2014204382 ps |
T692 |
/workspace/coverage/default/30.sysrst_ctrl_in_out_inverted.2017888487 |
|
|
Mar 31 01:20:53 PM PDT 24 |
Mar 31 01:20:56 PM PDT 24 |
2480627707 ps |
T693 |
/workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst.3596205176 |
|
|
Mar 31 01:19:18 PM PDT 24 |
Mar 31 01:19:24 PM PDT 24 |
2226509332 ps |
T694 |
/workspace/coverage/default/41.sysrst_ctrl_pin_override_test.167915991 |
|
|
Mar 31 01:21:22 PM PDT 24 |
Mar 31 01:21:29 PM PDT 24 |
2508507639 ps |
T185 |
/workspace/coverage/default/31.sysrst_ctrl_stress_all.2033359508 |
|
|
Mar 31 01:20:55 PM PDT 24 |
Mar 31 01:21:09 PM PDT 24 |
10710619136 ps |
T695 |
/workspace/coverage/default/2.sysrst_ctrl_in_out_inverted.372832087 |
|
|
Mar 31 01:19:16 PM PDT 24 |
Mar 31 01:19:21 PM PDT 24 |
2502931597 ps |
T156 |
/workspace/coverage/default/32.sysrst_ctrl_edge_detect.109943911 |
|
|
Mar 31 01:20:54 PM PDT 24 |
Mar 31 01:20:58 PM PDT 24 |
5200847381 ps |
T192 |
/workspace/coverage/default/34.sysrst_ctrl_stress_all_with_rand_reset.2053188177 |
|
|
Mar 31 01:21:01 PM PDT 24 |
Mar 31 01:23:41 PM PDT 24 |
325394798043 ps |
T696 |
/workspace/coverage/default/16.sysrst_ctrl_ultra_low_pwr.2144957949 |
|
|
Mar 31 01:20:13 PM PDT 24 |
Mar 31 01:20:19 PM PDT 24 |
2576285106 ps |
T697 |
/workspace/coverage/default/25.sysrst_ctrl_pin_override_test.1912714424 |
|
|
Mar 31 01:20:32 PM PDT 24 |
Mar 31 01:20:40 PM PDT 24 |
2513132806 ps |
T698 |
/workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.410459503 |
|
|
Mar 31 01:21:43 PM PDT 24 |
Mar 31 01:21:52 PM PDT 24 |
8370437368 ps |
T368 |
/workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.2504946396 |
|
|
Mar 31 01:21:43 PM PDT 24 |
Mar 31 01:24:52 PM PDT 24 |
75109710189 ps |
T699 |
/workspace/coverage/default/12.sysrst_ctrl_stress_all.408402660 |
|
|
Mar 31 01:20:00 PM PDT 24 |
Mar 31 01:20:08 PM PDT 24 |
11509382418 ps |
T700 |
/workspace/coverage/default/12.sysrst_ctrl_pin_access_test.3948046468 |
|
|
Mar 31 01:20:01 PM PDT 24 |
Mar 31 01:20:03 PM PDT 24 |
2272870208 ps |
T701 |
/workspace/coverage/default/8.sysrst_ctrl_stress_all.2711155854 |
|
|
Mar 31 01:19:46 PM PDT 24 |
Mar 31 01:19:53 PM PDT 24 |
11129647218 ps |
T702 |
/workspace/coverage/default/32.sysrst_ctrl_in_out_inverted.3379317756 |
|
|
Mar 31 01:20:53 PM PDT 24 |
Mar 31 01:20:57 PM PDT 24 |
2473003561 ps |
T703 |
/workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.328813400 |
|
|
Mar 31 01:19:47 PM PDT 24 |
Mar 31 01:19:49 PM PDT 24 |
2648740155 ps |
T704 |
/workspace/coverage/default/47.sysrst_ctrl_smoke.2777549592 |
|
|
Mar 31 01:21:33 PM PDT 24 |
Mar 31 01:21:39 PM PDT 24 |
2111066285 ps |
T705 |
/workspace/coverage/default/38.sysrst_ctrl_ec_pwr_on_rst.1372648199 |
|
|
Mar 31 01:21:17 PM PDT 24 |
Mar 31 01:21:27 PM PDT 24 |
3511253121 ps |
T706 |
/workspace/coverage/default/44.sysrst_ctrl_pin_override_test.1131406801 |
|
|
Mar 31 01:21:26 PM PDT 24 |
Mar 31 01:21:34 PM PDT 24 |
2509674345 ps |
T707 |
/workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.1864580676 |
|
|
Mar 31 01:21:43 PM PDT 24 |
Mar 31 01:23:35 PM PDT 24 |
41548218976 ps |
T249 |
/workspace/coverage/default/8.sysrst_ctrl_edge_detect.1438394425 |
|
|
Mar 31 01:19:45 PM PDT 24 |
Mar 31 01:19:48 PM PDT 24 |
5183497076 ps |
T708 |
/workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.4242225943 |
|
|
Mar 31 01:19:48 PM PDT 24 |
Mar 31 01:19:52 PM PDT 24 |
2470165294 ps |
T709 |
/workspace/coverage/default/22.sysrst_ctrl_flash_wr_prot_out.2829119338 |
|
|
Mar 31 01:20:29 PM PDT 24 |
Mar 31 01:20:32 PM PDT 24 |
2636111976 ps |
T366 |
/workspace/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.2809952768 |
|
|
Mar 31 01:19:35 PM PDT 24 |
Mar 31 01:21:01 PM PDT 24 |
114432116361 ps |
T710 |
/workspace/coverage/default/33.sysrst_ctrl_pin_access_test.1510265374 |
|
|
Mar 31 01:20:56 PM PDT 24 |
Mar 31 01:21:00 PM PDT 24 |
2221077332 ps |
T711 |
/workspace/coverage/default/10.sysrst_ctrl_ultra_low_pwr.18793646 |
|
|
Mar 31 01:19:53 PM PDT 24 |
Mar 31 01:19:54 PM PDT 24 |
4208322796 ps |
T712 |
/workspace/coverage/default/25.sysrst_ctrl_combo_detect_with_pre_cond.954517574 |
|
|
Mar 31 01:20:40 PM PDT 24 |
Mar 31 01:20:57 PM PDT 24 |
82497460144 ps |
T713 |
/workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.3585976682 |
|
|
Mar 31 01:21:37 PM PDT 24 |
Mar 31 01:21:42 PM PDT 24 |
2616812380 ps |
T361 |
/workspace/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.1994055573 |
|
|
Mar 31 01:19:40 PM PDT 24 |
Mar 31 01:22:00 PM PDT 24 |
57107105953 ps |
T714 |
/workspace/coverage/default/18.sysrst_ctrl_edge_detect.1785064039 |
|
|
Mar 31 01:20:16 PM PDT 24 |
Mar 31 01:20:22 PM PDT 24 |
2614493270 ps |
T715 |
/workspace/coverage/default/34.sysrst_ctrl_pin_override_test.950726568 |
|
|
Mar 31 01:21:05 PM PDT 24 |
Mar 31 01:21:12 PM PDT 24 |
2513674360 ps |
T387 |
/workspace/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.1841208892 |
|
|
Mar 31 01:19:09 PM PDT 24 |
Mar 31 01:20:54 PM PDT 24 |
76708920681 ps |
T305 |
/workspace/coverage/default/2.sysrst_ctrl_sec_cm.1697256896 |
|
|
Mar 31 01:19:21 PM PDT 24 |
Mar 31 01:19:50 PM PDT 24 |
43024322322 ps |
T716 |
/workspace/coverage/default/29.sysrst_ctrl_ec_pwr_on_rst.206004567 |
|
|
Mar 31 01:20:49 PM PDT 24 |
Mar 31 01:20:56 PM PDT 24 |
5143220790 ps |
T717 |
/workspace/coverage/default/41.sysrst_ctrl_alert_test.2839486055 |
|
|
Mar 31 01:21:21 PM PDT 24 |
Mar 31 01:21:24 PM PDT 24 |
2033543357 ps |
T718 |
/workspace/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.277434688 |
|
|
Mar 31 01:20:22 PM PDT 24 |
Mar 31 01:20:32 PM PDT 24 |
3164881914 ps |
T719 |
/workspace/coverage/default/14.sysrst_ctrl_edge_detect.235568968 |
|
|
Mar 31 01:20:09 PM PDT 24 |
Mar 31 01:20:12 PM PDT 24 |
4034739131 ps |
T720 |
/workspace/coverage/default/25.sysrst_ctrl_ultra_low_pwr.3538796889 |
|
|
Mar 31 01:20:41 PM PDT 24 |
Mar 31 01:20:51 PM PDT 24 |
7754124462 ps |
T721 |
/workspace/coverage/default/10.sysrst_ctrl_smoke.3239748507 |
|
|
Mar 31 01:19:54 PM PDT 24 |
Mar 31 01:19:58 PM PDT 24 |
2119523599 ps |
T306 |
/workspace/coverage/default/4.sysrst_ctrl_sec_cm.684803333 |
|
|
Mar 31 01:19:27 PM PDT 24 |
Mar 31 01:19:57 PM PDT 24 |
22025694014 ps |
T722 |
/workspace/coverage/default/40.sysrst_ctrl_auto_blk_key_output.438459059 |
|
|
Mar 31 01:21:19 PM PDT 24 |
Mar 31 01:21:21 PM PDT 24 |
3136457969 ps |
T723 |
/workspace/coverage/default/39.sysrst_ctrl_stress_all.3663910806 |
|
|
Mar 31 01:21:16 PM PDT 24 |
Mar 31 01:21:36 PM PDT 24 |
17070890151 ps |
T269 |
/workspace/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.1338058115 |
|
|
Mar 31 01:21:43 PM PDT 24 |
Mar 31 01:22:05 PM PDT 24 |
52496015400 ps |
T724 |
/workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.1399961590 |
|
|
Mar 31 01:21:42 PM PDT 24 |
Mar 31 01:21:44 PM PDT 24 |
2647550881 ps |
T725 |
/workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.2407044799 |
|
|
Mar 31 01:21:23 PM PDT 24 |
Mar 31 01:21:25 PM PDT 24 |
3359859863 ps |
T362 |
/workspace/coverage/default/36.sysrst_ctrl_combo_detect_with_pre_cond.3918494063 |
|
|
Mar 31 01:21:18 PM PDT 24 |
Mar 31 01:23:11 PM PDT 24 |
45786149923 ps |
T726 |
/workspace/coverage/default/10.sysrst_ctrl_in_out_inverted.4294468644 |
|
|
Mar 31 01:19:56 PM PDT 24 |
Mar 31 01:19:58 PM PDT 24 |
2522985895 ps |
T727 |
/workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.1808227595 |
|
|
Mar 31 01:21:24 PM PDT 24 |
Mar 31 01:21:34 PM PDT 24 |
3356829174 ps |
T728 |
/workspace/coverage/default/39.sysrst_ctrl_smoke.511002069 |
|
|
Mar 31 01:21:16 PM PDT 24 |
Mar 31 01:21:23 PM PDT 24 |
2111131036 ps |
T729 |
/workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.605344934 |
|
|
Mar 31 01:21:28 PM PDT 24 |
Mar 31 01:21:33 PM PDT 24 |
5552705075 ps |
T730 |
/workspace/coverage/default/37.sysrst_ctrl_alert_test.866152019 |
|
|
Mar 31 01:21:17 PM PDT 24 |
Mar 31 01:21:20 PM PDT 24 |
2037140794 ps |
T731 |
/workspace/coverage/default/26.sysrst_ctrl_combo_detect.2640776404 |
|
|
Mar 31 01:20:38 PM PDT 24 |
Mar 31 01:24:45 PM PDT 24 |
203287523249 ps |
T732 |
/workspace/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.3731076605 |
|
|
Mar 31 01:20:53 PM PDT 24 |
Mar 31 01:20:57 PM PDT 24 |
2626974694 ps |
T733 |
/workspace/coverage/default/31.sysrst_ctrl_smoke.368800097 |
|
|
Mar 31 01:20:54 PM PDT 24 |
Mar 31 01:20:56 PM PDT 24 |
2129722338 ps |
T734 |
/workspace/coverage/default/49.sysrst_ctrl_alert_test.745379735 |
|
|
Mar 31 01:21:42 PM PDT 24 |
Mar 31 01:21:44 PM PDT 24 |
2027838510 ps |
T735 |
/workspace/coverage/default/47.sysrst_ctrl_stress_all.3787872382 |
|
|
Mar 31 01:21:33 PM PDT 24 |
Mar 31 01:21:39 PM PDT 24 |
7453659229 ps |
T736 |
/workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.3311291934 |
|
|
Mar 31 01:21:27 PM PDT 24 |
Mar 31 01:21:35 PM PDT 24 |
2612719468 ps |
T737 |
/workspace/coverage/default/14.sysrst_ctrl_stress_all.1926428506 |
|
|
Mar 31 01:20:08 PM PDT 24 |
Mar 31 01:21:16 PM PDT 24 |
100192631883 ps |
T738 |
/workspace/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.3910957127 |
|
|
Mar 31 01:19:47 PM PDT 24 |
Mar 31 01:20:04 PM PDT 24 |
24099076429 ps |
T739 |
/workspace/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.1622394762 |
|
|
Mar 31 01:19:28 PM PDT 24 |
Mar 31 01:19:29 PM PDT 24 |
2648728628 ps |
T740 |
/workspace/coverage/default/13.sysrst_ctrl_ec_pwr_on_rst.3054762385 |
|
|
Mar 31 01:20:08 PM PDT 24 |
Mar 31 01:20:12 PM PDT 24 |
3881444641 ps |
T741 |
/workspace/coverage/default/44.sysrst_ctrl_combo_detect.3326902258 |
|
|
Mar 31 01:21:29 PM PDT 24 |
Mar 31 01:22:36 PM PDT 24 |
143022045136 ps |
T742 |
/workspace/coverage/default/19.sysrst_ctrl_pin_access_test.1977233901 |
|
|
Mar 31 01:20:22 PM PDT 24 |
Mar 31 01:20:28 PM PDT 24 |
2184741794 ps |
T743 |
/workspace/coverage/default/0.sysrst_ctrl_ultra_low_pwr.3097745547 |
|
|
Mar 31 01:19:09 PM PDT 24 |
Mar 31 01:21:27 PM PDT 24 |
1224632266914 ps |
T744 |
/workspace/coverage/default/33.sysrst_ctrl_combo_detect.4286095611 |
|
|
Mar 31 01:21:02 PM PDT 24 |
Mar 31 01:23:05 PM PDT 24 |
85780690849 ps |
T745 |
/workspace/coverage/default/19.sysrst_ctrl_ec_pwr_on_rst.1737657480 |
|
|
Mar 31 01:20:29 PM PDT 24 |
Mar 31 01:20:35 PM PDT 24 |
3941571031 ps |
T746 |
/workspace/coverage/default/3.sysrst_ctrl_pin_override_test.1187238596 |
|
|
Mar 31 01:19:25 PM PDT 24 |
Mar 31 01:19:27 PM PDT 24 |
2540697049 ps |
T747 |
/workspace/coverage/default/6.sysrst_ctrl_pin_access_test.2308497631 |
|
|
Mar 31 01:19:36 PM PDT 24 |
Mar 31 01:19:38 PM PDT 24 |
2273517085 ps |
T748 |
/workspace/coverage/default/24.sysrst_ctrl_ec_pwr_on_rst.4192770457 |
|
|
Mar 31 01:20:36 PM PDT 24 |
Mar 31 01:20:38 PM PDT 24 |
3040997983 ps |
T749 |
/workspace/coverage/default/33.sysrst_ctrl_pin_override_test.4041240271 |
|
|
Mar 31 01:21:00 PM PDT 24 |
Mar 31 01:21:04 PM PDT 24 |
2517314680 ps |
T750 |
/workspace/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.4170677069 |
|
|
Mar 31 01:20:16 PM PDT 24 |
Mar 31 01:25:07 PM PDT 24 |
105865992132 ps |
T751 |
/workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.2558645656 |
|
|
Mar 31 01:19:36 PM PDT 24 |
Mar 31 01:19:44 PM PDT 24 |
2607675390 ps |
T752 |
/workspace/coverage/default/39.sysrst_ctrl_ultra_low_pwr.278859298 |
|
|
Mar 31 01:21:18 PM PDT 24 |
Mar 31 01:21:25 PM PDT 24 |
5729134190 ps |
T753 |
/workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.1813658907 |
|
|
Mar 31 01:19:27 PM PDT 24 |
Mar 31 01:19:30 PM PDT 24 |
2264029036 ps |
T754 |
/workspace/coverage/default/10.sysrst_ctrl_ec_pwr_on_rst.3022435815 |
|
|
Mar 31 01:19:53 PM PDT 24 |
Mar 31 01:20:04 PM PDT 24 |
3333132167 ps |
T755 |
/workspace/coverage/default/35.sysrst_ctrl_pin_override_test.500869167 |
|
|
Mar 31 01:21:05 PM PDT 24 |
Mar 31 01:21:08 PM PDT 24 |
2533563491 ps |
T324 |
/workspace/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.68046915 |
|
|
Mar 31 01:20:21 PM PDT 24 |
Mar 31 01:22:25 PM PDT 24 |
55918176838 ps |
T756 |
/workspace/coverage/default/40.sysrst_ctrl_pin_access_test.1432635892 |
|
|
Mar 31 01:21:15 PM PDT 24 |
Mar 31 01:21:21 PM PDT 24 |
2169770479 ps |
T757 |
/workspace/coverage/default/20.sysrst_ctrl_stress_all_with_rand_reset.1912443056 |
|
|
Mar 31 01:20:29 PM PDT 24 |
Mar 31 01:20:58 PM PDT 24 |
20268337929 ps |
T758 |
/workspace/coverage/default/21.sysrst_ctrl_flash_wr_prot_out.3331914742 |
|
|
Mar 31 01:20:28 PM PDT 24 |
Mar 31 01:20:32 PM PDT 24 |
2615306212 ps |
T759 |
/workspace/coverage/default/27.sysrst_ctrl_pin_access_test.3387461433 |
|
|
Mar 31 01:20:42 PM PDT 24 |
Mar 31 01:20:49 PM PDT 24 |
2162779136 ps |
T760 |
/workspace/coverage/default/18.sysrst_ctrl_pin_override_test.696860716 |
|
|
Mar 31 01:20:15 PM PDT 24 |
Mar 31 01:20:17 PM PDT 24 |
2540690192 ps |
T761 |
/workspace/coverage/default/25.sysrst_ctrl_combo_detect.693610176 |
|
|
Mar 31 01:20:40 PM PDT 24 |
Mar 31 01:21:51 PM PDT 24 |
137697643972 ps |
T762 |
/workspace/coverage/default/25.sysrst_ctrl_smoke.3606328138 |
|
|
Mar 31 01:20:35 PM PDT 24 |
Mar 31 01:20:41 PM PDT 24 |
2107804450 ps |
T763 |
/workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.2304417612 |
|
|
Mar 31 01:21:41 PM PDT 24 |
Mar 31 01:21:57 PM PDT 24 |
23111305841 ps |
T764 |
/workspace/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.877711521 |
|
|
Mar 31 01:21:36 PM PDT 24 |
Mar 31 01:24:05 PM PDT 24 |
114640649691 ps |
T765 |
/workspace/coverage/default/38.sysrst_ctrl_pin_override_test.3369098294 |
|
|
Mar 31 01:21:13 PM PDT 24 |
Mar 31 01:21:16 PM PDT 24 |
2528492731 ps |
T393 |
/workspace/coverage/default/24.sysrst_ctrl_stress_all.534476272 |
|
|
Mar 31 01:20:36 PM PDT 24 |
Mar 31 01:53:10 PM PDT 24 |
1508850615733 ps |
T766 |
/workspace/coverage/default/5.sysrst_ctrl_smoke.1517440035 |
|
|
Mar 31 01:19:40 PM PDT 24 |
Mar 31 01:19:47 PM PDT 24 |
2110500298 ps |
T193 |
/workspace/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.316501691 |
|
|
Mar 31 01:21:43 PM PDT 24 |
Mar 31 01:22:58 PM PDT 24 |
26862714978 ps |
T767 |
/workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.3460447520 |
|
|
Mar 31 01:19:41 PM PDT 24 |
Mar 31 01:19:44 PM PDT 24 |
3353248115 ps |
T768 |
/workspace/coverage/default/28.sysrst_ctrl_auto_blk_key_output.2974036131 |
|
|
Mar 31 01:20:49 PM PDT 24 |
Mar 31 01:20:54 PM PDT 24 |
3311272241 ps |
T769 |
/workspace/coverage/default/0.sysrst_ctrl_stress_all_with_rand_reset.2636464030 |
|
|
Mar 31 01:19:07 PM PDT 24 |
Mar 31 01:19:45 PM PDT 24 |
60658882327 ps |
T770 |
/workspace/coverage/default/33.sysrst_ctrl_smoke.2665961473 |
|
|
Mar 31 01:20:53 PM PDT 24 |
Mar 31 01:20:57 PM PDT 24 |
2115658621 ps |
T771 |
/workspace/coverage/default/14.sysrst_ctrl_pin_access_test.866741927 |
|
|
Mar 31 01:20:08 PM PDT 24 |
Mar 31 01:20:11 PM PDT 24 |
2022316173 ps |
T772 |
/workspace/coverage/default/23.sysrst_ctrl_smoke.1324497800 |
|
|
Mar 31 01:20:32 PM PDT 24 |
Mar 31 01:20:38 PM PDT 24 |
2114002079 ps |
T355 |
/workspace/coverage/default/13.sysrst_ctrl_combo_detect_with_pre_cond.67666891 |
|
|
Mar 31 01:19:59 PM PDT 24 |
Mar 31 01:20:49 PM PDT 24 |
76760232430 ps |
T773 |
/workspace/coverage/default/17.sysrst_ctrl_combo_detect_with_pre_cond.194736799 |
|
|
Mar 31 01:20:17 PM PDT 24 |
Mar 31 01:22:50 PM PDT 24 |
59340546808 ps |
T385 |
/workspace/coverage/default/30.sysrst_ctrl_combo_detect.2507050694 |
|
|
Mar 31 01:20:53 PM PDT 24 |
Mar 31 01:22:35 PM PDT 24 |
148439302256 ps |
T177 |
/workspace/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.2656117281 |
|
|
Mar 31 01:19:14 PM PDT 24 |
Mar 31 01:20:23 PM PDT 24 |
103374260464 ps |
T774 |
/workspace/coverage/default/0.sysrst_ctrl_alert_test.2371552529 |
|
|
Mar 31 01:19:10 PM PDT 24 |
Mar 31 01:19:16 PM PDT 24 |
2012456225 ps |
T775 |
/workspace/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.97608795 |
|
|
Mar 31 01:20:34 PM PDT 24 |
Mar 31 01:23:19 PM PDT 24 |
63664057138 ps |
T178 |
/workspace/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.2866442399 |
|
|
Mar 31 01:20:31 PM PDT 24 |
Mar 31 01:22:20 PM PDT 24 |
43980904956 ps |
T776 |
/workspace/coverage/default/16.sysrst_ctrl_in_out_inverted.2047144062 |
|
|
Mar 31 01:20:08 PM PDT 24 |
Mar 31 01:20:14 PM PDT 24 |
2453391320 ps |
T777 |
/workspace/coverage/default/19.sysrst_ctrl_smoke.1052842200 |
|
|
Mar 31 01:20:22 PM PDT 24 |
Mar 31 01:20:24 PM PDT 24 |
2124257983 ps |
T778 |
/workspace/coverage/default/37.sysrst_ctrl_ultra_low_pwr.3630483876 |
|
|
Mar 31 01:21:10 PM PDT 24 |
Mar 31 01:26:17 PM PDT 24 |
1451730115950 ps |
T779 |
/workspace/coverage/default/34.sysrst_ctrl_alert_test.1116732894 |
|
|
Mar 31 01:21:02 PM PDT 24 |
Mar 31 01:21:05 PM PDT 24 |
2040936905 ps |
T780 |
/workspace/coverage/default/37.sysrst_ctrl_auto_blk_key_output.3124498410 |
|
|
Mar 31 01:21:12 PM PDT 24 |
Mar 31 01:21:23 PM PDT 24 |
3802922008 ps |
T781 |
/workspace/coverage/default/18.sysrst_ctrl_ultra_low_pwr.3363905712 |
|
|
Mar 31 01:20:15 PM PDT 24 |
Mar 31 01:20:23 PM PDT 24 |
3478678464 ps |
T782 |
/workspace/coverage/default/13.sysrst_ctrl_pin_access_test.2537522004 |
|
|
Mar 31 01:20:00 PM PDT 24 |
Mar 31 01:20:02 PM PDT 24 |
2268265338 ps |
T783 |
/workspace/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.3790710701 |
|
|
Mar 31 01:21:23 PM PDT 24 |
Mar 31 01:23:25 PM PDT 24 |
63009065042 ps |
T392 |
/workspace/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.4201891871 |
|
|
Mar 31 01:21:03 PM PDT 24 |
Mar 31 01:22:02 PM PDT 24 |
90981824233 ps |
T784 |
/workspace/coverage/default/4.sysrst_ctrl_edge_detect.3434670271 |
|
|
Mar 31 01:19:28 PM PDT 24 |
Mar 31 01:19:30 PM PDT 24 |
2822391877 ps |
T785 |
/workspace/coverage/default/4.sysrst_ctrl_smoke.3214717381 |
|
|
Mar 31 01:19:27 PM PDT 24 |
Mar 31 01:19:30 PM PDT 24 |
2131195179 ps |
T786 |
/workspace/coverage/default/36.sysrst_ctrl_auto_blk_key_output.342219645 |
|
|
Mar 31 01:21:08 PM PDT 24 |
Mar 31 01:21:13 PM PDT 24 |
3556295582 ps |
T239 |
/workspace/coverage/default/1.sysrst_ctrl_edge_detect.3588975222 |
|
|
Mar 31 01:19:18 PM PDT 24 |
Mar 31 01:19:21 PM PDT 24 |
3087663071 ps |
T787 |
/workspace/coverage/default/23.sysrst_ctrl_auto_blk_key_output.680096139 |
|
|
Mar 31 01:20:29 PM PDT 24 |
Mar 31 01:20:39 PM PDT 24 |
3622778942 ps |
T788 |
/workspace/coverage/default/9.sysrst_ctrl_pin_override_test.1561735957 |
|
|
Mar 31 01:19:48 PM PDT 24 |
Mar 31 01:19:51 PM PDT 24 |
2533417792 ps |
T789 |
/workspace/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.423740661 |
|
|
Mar 31 01:20:21 PM PDT 24 |
Mar 31 01:20:24 PM PDT 24 |
2634680586 ps |
T790 |
/workspace/coverage/default/22.sysrst_ctrl_pin_access_test.510431232 |
|
|
Mar 31 01:20:27 PM PDT 24 |
Mar 31 01:20:32 PM PDT 24 |
2258709398 ps |
T791 |
/workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.1322628163 |
|
|
Mar 31 01:21:42 PM PDT 24 |
Mar 31 01:21:45 PM PDT 24 |
2634683457 ps |
T792 |
/workspace/coverage/default/23.sysrst_ctrl_in_out_inverted.1197812399 |
|
|
Mar 31 01:20:27 PM PDT 24 |
Mar 31 01:20:31 PM PDT 24 |
2461356087 ps |
T28 |
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.1618714414 |
|
|
Mar 31 12:35:07 PM PDT 24 |
Mar 31 12:35:22 PM PDT 24 |
6019416789 ps |
T793 |
/workspace/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.118236700 |
|
|
Mar 31 12:35:41 PM PDT 24 |
Mar 31 12:35:48 PM PDT 24 |
2010571140 ps |