Unified Coverage Report :: Group :: tb.dut.u_sysrst_ctrl_cov_if::sysrst_ctrl_key_intr_status_cg

Group : tb.dut.u_sysrst_ctrl_cov_if::sysrst_ctrl_key_intr_status_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_cov_0/sysrst_ctrl_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_key_intr_status_cg	100.00	1	100	1	64	64

---

Group Instance : sysrst_ctrl_key_intr_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_key_intr_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	28	0	28	100.00

Variables for Group Instance sysrst_ctrl_key_intr_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_h2l	2	0	2	100.00	100	1	1	2
cp_ac_present_l2h	2	0	2	100.00	100	1	1	2
cp_ec_rst_l_h2l	2	0	2	100.00	100	1	1	2
cp_ec_rst_l_l2h	2	0	2	100.00	100	1	1	2
cp_flash_wp_l_h2l	2	0	2	100.00	100	1	1	2
cp_flash_wp_l_l2h	2	0	2	100.00	100	1	1	2
cp_key0_in_h2l	2	0	2	100.00	100	1	1	2
cp_key0_in_l2h	2	0	2	100.00	100	1	1	2
cp_key1_in_h2l	2	0	2	100.00	100	1	1	2
cp_key1_in_l2h	2	0	2	100.00	100	1	1	2
cp_key2_in_h2l	2	0	2	100.00	100	1	1	2
cp_key2_in_l2h	2	0	2	100.00	100	1	1	2
cp_pwrb_h2l	2	0	2	100.00	100	1	1	2
cp_pwrb_l2h	2	0	2	100.00	100	1	1	2

Summary for Variable cp_ac_present_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1081

1

T4

10

T1

28

T2

4

auto[1]

118

1

T1

3

T37

2

T35

1

---

Summary for Variable cp_ac_present_l2h

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_l2h

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1060

1

T4

10

T1

27

T2

4

auto[1]

139

1

T1

4

T37

3

T38

4

---

Summary for Variable cp_ec_rst_l_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ec_rst_l_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1067

1

T4

10

T1

30

T2

1

auto[1]

132

1

T1

1

T2

3

T37

1

---

Summary for Variable cp_ec_rst_l_l2h

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ec_rst_l_l2h

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1086

1

T4

10

T1

30

T2

4

auto[1]

113

1

T1

1

T37

2

T33

1

---

Summary for Variable cp_flash_wp_l_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_flash_wp_l_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1073

1

T4

10

T1

27

T2

4

auto[1]

126

1

T1

4

T38

2

T33

5

---

Summary for Variable cp_flash_wp_l_l2h

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_flash_wp_l_l2h

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1087

1

T4

10

T1

31

T2

4

auto[1]

112

1

T37

1

T35

2

T38

2

---

Summary for Variable cp_key0_in_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1095

1

T4

10

T1

30

T2

3

auto[1]

104

1

T1

1

T2

1

T35

2

---

Summary for Variable cp_key0_in_l2h

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_l2h

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1045

1

T4

10

T1

29

T2

4

auto[1]

154

1

T1

2

T40

2

T33

4

---

Summary for Variable cp_key1_in_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1095

1

T4

10

T1

29

T2

3

auto[1]

104

1

T1

2

T2

1

T37

2

---

Summary for Variable cp_key1_in_l2h

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_l2h

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1075

1

T4

10

T1

28

T2

4

auto[1]

124

1

T1

3

T35

2

T38

4

---

Summary for Variable cp_key2_in_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1112

1

T4

10

T1

29

T2

4

auto[1]

87

1

T1

2

T10

1

T37

3

---

Summary for Variable cp_key2_in_l2h

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_l2h

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1050

1

T4

10

T1

30

T2

2

auto[1]

149

1

T1

1

T2

2

T10

1

---

Summary for Variable cp_pwrb_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1110

1

T4

10

T1

27

T2

3

auto[1]

89

1

T1

4

T2

1

T10

1

---

Summary for Variable cp_pwrb_l2h

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_l2h

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1044

1

T4

10

T1

22

T2

1

auto[1]

155

1

T1

9

T2

3

T10

2