Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
92.68	92.68	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	92.68	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.68	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	6	56	90.32

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	6	25	80.65	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2000

1

T1

1

T3

11

T8

30

auto[1]

634

1

T1

2

T3

14

T8

22

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1961

1

T1

3

T3

16

T8

52

auto[1]

673

1

T3

9

T9

6

T11

1

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2004

1

T1

3

T3

7

T8

34

auto[1]

630

1

T3

18

T8

18

T9

8

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2052

1

T1

2

T3

15

T8

52

auto[1]

582

1

T1

1

T3

10

T9

10

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2397

1

T1

3

T3

25

T8

45

auto[1]

237

1

T8

7

T13

3

T26

3

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2402

1

T1

3

T3

25

T8

25

auto[1]

232

1

T8

27

T13

4

T26

2

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2427

1

T1

3

T3

25

T8

47

auto[1]

207

1

T8

5

T26

1

T30

4

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2453

1

T1

3

T3

25

T8

52

auto[1]

181

1

T26

1

T32

5

T42

3

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2472

1

T1

3

T3

25

T8

52

auto[1]

162

1

T13

4

T42

6

T121

1

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1966

1

T3

16

T8

47

T9

13

auto[1]

668

1

T1

3

T3

9

T8

5

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	6	25	80.65	6
Automatically Generated Cross Bins	31	6	25	80.65	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[1]]	*	[auto[0]]	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	964	1			T1	3		T3	20		T9	15
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	103	1			T8	7		T13	3		T106	1
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	24	1			T122	1		T97	4		T306	3
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	9	1			T121	1		T307	3		T308	5
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	61	1			T309	4		T310	1		T311	4
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	8	1			T312	2		T313	6		-	-
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	9	1			T42	2		T237	2		T200	2
auto[0]	auto[0]	auto[1]	auto[1]	auto[1]	12	1			T203	12		-	-		-	-
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	44	1			T42	7		T214	1		T309	6
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	30	1			T311	6		T314	3		T304	11
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	15	1			T315	4		T304	9		T316	1
auto[0]	auto[1]	auto[0]	auto[1]	auto[1]	4	1			T94	1		T317	3		-	-
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	24	1			T203	7		T306	2		T318	4
auto[0]	auto[1]	auto[1]	auto[0]	auto[1]	10	1			T26	1		T319	5		T320	4
auto[0]	auto[1]	auto[1]	auto[1]	auto[0]	1	1			T314	1		-	-		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	83	1			T8	22		T121	3		T108	5
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	8	1			T26	2		T97	1		T307	1
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	35	1			T13	4		T42	2		T240	14
auto[1]	auto[0]	auto[0]	auto[1]	auto[1]	3	1			T306	3		-	-		-	-
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	27	1			T32	5		T249	6		T170	1
auto[1]	auto[0]	auto[1]	auto[0]	auto[1]	2	1			T203	2		-	-		-	-
auto[1]	auto[0]	auto[1]	auto[1]	auto[0]	1	1			T316	1		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	35	1			T8	5		T30	4		T321	3
auto[1]	auto[1]	auto[0]	auto[1]	auto[0]	7	1			T322	2		T320	3		T323	2
auto[1]	auto[1]	auto[1]	auto[0]	auto[1]	4	1			T319	4		-	-		-	-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

113

1

T8

11

T45

9

T30

4

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

121

1

T8

5

T109

1

T214

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

76

1

T1

2

T3

2

T32

5

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

76

1

T13

3

T109

1

T210

10

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

60

1

T9

7

T11

6

T31

4

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

72

1

T1

1

T26

2

T189

6

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

19

1

T11

2

T324

3

T277

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

100

1

T8

7

T42

2

T108

5

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

51

1

T3

7

T8

11

T41

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

71

1

T121

3

T297

6

T111

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

38

1

T9

2

T216

3

T110

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

73

1

T3

1

T121

1

T240

7

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

24

1

T11

1

T13

4

T123

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

14

1

T3

1

T325

9

T326

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

19

1

T76

6

T259

1

T254

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

194

1

T31

11

T93

9

T242

13

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

65

1

T189

7

T237

2

T97

4

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

59

1

T45

6

T26

1

T203

7

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

23

1

T3

1

T11

1

T45

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

39

1

T31

5

T123

7

T259

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

26

1

T3

3

T93

2

T189

5

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

31

1

T123

3

T216

4

T299

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

5

1

T3

1

T303

2

T327

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

56

1

T95

6

T263

4

T243

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

16

1

T9

3

T42

2

T299

4

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

20

1

T106

1

T309

4

T298

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

8

1

T93

3

T310

1

T298

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

23

1

T3

4

T33

10

T242

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

10

1

T9

3

T31

1

T33

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

16

1

T216

4

T328

2

T313

8

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

5

1

T95

2

T329

1

T330

1

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded