Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1193

1

T4

12

T1

21

T53

12

auto[1]

1170

1

T4

28

T1

19

T53

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

560

1

T4

11

T1

13

T53

6

from_0to1

563

1

T4

11

T1

13

T53

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1155

1

T4

24

T1

20

T53

8

auto[1]

1208

1

T4

16

T1

20

T53

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1193

1

T4

19

T1

18

T53

12

auto[1]

1170

1

T4

21

T1

22

T53

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

74

1

T1

1

T132

1

T163

2

auto[0]

from_1to0

auto[0]

auto[1]

60

1

T53

1

T70

1

T136

1

auto[0]

from_1to0

auto[1]

auto[0]

85

1

T4

3

T1

2

T53

1

auto[0]

from_1to0

auto[1]

auto[1]

68

1

T4

1

T1

4

T53

2

auto[0]

from_0to1

auto[0]

auto[0]

81

1

T4

3

T1

1

T53

1

auto[0]

from_0to1

auto[0]

auto[1]

77

1

T1

2

T53

1

T116

1

auto[0]

from_0to1

auto[1]

auto[0]

75

1

T1

1

T70

1

T136

2

auto[0]

from_0to1

auto[1]

auto[1]

59

1

T4

1

T1

2

T53

1

auto[1]

from_1to0

auto[0]

auto[0]

63

1

T4

4

T1

1

T53

1

auto[1]

from_1to0

auto[0]

auto[1]

65

1

T4

1

T1

1

T69

1

auto[1]

from_1to0

auto[1]

auto[0]

71

1

T4

2

T1

2

T53

1

auto[1]

from_1to0

auto[1]

auto[1]

74

1

T1

2

T70

1

T116

2

auto[1]

from_0to1

auto[0]

auto[0]

65

1

T4

1

T1

4

T70

1

auto[1]

from_0to1

auto[0]

auto[1]

62

1

T4

3

T1

1

T69

1

auto[1]

from_0to1

auto[1]

auto[0]

67

1

T1

1

T53

2

T70

1

auto[1]

from_0to1

auto[1]

auto[1]

77

1

T4

3

T1

1

T53

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1204

1

T4

20

T1

22

T53

13

auto[1]

1159

1

T4

20

T1

18

T53

7

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

562

1

T4

8

T1

10

T53

4

from_0to1

550

1

T4

8

T1

11

T53

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1220

1

T4

17

T1

20

T53

8

auto[1]

1143

1

T4

23

T1

20

T53

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1182

1

T4

24

T1

16

T53

6

auto[1]

1181

1

T4

16

T1

24

T53

14

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

79

1

T4

2

T1

1

T70

1

auto[0]

from_1to0

auto[0]

auto[1]

78

1

T1

3

T53

3

T132

1

auto[0]

from_1to0

auto[1]

auto[0]

69

1

T1

2

T69

1

T116

1

auto[0]

from_1to0

auto[1]

auto[1]

55

1

T4

1

T1

1

T69

1

auto[0]

from_0to1

auto[0]

auto[0]

65

1

T4

1

T1

2

T132

1

auto[0]

from_0to1

auto[0]

auto[1]

71

1

T70

2

T136

1

T116

1

auto[0]

from_0to1

auto[1]

auto[0]

60

1

T4

1

T1

2

T53

1

auto[0]

from_0to1

auto[1]

auto[1]

71

1

T4

1

T1

3

T53

1

auto[1]

from_1to0

auto[0]

auto[0]

75

1

T1

1

T116

1

T132

2

auto[1]

from_1to0

auto[0]

auto[1]

77

1

T69

1

T70

1

T116

1

auto[1]

from_1to0

auto[1]

auto[0]

58

1

T4

2

T1

1

T136

2

auto[1]

from_1to0

auto[1]

auto[1]

71

1

T4

3

T1

1

T53

1

auto[1]

from_0to1

auto[0]

auto[0]

81

1

T4

3

T1

1

T69

2

auto[1]

from_0to1

auto[0]

auto[1]

65

1

T1

2

T53

1

T69

1

auto[1]

from_0to1

auto[1]

auto[0]

75

1

T4

1

T1

1

T53

1

auto[1]

from_0to1

auto[1]

auto[1]

62

1

T4

1

T69

2

T116

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1199

1

T4

21

T1

18

T53

8

auto[1]

1164

1

T4

19

T1

22

T53

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

582

1

T4

9

T1

11

T53

6

from_0to1

584

1

T4

9

T1

10

T53

7

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1173

1

T4

21

T1

23

T53

7

auto[1]

1190

1

T4

19

T1

17

T53

13

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1173

1

T4

13

T1

14

T53

10

auto[1]

1190

1

T4

27

T1

26

T53

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

66

1

T4

1

T1

2

T116

1

auto[0]

from_1to0

auto[0]

auto[1]

94

1

T4

1

T1

3

T136

1

auto[0]

from_1to0

auto[1]

auto[0]

69

1

T4

1

T53

1

T136

2

auto[0]

from_1to0

auto[1]

auto[1]

63

1

T4

1

T1

2

T53

2

auto[0]

from_0to1

auto[0]

auto[0]

87

1

T1

1

T70

2

T116

2

auto[0]

from_0to1

auto[0]

auto[1]

68

1

T4

2

T1

1

T53

1

auto[0]

from_0to1

auto[1]

auto[0]

68

1

T53

2

T69

1

T70

1

auto[0]

from_0to1

auto[1]

auto[1]

70

1

T4

1

T1

3

T69

1

auto[1]

from_1to0

auto[0]

auto[0]

55

1

T1

1

T69

1

T70

1

auto[1]

from_1to0

auto[0]

auto[1]

74

1

T4

3

T1

2

T53

1

auto[1]

from_1to0

auto[1]

auto[0]

84

1

T4

1

T53

1

T116

1

auto[1]

from_1to0

auto[1]

auto[1]

77

1

T4

1

T1

1

T53

1

auto[1]

from_0to1

auto[0]

auto[0]

76

1

T4

2

T1

2

T69

1

auto[1]

from_0to1

auto[0]

auto[1]

68

1

T4

1

T53

1

T136

1

auto[1]

from_0to1

auto[1]

auto[0]

71

1

T53

2

T69

2

T132

1

auto[1]

from_0to1

auto[1]

auto[1]

76

1

T4

3

T1

3

T53

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1207

1

T4

15

T1

18

T53

7

auto[1]

1156

1

T4

25

T1

22

T53

13

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

581

1

T4

9

T1

10

T53

4

from_0to1

573

1

T4

9

T1

11

T53

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1159

1

T4

15

T1

22

T53

10

auto[1]

1204

1

T4

25

T1

18

T53

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1211

1

T4

21

T1

22

T53

14

auto[1]

1152

1

T4

19

T1

18

T53

6

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

88

1

T4

2

T70

2

T116

1

auto[0]

from_1to0

auto[0]

auto[1]

65

1

T1

1

T53

1

T69

1

auto[0]

from_1to0

auto[1]

auto[0]

82

1

T4

2

T1

1

T53

2

auto[0]

from_1to0

auto[1]

auto[1]

69

1

T69

1

T136

1

T131

1

auto[0]

from_0to1

auto[0]

auto[0]

73

1

T70

1

T163

1

T351

1

auto[0]

from_0to1

auto[0]

auto[1]

71

1

T1

1

T70

2

T116

2

auto[0]

from_0to1

auto[1]

auto[0]

88

1

T4

2

T1

1

T70

1

auto[0]

from_0to1

auto[1]

auto[1]

58

1

T4

2

T1

1

T53

1

auto[1]

from_1to0

auto[0]

auto[0]

50

1

T1

2

T53

1

T70

1

auto[1]

from_1to0

auto[0]

auto[1]

68

1

T1

1

T132

1

T143

1

auto[1]

from_1to0

auto[1]

auto[0]

73

1

T4

3

T1

2

T69

1

auto[1]

from_1to0

auto[1]

auto[1]

86

1

T4

2

T1

3

T136

1

auto[1]

from_0to1

auto[0]

auto[0]

66

1

T4

2

T1

4

T53

1

auto[1]

from_0to1

auto[0]

auto[1]

73

1

T4

1

T1

3

T69

1

auto[1]

from_0to1

auto[1]

auto[0]

68

1

T1

1

T53

1

T69

2

auto[1]

from_0to1

auto[1]

auto[1]

76

1

T4

2

T131

1

T163

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1172

1

T4

19

T1

19

T53

8

auto[1]

1191

1

T4

21

T1

21

T53

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

561

1

T4

9

T1

6

T53

5

from_0to1

571

1

T4

10

T1

7

T53

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1172

1

T4

13

T1

22

T53

12

auto[1]

1191

1

T4

27

T1

18

T53

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1200

1

T4

22

T1

25

T53

10

auto[1]

1163

1

T4

18

T1

15

T53

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

78

1

T4

1

T1

3

T69

1

auto[0]

from_1to0

auto[0]

auto[1]

74

1

T69

1

T116

1

T132

1

auto[0]

from_1to0

auto[1]

auto[0]

69

1

T53

2

T69

1

T70

1

auto[0]

from_1to0

auto[1]

auto[1]

50

1

T4

3

T53

1

T70

1

auto[0]

from_0to1

auto[0]

auto[0]

84

1

T4

2

T1

1

T53

1

auto[0]

from_0to1

auto[0]

auto[1]

66

1

T53

2

T70

1

T132

1

auto[0]

from_0to1

auto[1]

auto[0]

67

1

T4

2

T1

1

T70

1

auto[0]

from_0to1

auto[1]

auto[1]

79

1

T4

1

T1

1

T69

2

auto[1]

from_1to0

auto[0]

auto[0]

85

1

T4

2

T1

1

T53

2

auto[1]

from_1to0

auto[0]

auto[1]

61

1

T136

1

T132

1

T351

2

auto[1]

from_1to0

auto[1]

auto[0]

73

1

T4

2

T1

2

T69

3

auto[1]

from_1to0

auto[1]

auto[1]

71

1

T4

1

T70

2

T136

1

auto[1]

from_0to1

auto[0]

auto[0]

67

1

T4

2

T1

1

T69

2

auto[1]

from_0to1

auto[0]

auto[1]

66

1

T4

1

T1

1

T136

1

auto[1]

from_0to1

auto[1]

auto[0]

59

1

T4

1

T53

2

T70

1

auto[1]

from_0to1

auto[1]

auto[1]

83

1

T4

1

T1

2

T69

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1203

1

T4

17

T1

22

T53

11

auto[1]

1160

1

T4

23

T1

18

T53

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

544

1

T4

8

T1

10

T53

4

from_0to1

538

1

T4

9

T1

11

T53

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1167

1

T4

22

T1

18

T53

12

auto[1]

1196

1

T4

18

T1

22

T53

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1194

1

T4

27

T1

22

T53

6

auto[1]

1169

1

T4

13

T1

18

T53

14

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

68

1

T1

2

T53

1

T69

2

auto[0]

from_1to0

auto[0]

auto[1]

75

1

T1

2

T53

1

T70

1

auto[0]

from_1to0

auto[1]

auto[0]

68

1

T4

1

T1

1

T69

2

auto[0]

from_1to0

auto[1]

auto[1]

64

1

T4

1

T53

1

T69

1

auto[0]

from_0to1

auto[0]

auto[0]

73

1

T4

1

T1

2

T136

1

auto[0]

from_0to1

auto[0]

auto[1]

67

1

T4

1

T1

2

T70

1

auto[0]

from_0to1

auto[1]

auto[0]

68

1

T4

1

T1

2

T53

1

auto[0]

from_0to1

auto[1]

auto[1]

66

1

T4

1

T1

3

T53

1

auto[1]

from_1to0

auto[0]

auto[0]

71

1

T4

3

T116

2

T132

1

auto[1]

from_1to0

auto[0]

auto[1]

47

1

T4

1

T1

1

T53

1

auto[1]

from_1to0

auto[1]

auto[0]

77

1

T4

2

T1

4

T136

1

auto[1]

from_1to0

auto[1]

auto[1]

74

1

T69

2

T70

2

T116

1

auto[1]

from_0to1

auto[0]

auto[0]

74

1

T4

4

T53

1

T69

1

auto[1]

from_0to1

auto[0]

auto[1]

68

1

T1

1

T53

2

T69

2

auto[1]

from_0to1

auto[1]

auto[0]

55

1

T1

1

T70

1

T116

1

auto[1]

from_0to1

auto[1]

auto[1]

67

1

T4

1

T69

2

T131

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1216

1

T4

22

T1

24

T53

9

auto[1]

1147

1

T4

18

T1

16

T53

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

591

1

T4

11

T1

10

T53

6

from_0to1

585

1

T4

12

T1

9

T53

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1225

1

T4

24

T1

19

T53

11

auto[1]

1138

1

T4

16

T1

21

T53

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1169

1

T4

23

T1

20

T53

12

auto[1]

1194

1

T4

17

T1

20

T53

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

74

1

T4

1

T1

2

T53

1

auto[0]

from_1to0

auto[0]

auto[1]

70

1

T4

2

T1

1

T53

1

auto[0]

from_1to0

auto[1]

auto[0]

72

1

T4

1

T1

4

T69

3

auto[0]

from_1to0

auto[1]

auto[1]

80

1

T4

1

T1

1

T136

2

auto[0]

from_0to1

auto[0]

auto[0]

81

1

T4

3

T53

1

T136

2

auto[0]

from_0to1

auto[0]

auto[1]

86

1

T4

1

T69

2

T70

1

auto[0]

from_0to1

auto[1]

auto[0]

62

1

T4

2

T1

1

T53

1

auto[0]

from_0to1

auto[1]

auto[1]

80

1

T4

1

T1

4

T132

1

auto[1]

from_1to0

auto[0]

auto[0]

67

1

T4

3

T1

1

T53

1

auto[1]

from_1to0

auto[0]

auto[1]

79

1

T53

1

T69

1

T70

1

auto[1]

from_1to0

auto[1]

auto[0]

73

1

T4

1

T53

1

T116

1

auto[1]

from_1to0

auto[1]

auto[1]

76

1

T4

2

T1

1

T53

1

auto[1]

from_0to1

auto[0]

auto[0]

82

1

T4

3

T1

1

T53

1

auto[1]

from_0to1

auto[0]

auto[1]

72

1

T1

2

T116

2

T351

2

auto[1]

from_0to1

auto[1]

auto[0]

54

1

T4

1

T53

1

T69

1

auto[1]

from_0to1

auto[1]

auto[1]

68

1

T4

1

T1

1

T53

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1169

1

T4

19

T1

19

T53

9

auto[1]

1194

1

T4

21

T1

21

T53

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

572

1

T4

8

T1

10

T53

2

from_0to1

563

1

T4

9

T1

10

T53

2

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1208

1

T4

20

T1

20

T53

11

auto[1]

1155

1

T4

20

T1

20

T53

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1165

1

T4

24

T1

17

T53

15

auto[1]

1198

1

T4

16

T1

23

T53

5

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

80

1

T4

2

T1

1

T53

1

auto[0]

from_1to0

auto[0]

auto[1]

80

1

T4

3

T1

1

T70

1

auto[0]

from_1to0

auto[1]

auto[0]

64

1

T69

2

T116

2

T132

1

auto[0]

from_1to0

auto[1]

auto[1]

75

1

T1

4

T70

1

T136

1

auto[0]

from_0to1

auto[0]

auto[0]

67

1

T1

1

T69

2

T116

1

auto[0]

from_0to1

auto[0]

auto[1]

74

1

T1

1

T116

1

T131

1

auto[0]

from_0to1

auto[1]

auto[0]

63

1

T1

1

T69

1

T131

1

auto[0]

from_0to1

auto[1]

auto[1]

58

1

T4

2

T1

1

T136

1

auto[1]

from_1to0

auto[0]

auto[0]

71

1

T4

1

T1

1

T70

1

auto[1]

from_1to0

auto[0]

auto[1]

65

1

T1

1

T136

1

T132

1

auto[1]

from_1to0

auto[1]

auto[0]

68

1

T4

2

T1

1

T53

1

auto[1]

from_1to0

auto[1]

auto[1]

69

1

T1

1

T69

2

T116

1

auto[1]

from_0to1

auto[0]

auto[0]

66

1

T4

1

T70

1

T136

1

auto[1]

from_0to1

auto[0]

auto[1]

70

1

T1

2

T53

1

T131

1

auto[1]

from_0to1

auto[1]

auto[0]

74

1

T4

5

T1

2

T53

1

auto[1]

from_0to1

auto[1]

auto[1]

91

1

T4

1

T1

2

T69

2