Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	153148	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

117800

1

T4

276

T5

7

T6

16

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	139735	1			T4	362		T5	2		T6	22
values[0x0]	64872	1			T4	123		T5	9		T6	11
values[0x1]	66341	1			T4	123		T5	9		T6	11

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	124261	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

146687

1

T4

330

T5

10

T6

22

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	822	1			T19	2		T8	4		T17	1
valid_sources[0x01]	1052	1			T1	5		T3	1		T54	1
valid_sources[0x02]	1400	1			T1	11		T3	3		T12	1
valid_sources[0x03]	1627	1			T6	1		T19	1		T1	3
valid_sources[0x04]	1585	1			T1	4		T3	9		T53	1
valid_sources[0x05]	832	1			T6	1		T1	3		T3	11
valid_sources[0x06]	934	1			T1	4		T3	10		T7	34
valid_sources[0x07]	933	1			T19	2		T1	2		T3	2
valid_sources[0x08]	858	1			T19	1		T1	6		T3	2
valid_sources[0x09]	1320	1			T1	5		T3	5		T13	4
valid_sources[0x0a]	972	1			T1	6		T8	2		T13	4
valid_sources[0x0b]	924	1			T1	5		T15	1		T3	2
valid_sources[0x0c]	882	1			T19	2		T1	1		T3	15
valid_sources[0x0d]	1013	1			T1	1		T3	16		T8	2
valid_sources[0x0e]	897	1			T1	10		T3	6		T8	6
valid_sources[0x0f]	941	1			T1	4		T3	2		T8	9
valid_sources[0x10]	1050	1			T1	5		T16	1		T3	4
valid_sources[0x11]	861	1			T1	1		T3	13		T8	7
valid_sources[0x12]	949	1			T1	5		T3	5		T8	34
valid_sources[0x13]	1545	1			T6	1		T19	1		T1	2
valid_sources[0x14]	1118	1			T1	2		T14	1		T3	2
valid_sources[0x15]	880	1			T4	6		T1	3		T16	1
valid_sources[0x16]	920	1			T6	2		T1	1		T14	1
valid_sources[0x17]	985	1			T1	20		T15	1		T3	9
valid_sources[0x18]	943	1			T1	11		T3	5		T8	8
valid_sources[0x19]	894	1			T1	8		T3	4		T8	1
valid_sources[0x1a]	1039	1			T1	2		T3	2		T8	1
valid_sources[0x1b]	978	1			T1	7		T3	20		T53	1
valid_sources[0x1c]	819	1			T1	3		T3	7		T8	2
valid_sources[0x1d]	834	1			T1	1		T3	16		T8	3
valid_sources[0x1e]	1058	1			T1	4		T3	2		T8	3
valid_sources[0x1f]	1800	1			T1	2		T3	27		T52	1
valid_sources[0x20]	1162	1			T1	11		T16	1		T3	2
valid_sources[0x21]	1547	1			T19	5		T1	4		T3	3
valid_sources[0x22]	977	1			T1	1		T3	9		T54	1
valid_sources[0x23]	1048	1			T1	3		T3	3		T8	10
valid_sources[0x24]	897	1			T1	2		T3	19		T17	1
valid_sources[0x25]	842	1			T1	2		T3	3		T8	6
valid_sources[0x26]	887	1			T1	11		T16	1		T17	1
valid_sources[0x27]	870	1			T1	4		T3	9		T17	1
valid_sources[0x28]	962	1			T1	3		T3	14		T8	4
valid_sources[0x29]	886	1			T1	6		T3	1		T53	1
valid_sources[0x2a]	1075	1			T6	1		T1	2		T14	1
valid_sources[0x2b]	884	1			T1	8		T2	1		T3	2
valid_sources[0x2c]	963	1			T1	9		T3	4		T8	20
valid_sources[0x2d]	912	1			T1	1		T3	6		T8	7
valid_sources[0x2e]	944	1			T1	3		T3	6		T13	4
valid_sources[0x2f]	919	1			T20	1		T1	12		T3	1
valid_sources[0x30]	1606	1			T3	5		T13	2		T26	4
valid_sources[0x31]	889	1			T3	7		T8	1		T17	3
valid_sources[0x32]	958	1			T1	5		T3	8		T13	1
valid_sources[0x33]	975	1			T3	10		T17	1		T13	4
valid_sources[0x34]	1360	1			T1	2		T15	1		T3	16
valid_sources[0x35]	1010	1			T19	1		T1	3		T14	1
valid_sources[0x36]	991	1			T1	1		T3	4		T8	17
valid_sources[0x37]	883	1			T1	1		T3	9		T8	5
valid_sources[0x38]	913	1			T15	1		T3	1		T8	4
valid_sources[0x39]	861	1			T1	5		T3	1		T8	8
valid_sources[0x3a]	936	1			T1	5		T3	4		T13	6
valid_sources[0x3b]	911	1			T1	4		T3	1		T8	3
valid_sources[0x3c]	869	1			T1	12		T3	1		T8	6
valid_sources[0x3d]	865	1			T6	3		T1	1		T3	9
valid_sources[0x3e]	1139	1			T1	4		T3	4		T8	2
valid_sources[0x3f]	3007	1			T1	6		T3	5		T8	9
valid_sources[0x40]	980	1			T6	8		T1	1		T3	12
valid_sources[0x41]	929	1			T19	2		T1	3		T3	2
valid_sources[0x42]	968	1			T19	2		T1	3		T3	9
valid_sources[0x43]	1127	1			T6	3		T1	3		T3	6
valid_sources[0x44]	983	1			T1	4		T3	9		T13	5
valid_sources[0x45]	1044	1			T4	191		T1	6		T3	1
valid_sources[0x46]	853	1			T6	1		T3	6		T13	7
valid_sources[0x47]	883	1			T1	4		T3	5		T8	7
valid_sources[0x48]	955	1			T1	15		T3	1		T53	1
valid_sources[0x49]	987	1			T3	1		T12	1		T13	1
valid_sources[0x4a]	889	1			T1	2		T15	1		T3	5
valid_sources[0x4b]	873	1			T1	6		T3	12		T17	1
valid_sources[0x4c]	905	1			T1	5		T3	3		T8	9
valid_sources[0x4d]	928	1			T4	20		T1	12		T3	4
valid_sources[0x4e]	908	1			T19	3		T3	3		T57	6
valid_sources[0x4f]	863	1			T1	3		T3	13		T8	4
valid_sources[0x50]	944	1			T1	3		T8	5		T53	1
valid_sources[0x51]	795	1			T19	1		T1	2		T3	2
valid_sources[0x52]	921	1			T1	1		T3	8		T8	15
valid_sources[0x53]	880	1			T1	3		T17	1		T13	8
valid_sources[0x54]	1020	1			T20	5		T1	3		T3	8
valid_sources[0x55]	856	1			T1	6		T3	13		T12	1
valid_sources[0x56]	988	1			T1	2		T3	4		T13	3
valid_sources[0x57]	1532	1			T1	6		T3	15		T8	4
valid_sources[0x58]	979	1			T3	2		T13	5		T26	5
valid_sources[0x59]	1174	1			T6	1		T19	3		T1	7
valid_sources[0x5a]	1411	1			T6	1		T1	8		T3	4
valid_sources[0x5b]	2039	1			T1	1		T3	2		T8	12
valid_sources[0x5c]	1018	1			T4	20		T6	1		T1	4
valid_sources[0x5d]	1565	1			T19	1		T1	3		T2	3
valid_sources[0x5e]	896	1			T19	1		T1	8		T16	1
valid_sources[0x5f]	933	1			T6	1		T19	1		T1	2
valid_sources[0x60]	867	1			T6	1		T1	3		T3	5
valid_sources[0x61]	849	1			T1	12		T3	8		T13	4
valid_sources[0x62]	982	1			T6	1		T1	1		T3	15
valid_sources[0x63]	832	1			T1	1		T3	1		T53	1
valid_sources[0x64]	1105	1			T5	20		T1	3		T3	14
valid_sources[0x65]	2024	1			T19	1		T1	7		T3	6
valid_sources[0x66]	992	1			T4	8		T19	1		T1	1
valid_sources[0x67]	993	1			T1	15		T2	5		T3	10
valid_sources[0x68]	1547	1			T6	1		T1	3		T8	1
valid_sources[0x69]	1243	1			T4	20		T1	5		T3	8
valid_sources[0x6a]	995	1			T19	1		T1	2		T3	4
valid_sources[0x6b]	1045	1			T19	1		T3	13		T8	20
valid_sources[0x6c]	921	1			T1	9		T3	12		T8	21
valid_sources[0x6d]	1005	1			T3	5		T8	15		T53	1
valid_sources[0x6e]	918	1			T3	1		T136	2		T26	1
valid_sources[0x6f]	1722	1			T1	3		T3	10		T13	1
valid_sources[0x70]	1340	1			T3	7		T8	21		T52	2
valid_sources[0x71]	1042	1			T1	5		T3	3		T25	45
valid_sources[0x72]	1726	1			T1	10		T3	7		T12	1
valid_sources[0x73]	1009	1			T19	1		T1	6		T3	4
valid_sources[0x74]	2009	1			T1	4		T3	9		T53	1
valid_sources[0x75]	951	1			T1	8		T8	25		T17	1
valid_sources[0x76]	891	1			T1	5		T3	8		T18	11
valid_sources[0x77]	1023	1			T3	1		T8	7		T53	1
valid_sources[0x78]	967	1			T19	1		T1	9		T3	2
valid_sources[0x79]	913	1			T3	3		T53	1		T13	8
valid_sources[0x7a]	866	1			T1	11		T3	4		T8	13
valid_sources[0x7b]	947	1			T1	2		T16	1		T3	5
valid_sources[0x7c]	1751	1			T1	6		T3	2		T54	1
valid_sources[0x7d]	849	1			T1	1		T2	1		T3	2
valid_sources[0x7e]	929	1			T1	2		T3	3		T8	10
valid_sources[0x7f]	898	1			T1	3		T3	1		T13	1
valid_sources[0x80]	1117	1			T1	5		T3	5		T53	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

64141

1

T4

183

T5

1

T6

8

values[0x0]

all_enables

biggest_size

31435

1

T4

57

T5

5

T6

6

values[0x1]

all_enables

biggest_size

22224

1

T4

36

T5

1

T6

2