Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.76	100.00	90.48		100.00	100.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.76	100.00	90.48		100.00	100.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T6,T19
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T19
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T3,T18

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T4,T1,T3

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T3,T18

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T3
1	0	Covered	T4,T6,T19
1	1	Covered	T4,T1,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T18,T43
0	1	Covered	T3,T114,T102
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T18,T43
0	1	Covered	T1,T18,T43
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T18,T43
1	-	Covered	T1,T18,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T1,T3
DetectSt	168	Covered	T1,T3,T18
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T18,T43

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T3,T18
DebounceSt->IdleSt	163	Covered	T4,T47,T75
DetectSt->IdleSt	186	Covered	T3,T114,T102
DetectSt->StableSt	191	Covered	T1,T18,T43
IdleSt->DebounceSt	148	Covered	T4,T1,T3
StableSt->IdleSt	206	Covered	T1,T18,T43

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T3,T18
0	1	Covered	T4,T1,T3
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T18
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T1,T3
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T55
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T3,T18
DebounceSt	-	0	1	0	-	-	-	Covered	T47,T105,T126
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T1,T3
DetectSt	-	-	-	-	1	-	-	Covered	T3,T114,T102
DetectSt	-	-	-	-	0	1	-	Covered	T1,T18,T43
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T18,T43
StableSt	-	-	-	-	-	-	0	Covered	T1,T18,T43
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9721734	332	0	0
CntIncr_A	9721734	238381	0	0
CntNoWrap_A	9721734	9034563	0	0
DetectStDropOut_A	9721734	3	0	0
DetectedOut_A	9721734	1000	0	0
DetectedPulseOut_A	9721734	151	0	0
DisabledIdleSt_A	9721734	8788625	0	0
DisabledNoDetection_A	9721734	8791064	0	0
EnterDebounceSt_A	9721734	183	0	0
EnterDetectSt_A	9721734	154	0	0
EnterStableSt_A	9721734	151	0	0
PulseIsPulse_A	9721734	151	0	0
StayInStableSt	9721734	849	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9721734	7273	0	0
gen_low_level_sva.LowLevelEvent_A	9721734	9037396	0	0
gen_not_sticky_sva.StableStDropOut_A	9721734	151	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	332	0	0
T1	17410	4	0	0
T2	525	0	0	0
T3	41713	2	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	2	0	0
T40	0	2	0	0
T43	0	4	0	0
T44	0	2	0	0
T47	0	3	0	0
T50	0	2	0	0
T51	0	2	0	0
T75	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	238381	0	0
T1	17410	113	0	0
T2	525	0	0	0
T3	0	36	0	0
T4	9352	5627	0	0
T5	407	0	0	0
T6	500	0	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T18	0	23	0	0
T19	521	0	0	0
T20	642	0	0	0
T40	0	27	0	0
T43	0	141	0	0
T44	0	10	0	0
T47	0	164	0	0
T50	0	73	0	0
T51	0	97	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	9034563	0	0
T1	17410	9045	0	0
T2	525	124	0	0
T4	9352	6128	0	0
T5	407	6	0	0
T6	500	99	0	0
T14	402	1	0	0
T15	405	4	0	0
T16	408	7	0	0
T19	521	120	0	0
T20	642	241	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	3	0	0
T3	41713	1	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T9	23901	0	0	0
T10	664	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T52	522	0	0	0
T53	506	0	0	0
T102	0	1	0	0
T114	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	1000	0	0
T1	17410	8	0	0
T2	525	0	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	3	0	0
T40	0	9	0	0
T41	0	11	0	0
T43	0	11	0	0
T44	0	1	0	0
T47	0	10	0	0
T50	0	10	0	0
T51	0	11	0	0
T109	0	18	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	151	0	0
T1	17410	2	0	0
T2	525	0	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	1	0	0
T40	0	1	0	0
T41	0	2	0	0
T43	0	2	0	0
T44	0	1	0	0
T47	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T109	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	8788625	0	0
T1	17410	8845	0	0
T2	525	124	0	0
T4	9352	492	0	0
T5	407	6	0	0
T6	500	99	0	0
T14	402	1	0	0
T15	405	4	0	0
T16	408	7	0	0
T19	521	120	0	0
T20	642	241	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	8791064	0	0
T1	17410	8868	0	0
T2	525	125	0	0
T4	9352	501	0	0
T5	407	7	0	0
T6	500	100	0	0
T14	402	2	0	0
T15	405	5	0	0
T16	408	8	0	0
T19	521	121	0	0
T20	642	242	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	183	0	0
T1	17410	2	0	0
T2	525	0	0	0
T3	0	1	0	0
T4	9352	1	0	0
T5	407	0	0	0
T6	500	0	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T18	0	1	0	0
T19	521	0	0	0
T20	642	0	0	0
T40	0	1	0	0
T43	0	2	0	0
T44	0	1	0	0
T47	0	2	0	0
T50	0	1	0	0
T51	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	154	0	0
T1	17410	2	0	0
T2	525	0	0	0
T3	41713	1	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	1	0	0
T40	0	1	0	0
T41	0	2	0	0
T43	0	2	0	0
T44	0	1	0	0
T47	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	151	0	0
T1	17410	2	0	0
T2	525	0	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	1	0	0
T40	0	1	0	0
T41	0	2	0	0
T43	0	2	0	0
T44	0	1	0	0
T47	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T109	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	151	0	0
T1	17410	2	0	0
T2	525	0	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	1	0	0
T40	0	1	0	0
T41	0	2	0	0
T43	0	2	0	0
T44	0	1	0	0
T47	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T109	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	849	0	0
T1	17410	6	0	0
T2	525	0	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	2	0	0
T40	0	8	0	0
T41	0	9	0	0
T43	0	9	0	0
T47	0	9	0	0
T50	0	9	0	0
T51	0	10	0	0
T105	0	9	0	0
T109	0	15	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	7273	0	0
T1	17410	31	0	0
T2	525	0	0	0
T3	0	53	0	0
T4	9352	14	0	0
T5	407	0	0	0
T6	500	8	0	0
T7	0	10	0	0
T8	0	31	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	0	5	0	0
T18	0	3	0	0
T19	521	4	0	0
T20	642	0	0	0
T52	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	9037396	0	0
T1	17410	9073	0	0
T2	525	125	0	0
T4	9352	6138	0	0
T5	407	7	0	0
T6	500	100	0	0
T14	402	2	0	0
T15	405	5	0	0
T16	408	8	0	0
T19	521	121	0	0
T20	642	242	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	151	0	0
T1	17410	2	0	0
T2	525	0	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	1	0	0
T40	0	1	0	0
T41	0	2	0	0
T43	0	2	0	0
T44	0	1	0	0
T47	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T109	0	3	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T6,T19
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T19
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T12,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T7,T12,T24

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T24,T56

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T12,T24
1	0	Covered	T4,T6,T19
1	1	Covered	T7,T12,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T24,T56
0	1	Covered	T40,T74,T104
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T24,T56
0	1	Unreachable
1	0	Covered	T7,T24,T56

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T12,T24
DetectSt	168	Covered	T7,T24,T56
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T7,T24,T56

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T24,T56
DebounceSt->IdleSt	163	Covered	T12,T40,T75
DetectSt->IdleSt	186	Covered	T40,T74,T104
DetectSt->StableSt	191	Covered	T7,T24,T56
IdleSt->DebounceSt	148	Covered	T7,T12,T24
StableSt->IdleSt	206	Covered	T7,T24,T56

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T12,T24
0	1	Covered	T7,T12,T24
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T24,T56
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T12,T24
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T55
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T24,T56
DebounceSt	-	0	1	0	-	-	-	Covered	T12,T40,T41
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T12,T24
DetectSt	-	-	-	-	1	-	-	Covered	T40,T74,T104
DetectSt	-	-	-	-	0	1	-	Covered	T7,T24,T56
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T24,T56
StableSt	-	-	-	-	-	-	0	Covered	T7,T24,T56
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9721734	169	0	0
CntIncr_A	9721734	109951	0	0
CntNoWrap_A	9721734	9034726	0	0
DetectStDropOut_A	9721734	10	0	0
DetectedOut_A	9721734	9982	0	0
DetectedPulseOut_A	9721734	49	0	0
DisabledIdleSt_A	9721734	7487420	0	0
DisabledNoDetection_A	9721734	7489919	0	0
EnterDebounceSt_A	9721734	111	0	0
EnterDetectSt_A	9721734	59	0	0
EnterStableSt_A	9721734	49	0	0
PulseIsPulse_A	9721734	49	0	0
StayInStableSt	9721734	9933	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9721734	7273	0	0
gen_low_level_sva.LowLevelEvent_A	9721734	9037396	0	0
gen_sticky_sva.StableStDropOut_A	9721734	1218504	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	169	0	0
T7	1548	4	0	0
T8	27383	0	0	0
T9	23901	0	0	0
T10	664	0	0	0
T12	0	4	0	0
T17	522	0	0	0
T18	61537	0	0	0
T24	0	4	0	0
T25	486	0	0	0
T40	0	3	0	0
T52	522	0	0	0
T53	506	0	0	0
T54	522	0	0	0
T56	0	4	0	0
T60	0	2	0	0
T73	0	2	0	0
T74	0	4	0	0
T75	0	2	0	0
T76	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	109951	0	0
T7	1548	30	0	0
T8	27383	0	0	0
T9	23901	0	0	0
T10	664	0	0	0
T12	0	220	0	0
T17	522	0	0	0
T18	61537	0	0	0
T24	0	86	0	0
T25	486	0	0	0
T40	0	136	0	0
T52	522	0	0	0
T53	506	0	0	0
T54	522	0	0	0
T56	0	34	0	0
T60	0	44	0	0
T73	0	42	0	0
T74	0	200	0	0
T75	0	43	0	0
T76	0	63	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	9034726	0	0
T1	17410	9049	0	0
T2	525	124	0	0
T4	9352	6128	0	0
T5	407	6	0	0
T6	500	99	0	0
T14	402	1	0	0
T15	405	4	0	0
T16	408	7	0	0
T19	521	120	0	0
T20	642	241	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	10	0	0
T31	29866	0	0	0
T33	19622	0	0	0
T40	8254	1	0	0
T66	492	0	0	0
T67	495	0	0	0
T68	496	0	0	0
T74	0	1	0	0
T85	0	1	0	0
T103	0	1	0	0
T104	0	1	0	0
T123	20853	0	0	0
T127	0	2	0	0
T128	0	1	0	0
T129	0	2	0	0
T130	794	0	0	0
T131	503	0	0	0
T132	511	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	9982	0	0
T7	1548	166	0	0
T8	27383	0	0	0
T9	23901	0	0	0
T10	664	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T24	0	137	0	0
T25	486	0	0	0
T34	0	222	0	0
T52	522	0	0	0
T53	506	0	0	0
T54	522	0	0	0
T56	0	195	0	0
T60	0	277	0	0
T73	0	149	0	0
T74	0	305	0	0
T76	0	295	0	0
T99	0	187	0	0
T109	0	82	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	49	0	0
T7	1548	2	0	0
T8	27383	0	0	0
T9	23901	0	0	0
T10	664	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T24	0	2	0	0
T25	486	0	0	0
T34	0	1	0	0
T52	522	0	0	0
T53	506	0	0	0
T54	522	0	0	0
T56	0	2	0	0
T60	0	1	0	0
T73	0	1	0	0
T74	0	1	0	0
T76	0	1	0	0
T99	0	1	0	0
T109	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	7487420	0	0
T1	17410	9049	0	0
T2	525	124	0	0
T4	9352	6128	0	0
T5	407	6	0	0
T6	500	99	0	0
T14	402	1	0	0
T15	405	4	0	0
T16	408	7	0	0
T19	521	120	0	0
T20	642	241	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	7489919	0	0
T1	17410	9073	0	0
T2	525	125	0	0
T4	9352	6138	0	0
T5	407	7	0	0
T6	500	100	0	0
T14	402	2	0	0
T15	405	5	0	0
T16	408	8	0	0
T19	521	121	0	0
T20	642	242	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	111	0	0
T7	1548	2	0	0
T8	27383	0	0	0
T9	23901	0	0	0
T10	664	0	0	0
T12	0	4	0	0
T17	522	0	0	0
T18	61537	0	0	0
T24	0	2	0	0
T25	486	0	0	0
T40	0	2	0	0
T52	522	0	0	0
T53	506	0	0	0
T54	522	0	0	0
T56	0	2	0	0
T60	0	1	0	0
T73	0	1	0	0
T74	0	2	0	0
T75	0	2	0	0
T76	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	59	0	0
T7	1548	2	0	0
T8	27383	0	0	0
T9	23901	0	0	0
T10	664	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T24	0	2	0	0
T25	486	0	0	0
T34	0	1	0	0
T40	0	1	0	0
T52	522	0	0	0
T53	506	0	0	0
T54	522	0	0	0
T56	0	2	0	0
T60	0	1	0	0
T73	0	1	0	0
T74	0	2	0	0
T76	0	1	0	0
T109	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	49	0	0
T7	1548	2	0	0
T8	27383	0	0	0
T9	23901	0	0	0
T10	664	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T24	0	2	0	0
T25	486	0	0	0
T34	0	1	0	0
T52	522	0	0	0
T53	506	0	0	0
T54	522	0	0	0
T56	0	2	0	0
T60	0	1	0	0
T73	0	1	0	0
T74	0	1	0	0
T76	0	1	0	0
T99	0	1	0	0
T109	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	49	0	0
T7	1548	2	0	0
T8	27383	0	0	0
T9	23901	0	0	0
T10	664	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T24	0	2	0	0
T25	486	0	0	0
T34	0	1	0	0
T52	522	0	0	0
T53	506	0	0	0
T54	522	0	0	0
T56	0	2	0	0
T60	0	1	0	0
T73	0	1	0	0
T74	0	1	0	0
T76	0	1	0	0
T99	0	1	0	0
T109	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	9933	0	0
T7	1548	164	0	0
T8	27383	0	0	0
T9	23901	0	0	0
T10	664	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T24	0	135	0	0
T25	486	0	0	0
T34	0	221	0	0
T52	522	0	0	0
T53	506	0	0	0
T54	522	0	0	0
T56	0	193	0	0
T60	0	276	0	0
T73	0	148	0	0
T74	0	304	0	0
T76	0	294	0	0
T99	0	186	0	0
T109	0	81	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	7273	0	0
T1	17410	31	0	0
T2	525	0	0	0
T3	0	53	0	0
T4	9352	14	0	0
T5	407	0	0	0
T6	500	8	0	0
T7	0	10	0	0
T8	0	31	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	0	5	0	0
T18	0	3	0	0
T19	521	4	0	0
T20	642	0	0	0
T52	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	9037396	0	0
T1	17410	9073	0	0
T2	525	125	0	0
T4	9352	6138	0	0
T5	407	7	0	0
T6	500	100	0	0
T14	402	2	0	0
T15	405	5	0	0
T16	408	8	0	0
T19	521	121	0	0
T20	642	242	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	1218504	0	0
T7	1548	878	0	0
T8	27383	0	0	0
T9	23901	0	0	0
T10	664	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T24	0	409	0	0
T25	486	0	0	0
T34	0	159	0	0
T52	522	0	0	0
T53	506	0	0	0
T54	522	0	0	0
T56	0	775550	0	0
T60	0	297	0	0
T73	0	316	0	0
T74	0	78	0	0
T76	0	273	0	0
T99	0	346	0	0
T109	0	65	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T19

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T6,T19
1	1	Covered	T4,T6,T19

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T12,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T7,T12,T24

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T24,T56

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T12,T24
1	0	Covered	T4,T6,T19
1	1	Covered	T7,T12,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T56,T60
0	1	Covered	T24,T102,T103
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T56,T60
0	1	Unreachable
1	0	Covered	T7,T56,T60

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T12,T24
DetectSt	168	Covered	T7,T24,T56
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T7,T56,T60

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T24,T56
DebounceSt->IdleSt	163	Covered	T12,T24,T74
DetectSt->IdleSt	186	Covered	T24,T102,T103
DetectSt->StableSt	191	Covered	T7,T56,T60
IdleSt->DebounceSt	148	Covered	T7,T12,T24
StableSt->IdleSt	206	Covered	T7,T56,T60

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T12,T24
0	1	Covered	T7,T12,T24
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T24,T56
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T12,T24
IdleSt	0	-	-	-	-	-	-	Covered	T4,T6,T19
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T55
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T24,T56
DebounceSt	-	0	1	0	-	-	-	Covered	T12,T24,T74
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T12,T24
DetectSt	-	-	-	-	1	-	-	Covered	T24,T102,T103
DetectSt	-	-	-	-	0	1	-	Covered	T7,T56,T60
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T56,T60
StableSt	-	-	-	-	-	-	0	Covered	T7,T56,T60
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9721734	175	0	0
CntIncr_A	9721734	202679	0	0
CntNoWrap_A	9721734	9034720	0	0
DetectStDropOut_A	9721734	16	0	0
DetectedOut_A	9721734	339736	0	0
DetectedPulseOut_A	9721734	47	0	0
DisabledIdleSt_A	9721734	7487420	0	0
DisabledNoDetection_A	9721734	7489919	0	0
EnterDebounceSt_A	9721734	113	0	0
EnterDetectSt_A	9721734	63	0	0
EnterStableSt_A	9721734	47	0	0
PulseIsPulse_A	9721734	47	0	0
StayInStableSt	9721734	339689	0	0
gen_high_level_sva.HighLevelEvent_A	9721734	9037396	0	0
gen_sticky_sva.StableStDropOut_A	9721734	811639	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	175	0	0
T7	1548	4	0	0
T8	27383	0	0	0
T9	23901	0	0	0
T10	664	0	0	0
T12	0	4	0	0
T17	522	0	0	0
T18	61537	0	0	0
T24	0	6	0	0
T25	486	0	0	0
T40	0	2	0	0
T52	522	0	0	0
T53	506	0	0	0
T54	522	0	0	0
T56	0	4	0	0
T60	0	2	0	0
T73	0	2	0	0
T74	0	3	0	0
T75	0	2	0	0
T76	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	202679	0	0
T7	1548	110	0	0
T8	27383	0	0	0
T9	23901	0	0	0
T10	664	0	0	0
T12	0	168	0	0
T17	522	0	0	0
T18	61537	0	0	0
T24	0	352	0	0
T25	486	0	0	0
T40	0	14	0	0
T52	522	0	0	0
T53	506	0	0	0
T54	522	0	0	0
T56	0	118	0	0
T60	0	99	0	0
T73	0	84	0	0
T74	0	48	0	0
T75	0	44	0	0
T76	0	14	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	9034720	0	0
T1	17410	9049	0	0
T2	525	124	0	0
T4	9352	6128	0	0
T5	407	6	0	0
T6	500	99	0	0
T14	402	1	0	0
T15	405	4	0	0
T16	408	7	0	0
T19	521	120	0	0
T20	642	241	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	16	0	0
T24	1115	2	0	0
T26	22699	0	0	0
T43	691	0	0	0
T44	626	0	0	0
T45	32295	0	0	0
T46	6466	0	0	0
T63	1417	0	0	0
T70	505	0	0	0
T85	0	2	0	0
T102	0	1	0	0
T103	0	3	0	0
T133	0	5	0	0
T134	0	3	0	0
T135	402	0	0	0
T136	503	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	339736	0	0
T7	1548	746	0	0
T8	27383	0	0	0
T9	23901	0	0	0
T10	664	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T40	0	41	0	0
T41	0	4	0	0
T52	522	0	0	0
T53	506	0	0	0
T54	522	0	0	0
T56	0	590	0	0
T60	0	401	0	0
T73	0	339	0	0
T74	0	75	0	0
T76	0	108	0	0
T100	0	255	0	0
T125	0	6811	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	47	0	0
T7	1548	2	0	0
T8	27383	0	0	0
T9	23901	0	0	0
T10	664	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T40	0	1	0	0
T41	0	1	0	0
T52	522	0	0	0
T53	506	0	0	0
T54	522	0	0	0
T56	0	2	0	0
T60	0	1	0	0
T73	0	1	0	0
T74	0	1	0	0
T76	0	1	0	0
T100	0	2	0	0
T125	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	7487420	0	0
T1	17410	9049	0	0
T2	525	124	0	0
T4	9352	6128	0	0
T5	407	6	0	0
T6	500	99	0	0
T14	402	1	0	0
T15	405	4	0	0
T16	408	7	0	0
T19	521	120	0	0
T20	642	241	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	7489919	0	0
T1	17410	9073	0	0
T2	525	125	0	0
T4	9352	6138	0	0
T5	407	7	0	0
T6	500	100	0	0
T14	402	2	0	0
T15	405	5	0	0
T16	408	8	0	0
T19	521	121	0	0
T20	642	242	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	113	0	0
T7	1548	2	0	0
T8	27383	0	0	0
T9	23901	0	0	0
T10	664	0	0	0
T12	0	4	0	0
T17	522	0	0	0
T18	61537	0	0	0
T24	0	4	0	0
T25	486	0	0	0
T40	0	1	0	0
T52	522	0	0	0
T53	506	0	0	0
T54	522	0	0	0
T56	0	2	0	0
T60	0	1	0	0
T73	0	1	0	0
T74	0	2	0	0
T75	0	2	0	0
T76	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	63	0	0
T7	1548	2	0	0
T8	27383	0	0	0
T9	23901	0	0	0
T10	664	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T24	0	2	0	0
T25	486	0	0	0
T40	0	1	0	0
T41	0	1	0	0
T52	522	0	0	0
T53	506	0	0	0
T54	522	0	0	0
T56	0	2	0	0
T60	0	1	0	0
T73	0	1	0	0
T74	0	1	0	0
T76	0	1	0	0
T100	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	47	0	0
T7	1548	2	0	0
T8	27383	0	0	0
T9	23901	0	0	0
T10	664	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T40	0	1	0	0
T41	0	1	0	0
T52	522	0	0	0
T53	506	0	0	0
T54	522	0	0	0
T56	0	2	0	0
T60	0	1	0	0
T73	0	1	0	0
T74	0	1	0	0
T76	0	1	0	0
T100	0	2	0	0
T125	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	47	0	0
T7	1548	2	0	0
T8	27383	0	0	0
T9	23901	0	0	0
T10	664	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T40	0	1	0	0
T41	0	1	0	0
T52	522	0	0	0
T53	506	0	0	0
T54	522	0	0	0
T56	0	2	0	0
T60	0	1	0	0
T73	0	1	0	0
T74	0	1	0	0
T76	0	1	0	0
T100	0	2	0	0
T125	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	339689	0	0
T7	1548	744	0	0
T8	27383	0	0	0
T9	23901	0	0	0
T10	664	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T40	0	40	0	0
T41	0	3	0	0
T52	522	0	0	0
T53	506	0	0	0
T54	522	0	0	0
T56	0	588	0	0
T60	0	400	0	0
T73	0	338	0	0
T74	0	74	0	0
T76	0	107	0	0
T100	0	253	0	0
T125	0	6810	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	9037396	0	0
T1	17410	9073	0	0
T2	525	125	0	0
T4	9352	6138	0	0
T5	407	7	0	0
T6	500	100	0	0
T14	402	2	0	0
T15	405	5	0	0
T16	408	8	0	0
T19	521	121	0	0
T20	642	242	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	811639	0	0
T7	1548	206	0	0
T8	27383	0	0	0
T9	23901	0	0	0
T10	664	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T40	0	137	0	0
T41	0	57	0	0
T52	522	0	0	0
T53	506	0	0	0
T54	522	0	0	0
T56	0	775088	0	0
T60	0	115	0	0
T73	0	81	0	0
T74	0	390	0	0
T76	0	506	0	0
T100	0	459	0	0
T125	0	123	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T19

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T12,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T7,T12,T24

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T12,T56

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T12,T24
1	0	Covered	T4,T6,T19
1	1	Covered	T7,T12,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T12,T56
0	1	Covered	T73,T99,T100
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T12,T56
0	1	Unreachable
1	0	Covered	T7,T12,T56

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T12,T24
DetectSt	168	Covered	T7,T12,T56
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T7,T12,T56

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T12,T56
DebounceSt->IdleSt	163	Covered	T24,T75,T41
DetectSt->IdleSt	186	Covered	T73,T99,T100
DetectSt->StableSt	191	Covered	T7,T12,T56
IdleSt->DebounceSt	148	Covered	T7,T12,T24
StableSt->IdleSt	206	Covered	T7,T12,T56

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T12,T24
0	1	Covered	T7,T12,T24
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T12,T56
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T12,T24
IdleSt	0	-	-	-	-	-	-	Covered	T4,T6,T19
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T55
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T12,T56
DebounceSt	-	0	1	0	-	-	-	Covered	T24,T41,T99
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T12,T24
DetectSt	-	-	-	-	1	-	-	Covered	T73,T99,T100
DetectSt	-	-	-	-	0	1	-	Covered	T7,T12,T56
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T12,T56
StableSt	-	-	-	-	-	-	0	Covered	T7,T12,T56
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9721734	181	0	0
CntIncr_A	9721734	168988	0	0
CntNoWrap_A	9721734	9034714	0	0
DetectStDropOut_A	9721734	19	0	0
DetectedOut_A	9721734	730760	0	0
DetectedPulseOut_A	9721734	47	0	0
DisabledIdleSt_A	9721734	7487420	0	0
DisabledNoDetection_A	9721734	7489919	0	0
EnterDebounceSt_A	9721734	116	0	0
EnterDetectSt_A	9721734	66	0	0
EnterStableSt_A	9721734	47	0	0
PulseIsPulse_A	9721734	47	0	0
StayInStableSt	9721734	730713	0	0
gen_high_event_sva.HighLevelEvent_A	9721734	9037396	0	0
gen_high_level_sva.HighLevelEvent_A	9721734	9037396	0	0
gen_sticky_sva.StableStDropOut_A	9721734	349870	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	181	0	0
T7	1548	4	0	0
T8	27383	0	0	0
T9	23901	0	0	0
T10	664	0	0	0
T12	0	4	0	0
T17	522	0	0	0
T18	61537	0	0	0
T24	0	4	0	0
T25	486	0	0	0
T40	0	2	0	0
T52	522	0	0	0
T53	506	0	0	0
T54	522	0	0	0
T56	0	4	0	0
T60	0	2	0	0
T73	0	8	0	0
T74	0	4	0	0
T75	0	2	0	0
T76	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	168988	0	0
T7	1548	48	0	0
T8	27383	0	0	0
T9	23901	0	0	0
T10	664	0	0	0
T12	0	104	0	0
T17	522	0	0	0
T18	61537	0	0	0
T24	0	232	0	0
T25	486	0	0	0
T40	0	47	0	0
T52	522	0	0	0
T53	506	0	0	0
T54	522	0	0	0
T56	0	129156	0	0
T60	0	14	0	0
T73	0	292	0	0
T74	0	22	0	0
T75	0	46	0	0
T76	0	77	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	9034714	0	0
T1	17410	9049	0	0
T2	525	124	0	0
T4	9352	6128	0	0
T5	407	6	0	0
T6	500	99	0	0
T14	402	1	0	0
T15	405	4	0	0
T16	408	7	0	0
T19	521	120	0	0
T20	642	241	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	19	0	0
T39	1039	0	0	0
T71	3713	0	0	0
T73	945	4	0	0
T74	1095	0	0	0
T99	0	1	0	0
T100	0	3	0	0
T107	4715	0	0	0
T121	15981	0	0	0
T122	9187	0	0	0
T137	0	3	0	0
T138	0	3	0	0
T139	0	1	0	0
T140	0	1	0	0
T141	0	2	0	0
T142	0	1	0	0
T143	504	0	0	0
T144	16237	0	0	0
T145	525	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	730760	0	0
T7	1548	218	0	0
T8	27383	0	0	0
T9	23901	0	0	0
T10	664	0	0	0
T12	0	157	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T34	0	214	0	0
T40	0	71	0	0
T52	522	0	0	0
T53	506	0	0	0
T54	522	0	0	0
T56	0	646547	0	0
T60	0	100	0	0
T74	0	49	0	0
T76	0	509	0	0
T99	0	101	0	0
T109	0	25	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	47	0	0
T7	1548	2	0	0
T8	27383	0	0	0
T9	23901	0	0	0
T10	664	0	0	0
T12	0	2	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T34	0	1	0	0
T40	0	1	0	0
T52	522	0	0	0
T53	506	0	0	0
T54	522	0	0	0
T56	0	2	0	0
T60	0	1	0	0
T74	0	2	0	0
T76	0	1	0	0
T99	0	1	0	0
T109	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	7487420	0	0
T1	17410	9049	0	0
T2	525	124	0	0
T4	9352	6128	0	0
T5	407	6	0	0
T6	500	99	0	0
T14	402	1	0	0
T15	405	4	0	0
T16	408	7	0	0
T19	521	120	0	0
T20	642	241	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	7489919	0	0
T1	17410	9073	0	0
T2	525	125	0	0
T4	9352	6138	0	0
T5	407	7	0	0
T6	500	100	0	0
T14	402	2	0	0
T15	405	5	0	0
T16	408	8	0	0
T19	521	121	0	0
T20	642	242	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	116	0	0
T7	1548	2	0	0
T8	27383	0	0	0
T9	23901	0	0	0
T10	664	0	0	0
T12	0	2	0	0
T17	522	0	0	0
T18	61537	0	0	0
T24	0	4	0	0
T25	486	0	0	0
T40	0	1	0	0
T52	522	0	0	0
T53	506	0	0	0
T54	522	0	0	0
T56	0	2	0	0
T60	0	1	0	0
T73	0	4	0	0
T74	0	2	0	0
T75	0	2	0	0
T76	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	66	0	0
T7	1548	2	0	0
T8	27383	0	0	0
T9	23901	0	0	0
T10	664	0	0	0
T12	0	2	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T34	0	1	0	0
T40	0	1	0	0
T52	522	0	0	0
T53	506	0	0	0
T54	522	0	0	0
T56	0	2	0	0
T60	0	1	0	0
T73	0	4	0	0
T74	0	2	0	0
T76	0	1	0	0
T109	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	47	0	0
T7	1548	2	0	0
T8	27383	0	0	0
T9	23901	0	0	0
T10	664	0	0	0
T12	0	2	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T34	0	1	0	0
T40	0	1	0	0
T52	522	0	0	0
T53	506	0	0	0
T54	522	0	0	0
T56	0	2	0	0
T60	0	1	0	0
T74	0	2	0	0
T76	0	1	0	0
T99	0	1	0	0
T109	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	47	0	0
T7	1548	2	0	0
T8	27383	0	0	0
T9	23901	0	0	0
T10	664	0	0	0
T12	0	2	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T34	0	1	0	0
T40	0	1	0	0
T52	522	0	0	0
T53	506	0	0	0
T54	522	0	0	0
T56	0	2	0	0
T60	0	1	0	0
T74	0	2	0	0
T76	0	1	0	0
T99	0	1	0	0
T109	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	730713	0	0
T7	1548	216	0	0
T8	27383	0	0	0
T9	23901	0	0	0
T10	664	0	0	0
T12	0	155	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T34	0	213	0	0
T40	0	70	0	0
T52	522	0	0	0
T53	506	0	0	0
T54	522	0	0	0
T56	0	646545	0	0
T60	0	99	0	0
T74	0	47	0	0
T76	0	508	0	0
T99	0	100	0	0
T109	0	24	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	9037396	0	0
T1	17410	9073	0	0
T2	525	125	0	0
T4	9352	6138	0	0
T5	407	7	0	0
T6	500	100	0	0
T14	402	2	0	0
T15	405	5	0	0
T16	408	8	0	0
T19	521	121	0	0
T20	642	242	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	9037396	0	0
T1	17410	9073	0	0
T2	525	125	0	0
T4	9352	6138	0	0
T5	407	7	0	0
T6	500	100	0	0
T14	402	2	0	0
T15	405	5	0	0
T16	408	8	0	0
T19	521	121	0	0
T20	642	242	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	349870	0	0
T7	1548	821	0	0
T8	27383	0	0	0
T9	23901	0	0	0
T10	664	0	0	0
T12	0	183	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T34	0	184	0	0
T40	0	84	0	0
T52	522	0	0	0
T53	506	0	0	0
T54	522	0	0	0
T56	0	99	0	0
T60	0	518	0	0
T74	0	553	0	0
T76	0	54	0	0
T99	0	110	0	0
T109	0	198	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T35,T38,T33

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T35,T38,T33

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T35,T38,T33

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T37,T35,T38
1	0	Covered	T4,T5,T6
1	1	Covered	T35,T38,T33

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T35,T38,T33
0	1	Not Covered
1	0	Covered	T55

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T35,T38,T33
0	1	Covered	T33,T146,T147
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T35,T38,T33
1	-	Covered	T33,T146,T147

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T35,T38,T33
DetectSt	168	Covered	T35,T38,T33
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T35,T38,T33

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T35,T38,T33
DebounceSt->IdleSt	163	Covered	T75,T148
DetectSt->IdleSt	186	Covered	T55
DetectSt->StableSt	191	Covered	T35,T38,T33
IdleSt->DebounceSt	148	Covered	T35,T38,T33
StableSt->IdleSt	206	Covered	T33,T34,T146

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T35,T38,T33
0	1	Covered	T35,T38,T33
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T35,T38,T33
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T35,T38,T33
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T75
DebounceSt	-	0	1	1	-	-	-	Covered	T35,T38,T33
DebounceSt	-	0	1	0	-	-	-	Covered	T148
DebounceSt	-	0	0	-	-	-	-	Covered	T35,T38,T33
DetectSt	-	-	-	-	1	-	-	Covered	T55
DetectSt	-	-	-	-	0	1	-	Covered	T35,T38,T33
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T33,T146,T147
StableSt	-	-	-	-	-	-	0	Covered	T35,T38,T33
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9721734	96	0	0
CntIncr_A	9721734	17525	0	0
CntNoWrap_A	9721734	9034799	0	0
DetectStDropOut_A	9721734	0	0	0
DetectedOut_A	9721734	13139	0	0
DetectedPulseOut_A	9721734	46	0	0
DisabledIdleSt_A	9721734	8838194	0	0
DisabledNoDetection_A	9721734	8840638	0	0
EnterDebounceSt_A	9721734	49	0	0
EnterDetectSt_A	9721734	47	0	0
EnterStableSt_A	9721734	46	0	0
PulseIsPulse_A	9721734	46	0	0
StayInStableSt	9721734	13066	0	0
gen_high_level_sva.HighLevelEvent_A	9721734	9037396	0	0
gen_not_sticky_sva.StableStDropOut_A	9721734	19	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	96	0	0
T30	7013	0	0	0
T32	18109	0	0	0
T33	0	4	0	0
T34	0	2	0	0
T35	913	2	0	0
T38	867	2	0	0
T47	707	0	0	0
T48	5019	0	0	0
T59	3647	0	0	0
T75	0	1	0	0
T146	0	4	0	0
T147	0	6	0	0
T149	0	2	0	0
T150	0	2	0	0
T151	0	2	0	0
T152	442	0	0	0
T153	402	0	0	0
T154	705	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	17525	0	0
T30	7013	0	0	0
T32	18109	0	0	0
T33	0	136	0	0
T34	0	21	0	0
T35	913	97	0	0
T38	867	82	0	0
T47	707	0	0	0
T48	5019	0	0	0
T59	3647	0	0	0
T75	0	44	0	0
T146	0	178	0	0
T147	0	69	0	0
T149	0	74	0	0
T150	0	83	0	0
T151	0	79	0	0
T152	442	0	0	0
T153	402	0	0	0
T154	705	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	9034799	0	0
T1	17410	9049	0	0
T2	525	124	0	0
T4	9352	6128	0	0
T5	407	6	0	0
T6	500	99	0	0
T14	402	1	0	0
T15	405	4	0	0
T16	408	7	0	0
T19	521	120	0	0
T20	642	241	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	13139	0	0
T30	7013	0	0	0
T32	18109	0	0	0
T33	0	84	0	0
T34	0	41	0	0
T35	913	41	0	0
T38	867	226	0	0
T47	707	0	0	0
T48	5019	0	0	0
T59	3647	0	0	0
T146	0	78	0	0
T147	0	127	0	0
T149	0	174	0	0
T150	0	42	0	0
T151	0	3	0	0
T152	442	0	0	0
T153	402	0	0	0
T154	705	0	0	0
T155	0	39	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	46	0	0
T30	7013	0	0	0
T32	18109	0	0	0
T33	0	2	0	0
T34	0	1	0	0
T35	913	1	0	0
T38	867	1	0	0
T47	707	0	0	0
T48	5019	0	0	0
T59	3647	0	0	0
T146	0	2	0	0
T147	0	3	0	0
T149	0	1	0	0
T150	0	1	0	0
T151	0	1	0	0
T152	442	0	0	0
T153	402	0	0	0
T154	705	0	0	0
T155	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	8838194	0	0
T1	17410	9049	0	0
T2	525	124	0	0
T4	9352	6128	0	0
T5	407	6	0	0
T6	500	99	0	0
T14	402	1	0	0
T15	405	4	0	0
T16	408	7	0	0
T19	521	120	0	0
T20	642	241	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	8840638	0	0
T1	17410	9073	0	0
T2	525	125	0	0
T4	9352	6138	0	0
T5	407	7	0	0
T6	500	100	0	0
T14	402	2	0	0
T15	405	5	0	0
T16	408	8	0	0
T19	521	121	0	0
T20	642	242	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	49	0	0
T30	7013	0	0	0
T32	18109	0	0	0
T33	0	2	0	0
T34	0	1	0	0
T35	913	1	0	0
T38	867	1	0	0
T47	707	0	0	0
T48	5019	0	0	0
T59	3647	0	0	0
T75	0	1	0	0
T146	0	2	0	0
T147	0	3	0	0
T149	0	1	0	0
T150	0	1	0	0
T151	0	1	0	0
T152	442	0	0	0
T153	402	0	0	0
T154	705	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	47	0	0
T30	7013	0	0	0
T32	18109	0	0	0
T33	0	2	0	0
T34	0	1	0	0
T35	913	1	0	0
T38	867	1	0	0
T47	707	0	0	0
T48	5019	0	0	0
T59	3647	0	0	0
T146	0	2	0	0
T147	0	3	0	0
T149	0	1	0	0
T150	0	1	0	0
T151	0	1	0	0
T152	442	0	0	0
T153	402	0	0	0
T154	705	0	0	0
T155	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	46	0	0
T30	7013	0	0	0
T32	18109	0	0	0
T33	0	2	0	0
T34	0	1	0	0
T35	913	1	0	0
T38	867	1	0	0
T47	707	0	0	0
T48	5019	0	0	0
T59	3647	0	0	0
T146	0	2	0	0
T147	0	3	0	0
T149	0	1	0	0
T150	0	1	0	0
T151	0	1	0	0
T152	442	0	0	0
T153	402	0	0	0
T154	705	0	0	0
T155	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	46	0	0
T30	7013	0	0	0
T32	18109	0	0	0
T33	0	2	0	0
T34	0	1	0	0
T35	913	1	0	0
T38	867	1	0	0
T47	707	0	0	0
T48	5019	0	0	0
T59	3647	0	0	0
T146	0	2	0	0
T147	0	3	0	0
T149	0	1	0	0
T150	0	1	0	0
T151	0	1	0	0
T152	442	0	0	0
T153	402	0	0	0
T154	705	0	0	0
T155	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	13066	0	0
T30	7013	0	0	0
T32	18109	0	0	0
T33	0	81	0	0
T34	0	39	0	0
T35	913	39	0	0
T38	867	224	0	0
T47	707	0	0	0
T48	5019	0	0	0
T59	3647	0	0	0
T146	0	75	0	0
T147	0	123	0	0
T149	0	172	0	0
T150	0	40	0	0
T151	0	2	0	0
T152	442	0	0	0
T153	402	0	0	0
T154	705	0	0	0
T155	0	37	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	9037396	0	0
T1	17410	9073	0	0
T2	525	125	0	0
T4	9352	6138	0	0
T5	407	7	0	0
T6	500	100	0	0
T14	402	2	0	0
T15	405	5	0	0
T16	408	8	0	0
T19	521	121	0	0
T20	642	242	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	19	0	0
T33	19622	1	0	0
T50	66136	0	0	0
T93	15445	0	0	0
T102	0	2	0	0
T123	20853	0	0	0
T124	888	0	0	0
T127	0	1	0	0
T146	0	1	0	0
T147	0	2	0	0
T151	0	1	0	0
T156	0	2	0	0
T157	0	1	0	0
T158	0	1	0	0
T159	0	1	0	0
T160	423	0	0	0
T161	426	0	0	0
T162	438	0	0	0
T163	503	0	0	0
T164	901	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T38,T33

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T38,T33

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T38,T33

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T38,T33
1	0	Covered	T4,T6,T19
1	1	Covered	T1,T38,T33

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T38,T33
0	1	Covered	T165
1	0	Covered	T55

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T38,T33
0	1	Covered	T1,T38,T33
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T38,T33
1	-	Covered	T1,T38,T33

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T38,T33
DetectSt	168	Covered	T1,T38,T33
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T38,T33

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T38,T33
DebounceSt->IdleSt	163	Covered	T75,T146,T166
DetectSt->IdleSt	186	Covered	T165,T55
DetectSt->StableSt	191	Covered	T1,T38,T33
IdleSt->DebounceSt	148	Covered	T1,T38,T33
StableSt->IdleSt	206	Covered	T1,T38,T33

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T38,T33
0	1	Covered	T1,T38,T33
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T38,T33
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T38,T33
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T75
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T38,T33
DebounceSt	-	0	1	0	-	-	-	Covered	T146,T166,T159
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T38,T33
DetectSt	-	-	-	-	1	-	-	Covered	T165,T55
DetectSt	-	-	-	-	0	1	-	Covered	T1,T38,T33
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T38,T33
StableSt	-	-	-	-	-	-	0	Covered	T1,T38,T33
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9721734	126	0	0
CntIncr_A	9721734	87086	0	0
CntNoWrap_A	9721734	9034769	0	0
DetectStDropOut_A	9721734	1	0	0
DetectedOut_A	9721734	60534	0	0
DetectedPulseOut_A	9721734	58	0	0
DisabledIdleSt_A	9721734	8835439	0	0
DisabledNoDetection_A	9721734	8837887	0	0
EnterDebounceSt_A	9721734	66	0	0
EnterDetectSt_A	9721734	60	0	0
EnterStableSt_A	9721734	58	0	0
PulseIsPulse_A	9721734	58	0	0
StayInStableSt	9721734	60452	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9721734	2763	0	0
gen_low_level_sva.LowLevelEvent_A	9721734	9037396	0	0
gen_not_sticky_sva.StableStDropOut_A	9721734	34	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	126	0	0
T1	17410	4	0	0
T2	525	0	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T33	0	6	0	0
T38	0	2	0	0
T39	0	2	0	0
T41	0	2	0	0
T75	0	1	0	0
T96	0	4	0	0
T146	0	3	0	0
T167	0	2	0	0
T168	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	87086	0	0
T1	17410	128	0	0
T2	525	0	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T33	0	232	0	0
T38	0	82	0	0
T39	0	84	0	0
T41	0	12	0	0
T75	0	44	0	0
T96	0	74	0	0
T146	0	178	0	0
T167	0	94	0	0
T168	0	82	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	9034769	0	0
T1	17410	9045	0	0
T2	525	124	0	0
T4	9352	6128	0	0
T5	407	6	0	0
T6	500	99	0	0
T14	402	1	0	0
T15	405	4	0	0
T16	408	7	0	0
T19	521	120	0	0
T20	642	241	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	1	0	0
T165	478	1	0	0
T169	34969	0	0	0
T170	8743	0	0	0
T171	584	0	0	0
T172	402	0	0	0
T173	406	0	0	0
T174	649	0	0	0
T175	69020	0	0	0
T176	1523	0	0	0
T177	18949	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	60534	0	0
T1	17410	213	0	0
T2	525	0	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T33	0	203	0	0
T38	0	66	0	0
T39	0	127	0	0
T41	0	39	0	0
T96	0	88	0	0
T146	0	26	0	0
T151	0	85	0	0
T167	0	196	0	0
T168	0	39	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	58	0	0
T1	17410	2	0	0
T2	525	0	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T33	0	3	0	0
T38	0	1	0	0
T39	0	1	0	0
T41	0	1	0	0
T96	0	2	0	0
T146	0	1	0	0
T151	0	2	0	0
T167	0	1	0	0
T168	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	8835439	0	0
T1	17410	8390	0	0
T2	525	124	0	0
T4	9352	6128	0	0
T5	407	6	0	0
T6	500	99	0	0
T14	402	1	0	0
T15	405	4	0	0
T16	408	7	0	0
T19	521	120	0	0
T20	642	241	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	8837887	0	0
T1	17410	8413	0	0
T2	525	125	0	0
T4	9352	6138	0	0
T5	407	7	0	0
T6	500	100	0	0
T14	402	2	0	0
T15	405	5	0	0
T16	408	8	0	0
T19	521	121	0	0
T20	642	242	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	66	0	0
T1	17410	2	0	0
T2	525	0	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T33	0	3	0	0
T38	0	1	0	0
T39	0	1	0	0
T41	0	1	0	0
T75	0	1	0	0
T96	0	2	0	0
T146	0	2	0	0
T167	0	1	0	0
T168	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	60	0	0
T1	17410	2	0	0
T2	525	0	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T33	0	3	0	0
T38	0	1	0	0
T39	0	1	0	0
T41	0	1	0	0
T96	0	2	0	0
T146	0	1	0	0
T151	0	2	0	0
T167	0	1	0	0
T168	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	58	0	0
T1	17410	2	0	0
T2	525	0	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T33	0	3	0	0
T38	0	1	0	0
T39	0	1	0	0
T41	0	1	0	0
T96	0	2	0	0
T146	0	1	0	0
T151	0	2	0	0
T167	0	1	0	0
T168	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	58	0	0
T1	17410	2	0	0
T2	525	0	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T33	0	3	0	0
T38	0	1	0	0
T39	0	1	0	0
T41	0	1	0	0
T96	0	2	0	0
T146	0	1	0	0
T151	0	2	0	0
T167	0	1	0	0
T168	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	60452	0	0
T1	17410	211	0	0
T2	525	0	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T33	0	199	0	0
T38	0	65	0	0
T39	0	126	0	0
T41	0	37	0	0
T96	0	85	0	0
T146	0	25	0	0
T151	0	82	0	0
T167	0	194	0	0
T168	0	37	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	2763	0	0
T1	17410	34	0	0
T2	525	1	0	0
T3	0	23	0	0
T4	9352	17	0	0
T5	407	0	0	0
T6	500	4	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	0	6	0	0
T19	521	6	0	0
T20	642	0	0	0
T25	0	3	0	0
T52	0	7	0	0
T53	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	9037396	0	0
T1	17410	9073	0	0
T2	525	125	0	0
T4	9352	6138	0	0
T5	407	7	0	0
T6	500	100	0	0
T14	402	2	0	0
T15	405	5	0	0
T16	408	8	0	0
T19	521	121	0	0
T20	642	242	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	34	0	0
T1	17410	2	0	0
T2	525	0	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T33	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T96	0	1	0	0
T146	0	1	0	0
T151	0	1	0	0
T178	0	1	0	0
T179	0	1	0	0
T180	0	1	0	0