Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T37,T39,T75

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T37,T39,T75

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T37,T39,T41

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T37,T33
1	0	Covered	T4,T5,T6
1	1	Covered	T37,T39,T75

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T37,T39,T41
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T37,T39,T41
0	1	Covered	T41,T36,T149
1	0	Covered	T55

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T37,T39,T41
1	-	Covered	T41,T36,T149

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T37,T39,T75
DetectSt	168	Covered	T37,T39,T41
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T37,T39,T41

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T37,T39,T41
DebounceSt->IdleSt	163	Covered	T75,T181,T166
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T37,T39,T41
IdleSt->DebounceSt	148	Covered	T37,T39,T75
StableSt->IdleSt	206	Covered	T41,T36,T149

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T37,T39,T75
0	1	Covered	T37,T39,T75
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T37,T39,T41
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T37,T39,T75
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T75
DebounceSt	-	0	1	1	-	-	-	Covered	T37,T39,T41
DebounceSt	-	0	1	0	-	-	-	Covered	T181,T166
DebounceSt	-	0	0	-	-	-	-	Covered	T37,T39,T75
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T37,T39,T41
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T41,T36,T149
StableSt	-	-	-	-	-	-	0	Covered	T37,T39,T41
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9721734	79	0	0
CntIncr_A	9721734	27358	0	0
CntNoWrap_A	9721734	9034816	0	0
DetectStDropOut_A	9721734	0	0	0
DetectedOut_A	9721734	46226	0	0
DetectedPulseOut_A	9721734	38	0	0
DisabledIdleSt_A	9721734	8803085	0	0
DisabledNoDetection_A	9721734	8805531	0	0
EnterDebounceSt_A	9721734	41	0	0
EnterDetectSt_A	9721734	38	0	0
EnterStableSt_A	9721734	38	0	0
PulseIsPulse_A	9721734	38	0	0
StayInStableSt	9721734	46169	0	0
gen_high_level_sva.HighLevelEvent_A	9721734	9037396	0	0
gen_not_sticky_sva.StableStDropOut_A	9721734	18	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	79	0	0
T30	7013	0	0	0
T32	18109	0	0	0
T35	913	0	0	0
T36	0	4	0	0
T37	125312	2	0	0
T39	0	2	0	0
T41	0	2	0	0
T47	707	0	0	0
T48	5019	0	0	0
T59	3647	0	0	0
T75	0	1	0	0
T149	0	4	0	0
T151	0	2	0	0
T152	442	0	0	0
T153	402	0	0	0
T154	705	0	0	0
T168	0	2	0	0
T181	0	3	0	0
T182	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	27358	0	0
T30	7013	0	0	0
T32	18109	0	0	0
T35	913	0	0	0
T36	0	82	0	0
T37	125312	25439	0	0
T39	0	84	0	0
T41	0	12	0	0
T47	707	0	0	0
T48	5019	0	0	0
T59	3647	0	0	0
T75	0	44	0	0
T149	0	148	0	0
T151	0	79	0	0
T152	442	0	0	0
T153	402	0	0	0
T154	705	0	0	0
T168	0	82	0	0
T181	0	164	0	0
T182	0	10	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	9034816	0	0
T1	17410	9049	0	0
T2	525	124	0	0
T4	9352	6128	0	0
T5	407	6	0	0
T6	500	99	0	0
T14	402	1	0	0
T15	405	4	0	0
T16	408	7	0	0
T19	521	120	0	0
T20	642	241	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	46226	0	0
T30	7013	0	0	0
T32	18109	0	0	0
T35	913	0	0	0
T36	0	107	0	0
T37	125312	43691	0	0
T39	0	42	0	0
T41	0	55	0	0
T47	707	0	0	0
T48	5019	0	0	0
T59	3647	0	0	0
T110	0	49	0	0
T149	0	86	0	0
T151	0	125	0	0
T152	442	0	0	0
T153	402	0	0	0
T154	705	0	0	0
T168	0	38	0	0
T181	0	184	0	0
T182	0	42	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	38	0	0
T30	7013	0	0	0
T32	18109	0	0	0
T35	913	0	0	0
T36	0	2	0	0
T37	125312	1	0	0
T39	0	1	0	0
T41	0	1	0	0
T47	707	0	0	0
T48	5019	0	0	0
T59	3647	0	0	0
T110	0	1	0	0
T149	0	2	0	0
T151	0	1	0	0
T152	442	0	0	0
T153	402	0	0	0
T154	705	0	0	0
T168	0	1	0	0
T181	0	1	0	0
T182	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	8803085	0	0
T1	17410	8955	0	0
T2	525	124	0	0
T4	9352	6128	0	0
T5	407	6	0	0
T6	500	99	0	0
T14	402	1	0	0
T15	405	4	0	0
T16	408	7	0	0
T19	521	120	0	0
T20	642	241	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	8805531	0	0
T1	17410	8978	0	0
T2	525	125	0	0
T4	9352	6138	0	0
T5	407	7	0	0
T6	500	100	0	0
T14	402	2	0	0
T15	405	5	0	0
T16	408	8	0	0
T19	521	121	0	0
T20	642	242	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	41	0	0
T30	7013	0	0	0
T32	18109	0	0	0
T35	913	0	0	0
T36	0	2	0	0
T37	125312	1	0	0
T39	0	1	0	0
T41	0	1	0	0
T47	707	0	0	0
T48	5019	0	0	0
T59	3647	0	0	0
T75	0	1	0	0
T149	0	2	0	0
T151	0	1	0	0
T152	442	0	0	0
T153	402	0	0	0
T154	705	0	0	0
T168	0	1	0	0
T181	0	2	0	0
T182	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	38	0	0
T30	7013	0	0	0
T32	18109	0	0	0
T35	913	0	0	0
T36	0	2	0	0
T37	125312	1	0	0
T39	0	1	0	0
T41	0	1	0	0
T47	707	0	0	0
T48	5019	0	0	0
T59	3647	0	0	0
T110	0	1	0	0
T149	0	2	0	0
T151	0	1	0	0
T152	442	0	0	0
T153	402	0	0	0
T154	705	0	0	0
T168	0	1	0	0
T181	0	1	0	0
T182	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	38	0	0
T30	7013	0	0	0
T32	18109	0	0	0
T35	913	0	0	0
T36	0	2	0	0
T37	125312	1	0	0
T39	0	1	0	0
T41	0	1	0	0
T47	707	0	0	0
T48	5019	0	0	0
T59	3647	0	0	0
T110	0	1	0	0
T149	0	2	0	0
T151	0	1	0	0
T152	442	0	0	0
T153	402	0	0	0
T154	705	0	0	0
T168	0	1	0	0
T181	0	1	0	0
T182	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	38	0	0
T30	7013	0	0	0
T32	18109	0	0	0
T35	913	0	0	0
T36	0	2	0	0
T37	125312	1	0	0
T39	0	1	0	0
T41	0	1	0	0
T47	707	0	0	0
T48	5019	0	0	0
T59	3647	0	0	0
T110	0	1	0	0
T149	0	2	0	0
T151	0	1	0	0
T152	442	0	0	0
T153	402	0	0	0
T154	705	0	0	0
T168	0	1	0	0
T181	0	1	0	0
T182	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	46169	0	0
T30	7013	0	0	0
T32	18109	0	0	0
T35	913	0	0	0
T36	0	104	0	0
T37	125312	43689	0	0
T39	0	40	0	0
T41	0	54	0	0
T47	707	0	0	0
T48	5019	0	0	0
T59	3647	0	0	0
T110	0	47	0	0
T149	0	84	0	0
T151	0	123	0	0
T152	442	0	0	0
T153	402	0	0	0
T154	705	0	0	0
T168	0	36	0	0
T181	0	182	0	0
T182	0	40	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	9037396	0	0
T1	17410	9073	0	0
T2	525	125	0	0
T4	9352	6138	0	0
T5	407	7	0	0
T6	500	100	0	0
T14	402	2	0	0
T15	405	5	0	0
T16	408	8	0	0
T19	521	121	0	0
T20	642	242	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	18	0	0
T34	13915	0	0	0
T36	0	1	0	0
T41	16960	1	0	0
T95	30344	0	0	0
T105	174990	0	0	0
T108	16785	0	0	0
T109	18354	0	0	0
T127	0	1	0	0
T149	0	2	0	0
T157	0	1	0	0
T159	0	1	0	0
T166	0	1	0	0
T183	0	1	0	0
T184	0	1	0	0
T185	0	1	0	0
T186	424	0	0	0
T187	493	0	0	0
T188	522	0	0	0
T189	25987	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T37,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T2,T37,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T40,T33

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T37
1	0	Covered	T4,T6,T19
1	1	Covered	T2,T37,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T40,T33
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T40,T33
0	1	Covered	T2,T40,T33
1	0	Covered	T55

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T40,T33
1	-	Covered	T2,T40,T33

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T37,T40
DetectSt	168	Covered	T2,T40,T33
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T2,T40,T33

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T40,T33
DebounceSt->IdleSt	163	Covered	T37,T75,T149
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T2,T40,T33
IdleSt->DebounceSt	148	Covered	T2,T37,T40
StableSt->IdleSt	206	Covered	T2,T40,T33

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T37,T40
0	1	Covered	T2,T37,T40
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T40,T33
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T37,T40
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T75
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T40,T33
DebounceSt	-	0	1	0	-	-	-	Covered	T37,T149,T110
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T37,T40
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T2,T40,T33
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T40,T33
StableSt	-	-	-	-	-	-	0	Covered	T2,T40,T33
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9721734	130	0	0
CntIncr_A	9721734	32840	0	0
CntNoWrap_A	9721734	9034765	0	0
DetectStDropOut_A	9721734	0	0	0
DetectedOut_A	9721734	4605	0	0
DetectedPulseOut_A	9721734	61	0	0
DisabledIdleSt_A	9721734	8841995	0	0
DisabledNoDetection_A	9721734	8844446	0	0
EnterDebounceSt_A	9721734	70	0	0
EnterDetectSt_A	9721734	61	0	0
EnterStableSt_A	9721734	61	0	0
PulseIsPulse_A	9721734	61	0	0
StayInStableSt	9721734	4514	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9721734	3119	0	0
gen_low_level_sva.LowLevelEvent_A	9721734	9037396	0	0
gen_not_sticky_sva.StableStDropOut_A	9721734	30	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	130	0	0
T2	525	2	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T9	23901	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T33	0	4	0	0
T36	0	4	0	0
T37	0	1	0	0
T39	0	2	0	0
T40	0	6	0	0
T52	522	0	0	0
T75	0	1	0	0
T146	0	2	0	0
T147	0	4	0	0
T149	0	5	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	32840	0	0
T2	525	33	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T9	23901	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T33	0	136	0	0
T36	0	82	0	0
T37	0	25439	0	0
T39	0	84	0	0
T40	0	129	0	0
T52	522	0	0	0
T75	0	44	0	0
T146	0	89	0	0
T147	0	46	0	0
T149	0	222	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	9034765	0	0
T1	17410	9049	0	0
T2	525	122	0	0
T4	9352	6128	0	0
T5	407	6	0	0
T6	500	99	0	0
T14	402	1	0	0
T15	405	4	0	0
T16	408	7	0	0
T19	521	120	0	0
T20	642	241	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	4605	0	0
T2	525	3	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T9	23901	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T33	0	154	0	0
T36	0	83	0	0
T39	0	120	0	0
T40	0	178	0	0
T52	522	0	0	0
T146	0	191	0	0
T147	0	97	0	0
T149	0	218	0	0
T150	0	185	0	0
T168	0	32	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	61	0	0
T2	525	1	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T9	23901	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T33	0	2	0	0
T36	0	2	0	0
T39	0	1	0	0
T40	0	3	0	0
T52	522	0	0	0
T146	0	1	0	0
T147	0	2	0	0
T149	0	2	0	0
T150	0	2	0	0
T168	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	8841995	0	0
T1	17410	8955	0	0
T2	525	3	0	0
T4	9352	6128	0	0
T5	407	6	0	0
T6	500	99	0	0
T14	402	1	0	0
T15	405	4	0	0
T16	408	7	0	0
T19	521	120	0	0
T20	642	241	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	8844446	0	0
T1	17410	8978	0	0
T2	525	3	0	0
T4	9352	6138	0	0
T5	407	7	0	0
T6	500	100	0	0
T14	402	2	0	0
T15	405	5	0	0
T16	408	8	0	0
T19	521	121	0	0
T20	642	242	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	70	0	0
T2	525	1	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T9	23901	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T33	0	2	0	0
T36	0	2	0	0
T37	0	1	0	0
T39	0	1	0	0
T40	0	3	0	0
T52	522	0	0	0
T75	0	1	0	0
T146	0	1	0	0
T147	0	2	0	0
T149	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	61	0	0
T2	525	1	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T9	23901	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T33	0	2	0	0
T36	0	2	0	0
T39	0	1	0	0
T40	0	3	0	0
T52	522	0	0	0
T146	0	1	0	0
T147	0	2	0	0
T149	0	2	0	0
T150	0	2	0	0
T168	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	61	0	0
T2	525	1	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T9	23901	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T33	0	2	0	0
T36	0	2	0	0
T39	0	1	0	0
T40	0	3	0	0
T52	522	0	0	0
T146	0	1	0	0
T147	0	2	0	0
T149	0	2	0	0
T150	0	2	0	0
T168	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	61	0	0
T2	525	1	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T9	23901	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T33	0	2	0	0
T36	0	2	0	0
T39	0	1	0	0
T40	0	3	0	0
T52	522	0	0	0
T146	0	1	0	0
T147	0	2	0	0
T149	0	2	0	0
T150	0	2	0	0
T168	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	4514	0	0
T2	525	2	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T9	23901	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T33	0	151	0	0
T36	0	81	0	0
T39	0	119	0	0
T40	0	174	0	0
T52	522	0	0	0
T146	0	189	0	0
T147	0	95	0	0
T149	0	215	0	0
T150	0	182	0	0
T168	0	31	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	3119	0	0
T1	17410	37	0	0
T2	525	1	0	0
T3	0	24	0	0
T4	9352	15	0	0
T5	407	0	0	0
T6	500	7	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	0	7	0	0
T19	521	6	0	0
T20	642	2	0	0
T25	0	6	0	0
T52	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	9037396	0	0
T1	17410	9073	0	0
T2	525	125	0	0
T4	9352	6138	0	0
T5	407	7	0	0
T6	500	100	0	0
T14	402	2	0	0
T15	405	5	0	0
T16	408	8	0	0
T19	521	121	0	0
T20	642	242	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	30	0	0
T2	525	1	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T9	23901	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T33	0	1	0	0
T36	0	2	0	0
T39	0	1	0	0
T40	0	2	0	0
T52	522	0	0	0
T147	0	2	0	0
T149	0	1	0	0
T150	0	1	0	0
T168	0	1	0	0
T183	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T19

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T6,T19
1	1	Covered	T4,T6,T19

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T37,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T37,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T37,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T37,T38
1	0	Covered	T4,T6,T19
1	1	Covered	T1,T37,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T37,T38
0	1	Covered	T33,T175
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T37,T38
0	1	Covered	T1,T37,T38
1	0	Covered	T55

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T37,T38
1	-	Covered	T1,T37,T38

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T37,T38
DetectSt	168	Covered	T1,T37,T38
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T37,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T37,T38
DebounceSt->IdleSt	163	Covered	T75,T181,T110
DetectSt->IdleSt	186	Covered	T33,T175
DetectSt->StableSt	191	Covered	T1,T37,T38
IdleSt->DebounceSt	148	Covered	T1,T37,T38
StableSt->IdleSt	206	Covered	T1,T37,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T37,T38
0	1	Covered	T1,T37,T38
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T37,T38
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T37,T38
IdleSt	0	-	-	-	-	-	-	Covered	T4,T6,T19
DebounceSt	-	1	-	-	-	-	-	Covered	T75
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T37,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T181,T110,T166
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T37,T38
DetectSt	-	-	-	-	1	-	-	Covered	T33,T175
DetectSt	-	-	-	-	0	1	-	Covered	T1,T37,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T37,T38
StableSt	-	-	-	-	-	-	0	Covered	T1,T37,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9721734	138	0	0
CntIncr_A	9721734	160146	0	0
CntNoWrap_A	9721734	9034757	0	0
DetectStDropOut_A	9721734	2	0	0
DetectedOut_A	9721734	68304	0	0
DetectedPulseOut_A	9721734	65	0	0
DisabledIdleSt_A	9721734	8663212	0	0
DisabledNoDetection_A	9721734	8665657	0	0
EnterDebounceSt_A	9721734	71	0	0
EnterDetectSt_A	9721734	67	0	0
EnterStableSt_A	9721734	65	0	0
PulseIsPulse_A	9721734	65	0	0
StayInStableSt	9721734	68209	0	0
gen_high_level_sva.HighLevelEvent_A	9721734	9037396	0	0
gen_not_sticky_sva.StableStDropOut_A	9721734	34	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	138	0	0
T1	17410	4	0	0
T2	525	0	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T33	0	6	0	0
T37	0	4	0	0
T38	0	4	0	0
T75	0	1	0	0
T105	0	4	0	0
T110	0	5	0	0
T178	0	4	0	0
T181	0	3	0	0
T190	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	160146	0	0
T1	17410	128	0	0
T2	525	0	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T33	0	232	0	0
T37	0	50878	0	0
T38	0	164	0	0
T75	0	43	0	0
T105	0	84	0	0
T110	0	70526	0	0
T178	0	180	0	0
T181	0	164	0	0
T190	0	28	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	9034757	0	0
T1	17410	9045	0	0
T2	525	124	0	0
T4	9352	6128	0	0
T5	407	6	0	0
T6	500	99	0	0
T14	402	1	0	0
T15	405	4	0	0
T16	408	7	0	0
T19	521	120	0	0
T20	642	241	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	2	0	0
T33	19622	1	0	0
T50	66136	0	0	0
T93	15445	0	0	0
T123	20853	0	0	0
T124	888	0	0	0
T160	423	0	0	0
T161	426	0	0	0
T162	438	0	0	0
T163	503	0	0	0
T164	901	0	0	0
T175	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	68304	0	0
T1	17410	427	0	0
T2	525	0	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T33	0	57	0	0
T37	0	30374	0	0
T38	0	170	0	0
T105	0	137	0	0
T110	0	24217	0	0
T178	0	84	0	0
T181	0	62	0	0
T190	0	82	0	0
T191	0	46	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	65	0	0
T1	17410	2	0	0
T2	525	0	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T33	0	2	0	0
T37	0	2	0	0
T38	0	2	0	0
T105	0	2	0	0
T110	0	2	0	0
T178	0	2	0	0
T181	0	1	0	0
T190	0	2	0	0
T191	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	8663212	0	0
T1	17410	8390	0	0
T2	525	124	0	0
T4	9352	6128	0	0
T5	407	6	0	0
T6	500	99	0	0
T14	402	1	0	0
T15	405	4	0	0
T16	408	7	0	0
T19	521	120	0	0
T20	642	241	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	8665657	0	0
T1	17410	8413	0	0
T2	525	125	0	0
T4	9352	6138	0	0
T5	407	7	0	0
T6	500	100	0	0
T14	402	2	0	0
T15	405	5	0	0
T16	408	8	0	0
T19	521	121	0	0
T20	642	242	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	71	0	0
T1	17410	2	0	0
T2	525	0	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T33	0	3	0	0
T37	0	2	0	0
T38	0	2	0	0
T75	0	1	0	0
T105	0	2	0	0
T110	0	3	0	0
T178	0	2	0	0
T181	0	2	0	0
T190	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	67	0	0
T1	17410	2	0	0
T2	525	0	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T33	0	3	0	0
T37	0	2	0	0
T38	0	2	0	0
T105	0	2	0	0
T110	0	2	0	0
T178	0	2	0	0
T181	0	1	0	0
T190	0	2	0	0
T191	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	65	0	0
T1	17410	2	0	0
T2	525	0	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T33	0	2	0	0
T37	0	2	0	0
T38	0	2	0	0
T105	0	2	0	0
T110	0	2	0	0
T178	0	2	0	0
T181	0	1	0	0
T190	0	2	0	0
T191	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	65	0	0
T1	17410	2	0	0
T2	525	0	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T33	0	2	0	0
T37	0	2	0	0
T38	0	2	0	0
T105	0	2	0	0
T110	0	2	0	0
T178	0	2	0	0
T181	0	1	0	0
T190	0	2	0	0
T191	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	68209	0	0
T1	17410	424	0	0
T2	525	0	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T33	0	54	0	0
T37	0	30371	0	0
T38	0	167	0	0
T105	0	134	0	0
T110	0	24214	0	0
T178	0	81	0	0
T181	0	61	0	0
T190	0	79	0	0
T191	0	44	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	9037396	0	0
T1	17410	9073	0	0
T2	525	125	0	0
T4	9352	6138	0	0
T5	407	7	0	0
T6	500	100	0	0
T14	402	2	0	0
T15	405	5	0	0
T16	408	8	0	0
T19	521	121	0	0
T20	642	242	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	34	0	0
T1	17410	1	0	0
T2	525	0	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T33	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T105	0	1	0	0
T110	0	1	0	0
T178	0	1	0	0
T181	0	1	0	0
T184	0	1	0	0
T190	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T6,T19
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T19
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T37,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T37,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T37,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T37,T35
1	0	Covered	T4,T6,T19
1	1	Covered	T1,T37,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T37,T38
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T37,T38
0	1	Covered	T1,T37,T38
1	0	Covered	T55

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T37,T38
1	-	Covered	T1,T37,T38

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T37,T38
DetectSt	168	Covered	T1,T37,T38
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T37,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T37,T38
DebounceSt->IdleSt	163	Covered	T75,T156
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T1,T37,T38
IdleSt->DebounceSt	148	Covered	T1,T37,T38
StableSt->IdleSt	206	Covered	T1,T37,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T37,T38
0	1	Covered	T1,T37,T38
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T37,T38
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T37,T38
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T75
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T37,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T156
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T37,T38
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T1,T37,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T37,T38
StableSt	-	-	-	-	-	-	0	Covered	T1,T37,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9721734	94	0	0
CntIncr_A	9721734	134383	0	0
CntNoWrap_A	9721734	9034801	0	0
DetectStDropOut_A	9721734	0	0	0
DetectedOut_A	9721734	76835	0	0
DetectedPulseOut_A	9721734	46	0	0
DisabledIdleSt_A	9721734	8556629	0	0
DisabledNoDetection_A	9721734	8559071	0	0
EnterDebounceSt_A	9721734	48	0	0
EnterDetectSt_A	9721734	46	0	0
EnterStableSt_A	9721734	46	0	0
PulseIsPulse_A	9721734	46	0	0
StayInStableSt	9721734	76769	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9721734	6834	0	0
gen_low_level_sva.LowLevelEvent_A	9721734	9037396	0	0
gen_not_sticky_sva.StableStDropOut_A	9721734	25	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	94	0	0
T1	17410	2	0	0
T2	525	0	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T33	0	4	0	0
T37	0	2	0	0
T38	0	2	0	0
T40	0	4	0	0
T75	0	1	0	0
T96	0	2	0	0
T105	0	2	0	0
T150	0	4	0	0
T181	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	134383	0	0
T1	17410	64	0	0
T2	525	0	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T33	0	136	0	0
T37	0	25439	0	0
T38	0	82	0	0
T40	0	86	0	0
T75	0	44	0	0
T96	0	37	0	0
T105	0	42	0	0
T150	0	166	0	0
T181	0	164	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	9034801	0	0
T1	17410	9047	0	0
T2	525	124	0	0
T4	9352	6128	0	0
T5	407	6	0	0
T6	500	99	0	0
T14	402	1	0	0
T15	405	4	0	0
T16	408	7	0	0
T19	521	120	0	0
T20	642	241	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	76835	0	0
T1	17410	34	0	0
T2	525	0	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T33	0	300	0	0
T37	0	18209	0	0
T38	0	40	0	0
T40	0	23	0	0
T96	0	82	0	0
T105	0	124	0	0
T150	0	85	0	0
T155	0	9	0	0
T181	0	290	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	46	0	0
T1	17410	1	0	0
T2	525	0	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T33	0	2	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	2	0	0
T96	0	1	0	0
T105	0	1	0	0
T150	0	2	0	0
T155	0	1	0	0
T181	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	8556629	0	0
T1	17410	8244	0	0
T2	525	124	0	0
T4	9352	6128	0	0
T5	407	6	0	0
T6	500	99	0	0
T14	402	1	0	0
T15	405	4	0	0
T16	408	7	0	0
T19	521	120	0	0
T20	642	241	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	8559071	0	0
T1	17410	8266	0	0
T2	525	125	0	0
T4	9352	6138	0	0
T5	407	7	0	0
T6	500	100	0	0
T14	402	2	0	0
T15	405	5	0	0
T16	408	8	0	0
T19	521	121	0	0
T20	642	242	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	48	0	0
T1	17410	1	0	0
T2	525	0	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T33	0	2	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	2	0	0
T75	0	1	0	0
T96	0	1	0	0
T105	0	1	0	0
T150	0	2	0	0
T181	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	46	0	0
T1	17410	1	0	0
T2	525	0	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T33	0	2	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	2	0	0
T96	0	1	0	0
T105	0	1	0	0
T150	0	2	0	0
T155	0	1	0	0
T181	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	46	0	0
T1	17410	1	0	0
T2	525	0	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T33	0	2	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	2	0	0
T96	0	1	0	0
T105	0	1	0	0
T150	0	2	0	0
T155	0	1	0	0
T181	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	46	0	0
T1	17410	1	0	0
T2	525	0	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T33	0	2	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	2	0	0
T96	0	1	0	0
T105	0	1	0	0
T150	0	2	0	0
T155	0	1	0	0
T181	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	76769	0	0
T1	17410	33	0	0
T2	525	0	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T33	0	297	0	0
T37	0	18208	0	0
T38	0	39	0	0
T40	0	21	0	0
T96	0	80	0	0
T105	0	123	0	0
T150	0	82	0	0
T155	0	8	0	0
T181	0	287	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	6834	0	0
T1	17410	25	0	0
T2	525	0	0	0
T3	0	56	0	0
T4	9352	13	0	0
T5	407	0	0	0
T6	500	7	0	0
T7	0	10	0	0
T8	0	27	0	0
T9	0	12	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	0	6	0	0
T19	521	5	0	0
T20	642	0	0	0
T52	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	9037396	0	0
T1	17410	9073	0	0
T2	525	125	0	0
T4	9352	6138	0	0
T5	407	7	0	0
T6	500	100	0	0
T14	402	2	0	0
T15	405	5	0	0
T16	408	8	0	0
T19	521	121	0	0
T20	642	242	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	25	0	0
T1	17410	1	0	0
T2	525	0	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T33	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	2	0	0
T105	0	1	0	0
T150	0	1	0	0
T155	0	1	0	0
T181	0	1	0	0
T192	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T19

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T6,T19
1	1	Covered	T4,T6,T19

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T37,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T2,T37,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T37,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T10
1	0	Covered	T4,T6,T19
1	1	Covered	T2,T37,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T37,T40
0	1	Covered	T185
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T37,T40
0	1	Covered	T37,T40,T33
1	0	Covered	T55

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T37,T40
1	-	Covered	T37,T40,T33

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T37,T40
DetectSt	168	Covered	T2,T37,T40
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T2,T37,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T37,T40
DebounceSt->IdleSt	163	Covered	T75,T193,T84
DetectSt->IdleSt	186	Covered	T185
DetectSt->StableSt	191	Covered	T2,T37,T40
IdleSt->DebounceSt	148	Covered	T2,T37,T40
StableSt->IdleSt	206	Covered	T37,T40,T33

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T37,T40
0	1	Covered	T2,T37,T40
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T37,T40
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T37,T40
IdleSt	0	-	-	-	-	-	-	Covered	T4,T6,T19
DebounceSt	-	1	-	-	-	-	-	Covered	T75
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T37,T40
DebounceSt	-	0	1	0	-	-	-	Covered	T193,T84
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T37,T40
DetectSt	-	-	-	-	1	-	-	Covered	T185
DetectSt	-	-	-	-	0	1	-	Covered	T2,T37,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T37,T40,T33
StableSt	-	-	-	-	-	-	0	Covered	T2,T37,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9721734	143	0	0
CntIncr_A	9721734	116562	0	0
CntNoWrap_A	9721734	9034752	0	0
DetectStDropOut_A	9721734	1	0	0
DetectedOut_A	9721734	64114	0	0
DetectedPulseOut_A	9721734	69	0	0
DisabledIdleSt_A	9721734	8665410	0	0
DisabledNoDetection_A	9721734	8667849	0	0
EnterDebounceSt_A	9721734	73	0	0
EnterDetectSt_A	9721734	70	0	0
EnterStableSt_A	9721734	69	0	0
PulseIsPulse_A	9721734	69	0	0
StayInStableSt	9721734	64013	0	0
gen_high_level_sva.HighLevelEvent_A	9721734	9037396	0	0
gen_not_sticky_sva.StableStDropOut_A	9721734	36	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	143	0	0
T2	525	2	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T9	23901	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T33	0	4	0	0
T37	0	4	0	0
T40	0	6	0	0
T52	522	0	0	0
T75	0	1	0	0
T95	0	4	0	0
T101	0	2	0	0
T105	0	4	0	0
T146	0	2	0	0
T190	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	116562	0	0
T2	525	33	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T9	23901	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T33	0	136	0	0
T37	0	50878	0	0
T40	0	129	0	0
T52	522	0	0	0
T75	0	43	0	0
T95	0	36	0	0
T101	0	25	0	0
T105	0	84	0	0
T146	0	89	0	0
T190	0	14	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	9034752	0	0
T1	17410	9049	0	0
T2	525	122	0	0
T4	9352	6128	0	0
T5	407	6	0	0
T6	500	99	0	0
T14	402	1	0	0
T15	405	4	0	0
T16	408	7	0	0
T19	521	120	0	0
T20	642	241	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	1	0	0
T185	15504	1	0	0
T194	757	0	0	0
T195	442	0	0	0
T196	1303	0	0	0
T197	42800	0	0	0
T198	528	0	0	0
T199	818	0	0	0
T200	15150	0	0	0
T201	29730	0	0	0
T202	535	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	64114	0	0
T2	525	47	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T9	23901	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T33	0	122	0	0
T37	0	43687	0	0
T40	0	90	0	0
T52	522	0	0	0
T95	0	159	0	0
T101	0	64	0	0
T105	0	220	0	0
T146	0	158	0	0
T167	0	62	0	0
T190	0	133	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	69	0	0
T2	525	1	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T9	23901	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T33	0	2	0	0
T37	0	2	0	0
T40	0	3	0	0
T52	522	0	0	0
T95	0	2	0	0
T101	0	1	0	0
T105	0	2	0	0
T146	0	1	0	0
T167	0	1	0	0
T190	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	8665410	0	0
T1	17410	8955	0	0
T2	525	3	0	0
T4	9352	6128	0	0
T5	407	6	0	0
T6	500	99	0	0
T14	402	1	0	0
T15	405	4	0	0
T16	408	7	0	0
T19	521	120	0	0
T20	642	241	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	8667849	0	0
T1	17410	8978	0	0
T2	525	3	0	0
T4	9352	6138	0	0
T5	407	7	0	0
T6	500	100	0	0
T14	402	2	0	0
T15	405	5	0	0
T16	408	8	0	0
T19	521	121	0	0
T20	642	242	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	73	0	0
T2	525	1	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T9	23901	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T33	0	2	0	0
T37	0	2	0	0
T40	0	3	0	0
T52	522	0	0	0
T75	0	1	0	0
T95	0	2	0	0
T101	0	1	0	0
T105	0	2	0	0
T146	0	1	0	0
T190	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	70	0	0
T2	525	1	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T9	23901	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T33	0	2	0	0
T37	0	2	0	0
T40	0	3	0	0
T52	522	0	0	0
T95	0	2	0	0
T101	0	1	0	0
T105	0	2	0	0
T146	0	1	0	0
T167	0	1	0	0
T190	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	69	0	0
T2	525	1	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T9	23901	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T33	0	2	0	0
T37	0	2	0	0
T40	0	3	0	0
T52	522	0	0	0
T95	0	2	0	0
T101	0	1	0	0
T105	0	2	0	0
T146	0	1	0	0
T167	0	1	0	0
T190	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	69	0	0
T2	525	1	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T9	23901	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T33	0	2	0	0
T37	0	2	0	0
T40	0	3	0	0
T52	522	0	0	0
T95	0	2	0	0
T101	0	1	0	0
T105	0	2	0	0
T146	0	1	0	0
T167	0	1	0	0
T190	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	64013	0	0
T2	525	45	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T9	23901	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T33	0	120	0	0
T37	0	43684	0	0
T40	0	86	0	0
T52	522	0	0	0
T95	0	156	0	0
T101	0	62	0	0
T105	0	217	0	0
T146	0	157	0	0
T167	0	61	0	0
T190	0	131	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	9037396	0	0
T1	17410	9073	0	0
T2	525	125	0	0
T4	9352	6138	0	0
T5	407	7	0	0
T6	500	100	0	0
T14	402	2	0	0
T15	405	5	0	0
T16	408	8	0	0
T19	521	121	0	0
T20	642	242	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	36	0	0
T30	7013	0	0	0
T32	18109	0	0	0
T33	0	2	0	0
T35	913	0	0	0
T37	125312	1	0	0
T40	0	2	0	0
T47	707	0	0	0
T48	5019	0	0	0
T59	3647	0	0	0
T95	0	1	0	0
T105	0	1	0	0
T146	0	1	0	0
T151	0	1	0	0
T152	442	0	0	0
T153	402	0	0	0
T154	705	0	0	0
T167	0	1	0	0
T183	0	1	0	0
T192	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T6,T19
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T19
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T37,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T37,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T37,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T10,T37
1	0	Covered	T4,T6,T19
1	1	Covered	T1,T37,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T37,T38
0	1	Covered	T96
1	0	Covered	T55

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T37,T38
0	1	Covered	T37,T38,T40
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T37,T38
1	-	Covered	T37,T38,T40

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T37,T38
DetectSt	168	Covered	T1,T37,T38
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T37,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T37,T38
DebounceSt->IdleSt	163	Covered	T75,T34
DetectSt->IdleSt	186	Covered	T96,T55
DetectSt->StableSt	191	Covered	T1,T37,T38
IdleSt->DebounceSt	148	Covered	T1,T37,T38
StableSt->IdleSt	206	Covered	T1,T37,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T37,T38
0	1	Covered	T1,T37,T38
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T37,T38
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T37,T38
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T75
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T37,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T34
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T37,T38
DetectSt	-	-	-	-	1	-	-	Covered	T96,T55
DetectSt	-	-	-	-	0	1	-	Covered	T1,T37,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T37,T38,T40
StableSt	-	-	-	-	-	-	0	Covered	T1,T37,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9721734	66	0	0
CntIncr_A	9721734	76568	0	0
CntNoWrap_A	9721734	9034829	0	0
DetectStDropOut_A	9721734	1	0	0
DetectedOut_A	9721734	94018	0	0
DetectedPulseOut_A	9721734	30	0	0
DisabledIdleSt_A	9721734	8660521	0	0
DisabledNoDetection_A	9721734	8662976	0	0
EnterDebounceSt_A	9721734	34	0	0
EnterDetectSt_A	9721734	32	0	0
EnterStableSt_A	9721734	30	0	0
PulseIsPulse_A	9721734	30	0	0
StayInStableSt	9721734	93972	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9721734	6350	0	0
gen_low_level_sva.LowLevelEvent_A	9721734	9037396	0	0
gen_not_sticky_sva.StableStDropOut_A	9721734	14	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	66	0	0
T1	17410	2	0	0
T2	525	0	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T34	0	1	0	0
T37	0	2	0	0
T38	0	2	0	0
T40	0	4	0	0
T71	0	2	0	0
T75	0	1	0	0
T95	0	2	0	0
T96	0	2	0	0
T149	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	76568	0	0
T1	17410	64	0	0
T2	525	0	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T34	0	21	0	0
T37	0	25439	0	0
T38	0	82	0	0
T40	0	86	0	0
T71	0	96	0	0
T75	0	44	0	0
T95	0	18	0	0
T96	0	37	0	0
T149	0	148	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	9034829	0	0
T1	17410	9047	0	0
T2	525	124	0	0
T4	9352	6128	0	0
T5	407	6	0	0
T6	500	99	0	0
T14	402	1	0	0
T15	405	4	0	0
T16	408	7	0	0
T19	521	120	0	0
T20	642	241	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	1	0	0
T36	7273	0	0	0
T96	807	1	0	0
T203	25742	0	0	0
T204	422	0	0	0
T205	402	0	0	0
T206	748	0	0	0
T207	422	0	0	0
T208	416	0	0	0
T209	527	0	0	0
T210	38704	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	94018	0	0
T1	17410	37	0	0
T2	525	0	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T37	0	4896	0	0
T38	0	39	0	0
T40	0	108	0	0
T71	0	42	0	0
T95	0	7	0	0
T146	0	60	0	0
T149	0	335	0	0
T150	0	146	0	0
T181	0	81	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	30	0	0
T1	17410	1	0	0
T2	525	0	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	2	0	0
T71	0	1	0	0
T95	0	1	0	0
T146	0	1	0	0
T149	0	2	0	0
T150	0	1	0	0
T181	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	8660521	0	0
T1	17410	8390	0	0
T2	525	124	0	0
T4	9352	6128	0	0
T5	407	6	0	0
T6	500	99	0	0
T14	402	1	0	0
T15	405	4	0	0
T16	408	7	0	0
T19	521	120	0	0
T20	642	241	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	8662976	0	0
T1	17410	8413	0	0
T2	525	125	0	0
T4	9352	6138	0	0
T5	407	7	0	0
T6	500	100	0	0
T14	402	2	0	0
T15	405	5	0	0
T16	408	8	0	0
T19	521	121	0	0
T20	642	242	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	34	0	0
T1	17410	1	0	0
T2	525	0	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T34	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	2	0	0
T71	0	1	0	0
T75	0	1	0	0
T95	0	1	0	0
T96	0	1	0	0
T149	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	32	0	0
T1	17410	1	0	0
T2	525	0	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	2	0	0
T71	0	1	0	0
T95	0	1	0	0
T96	0	1	0	0
T146	0	1	0	0
T149	0	2	0	0
T181	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	30	0	0
T1	17410	1	0	0
T2	525	0	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	2	0	0
T71	0	1	0	0
T95	0	1	0	0
T146	0	1	0	0
T149	0	2	0	0
T150	0	1	0	0
T181	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	30	0	0
T1	17410	1	0	0
T2	525	0	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	2	0	0
T71	0	1	0	0
T95	0	1	0	0
T146	0	1	0	0
T149	0	2	0	0
T150	0	1	0	0
T181	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	93972	0	0
T1	17410	35	0	0
T2	525	0	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T37	0	4895	0	0
T38	0	38	0	0
T40	0	106	0	0
T71	0	40	0	0
T95	0	6	0	0
T146	0	58	0	0
T149	0	332	0	0
T150	0	145	0	0
T181	0	78	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	6350	0	0
T1	17410	31	0	0
T2	525	0	0	0
T3	0	56	0	0
T4	9352	15	0	0
T5	407	0	0	0
T6	500	8	0	0
T8	0	27	0	0
T9	0	18	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	0	3	0	0
T19	521	5	0	0
T20	642	0	0	0
T25	0	4	0	0
T52	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	9037396	0	0
T1	17410	9073	0	0
T2	525	125	0	0
T4	9352	6138	0	0
T5	407	7	0	0
T6	500	100	0	0
T14	402	2	0	0
T15	405	5	0	0
T16	408	8	0	0
T19	521	121	0	0
T20	642	242	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	14	0	0
T30	7013	0	0	0
T32	18109	0	0	0
T35	913	0	0	0
T37	125312	1	0	0
T38	0	1	0	0
T40	0	2	0	0
T47	707	0	0	0
T48	5019	0	0	0
T59	3647	0	0	0
T95	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T152	442	0	0	0
T153	402	0	0	0
T154	705	0	0	0
T156	0	1	0	0
T181	0	1	0	0
T185	0	1	0	0
T211	0	1	0	0