Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T19

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T6,T19
1	1	Covered	T4,T6,T19

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T35,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T35,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T35,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T35,T38
1	0	Covered	T4,T6,T19
1	1	Covered	T1,T35,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T35,T38
0	1	Covered	T95,T101,T212
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T35,T38
0	1	Covered	T38,T40,T33
1	0	Covered	T55

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T35,T38
1	-	Covered	T38,T40,T33

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T35,T38
DetectSt	168	Covered	T1,T35,T38
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T35,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T35,T38
DebounceSt->IdleSt	163	Covered	T75,T95,T34
DetectSt->IdleSt	186	Covered	T95,T101,T212
DetectSt->StableSt	191	Covered	T1,T35,T38
IdleSt->DebounceSt	148	Covered	T1,T35,T38
StableSt->IdleSt	206	Covered	T1,T38,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T35,T38
0	1	Covered	T1,T35,T38
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T35,T38
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T35,T38
IdleSt	0	-	-	-	-	-	-	Covered	T4,T6,T19
DebounceSt	-	1	-	-	-	-	-	Covered	T75
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T35,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T95,T34,T103
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T35,T38
DetectSt	-	-	-	-	1	-	-	Covered	T95,T101,T212
DetectSt	-	-	-	-	0	1	-	Covered	T1,T35,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T38,T40,T33
StableSt	-	-	-	-	-	-	0	Covered	T1,T35,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9721734	124	0	0
CntIncr_A	9721734	59937	0	0
CntNoWrap_A	9721734	9034771	0	0
DetectStDropOut_A	9721734	3	0	0
DetectedOut_A	9721734	58955	0	0
DetectedPulseOut_A	9721734	57	0	0
DisabledIdleSt_A	9721734	8789063	0	0
DisabledNoDetection_A	9721734	8791517	0	0
EnterDebounceSt_A	9721734	64	0	0
EnterDetectSt_A	9721734	60	0	0
EnterStableSt_A	9721734	57	0	0
PulseIsPulse_A	9721734	57	0	0
StayInStableSt	9721734	58875	0	0
gen_high_level_sva.HighLevelEvent_A	9721734	9037396	0	0
gen_not_sticky_sva.StableStDropOut_A	9721734	33	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	124	0	0
T1	17410	2	0	0
T2	525	0	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T33	0	4	0	0
T34	0	3	0	0
T35	0	2	0	0
T38	0	4	0	0
T40	0	2	0	0
T75	0	1	0	0
T95	0	5	0	0
T96	0	6	0	0
T190	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	59937	0	0
T1	17410	29	0	0
T2	525	0	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T33	0	136	0	0
T34	0	42	0	0
T35	0	97	0	0
T38	0	164	0	0
T40	0	43	0	0
T75	0	44	0	0
T95	0	54	0	0
T96	0	111	0	0
T190	0	28	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	9034771	0	0
T1	17410	9047	0	0
T2	525	124	0	0
T4	9352	6128	0	0
T5	407	6	0	0
T6	500	99	0	0
T14	402	1	0	0
T15	405	4	0	0
T16	408	7	0	0
T19	521	120	0	0
T20	642	241	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	3	0	0
T34	13915	0	0	0
T95	30344	1	0	0
T99	1828	0	0	0
T101	0	1	0	0
T105	174990	0	0	0
T188	522	0	0	0
T189	25987	0	0	0
T212	0	1	0	0
T213	426	0	0	0
T214	13354	0	0	0
T215	495	0	0	0
T216	15156	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	58955	0	0
T1	17410	61	0	0
T2	525	0	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T33	0	154	0	0
T34	0	40	0	0
T35	0	140	0	0
T38	0	169	0	0
T40	0	43	0	0
T95	0	6	0	0
T96	0	123	0	0
T182	0	55	0	0
T190	0	62	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	57	0	0
T1	17410	1	0	0
T2	525	0	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T33	0	2	0	0
T34	0	1	0	0
T35	0	1	0	0
T38	0	2	0	0
T40	0	1	0	0
T95	0	1	0	0
T96	0	3	0	0
T182	0	1	0	0
T190	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	8789063	0	0
T1	17410	8955	0	0
T2	525	124	0	0
T4	9352	6128	0	0
T5	407	6	0	0
T6	500	99	0	0
T14	402	1	0	0
T15	405	4	0	0
T16	408	7	0	0
T19	521	120	0	0
T20	642	241	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	8791517	0	0
T1	17410	8978	0	0
T2	525	125	0	0
T4	9352	6138	0	0
T5	407	7	0	0
T6	500	100	0	0
T14	402	2	0	0
T15	405	5	0	0
T16	408	8	0	0
T19	521	121	0	0
T20	642	242	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	64	0	0
T1	17410	1	0	0
T2	525	0	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T33	0	2	0	0
T34	0	2	0	0
T35	0	1	0	0
T38	0	2	0	0
T40	0	1	0	0
T75	0	1	0	0
T95	0	3	0	0
T96	0	3	0	0
T190	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	60	0	0
T1	17410	1	0	0
T2	525	0	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T33	0	2	0	0
T34	0	1	0	0
T35	0	1	0	0
T38	0	2	0	0
T40	0	1	0	0
T95	0	2	0	0
T96	0	3	0	0
T182	0	1	0	0
T190	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	57	0	0
T1	17410	1	0	0
T2	525	0	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T33	0	2	0	0
T34	0	1	0	0
T35	0	1	0	0
T38	0	2	0	0
T40	0	1	0	0
T95	0	1	0	0
T96	0	3	0	0
T182	0	1	0	0
T190	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	57	0	0
T1	17410	1	0	0
T2	525	0	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T33	0	2	0	0
T34	0	1	0	0
T35	0	1	0	0
T38	0	2	0	0
T40	0	1	0	0
T95	0	1	0	0
T96	0	3	0	0
T182	0	1	0	0
T190	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	58875	0	0
T1	17410	59	0	0
T2	525	0	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T33	0	152	0	0
T34	0	38	0	0
T35	0	138	0	0
T38	0	166	0	0
T40	0	42	0	0
T95	0	5	0	0
T96	0	119	0	0
T182	0	53	0	0
T190	0	59	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	9037396	0	0
T1	17410	9073	0	0
T2	525	125	0	0
T4	9352	6138	0	0
T5	407	7	0	0
T6	500	100	0	0
T14	402	2	0	0
T15	405	5	0	0
T16	408	8	0	0
T19	521	121	0	0
T20	642	242	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	33	0	0
T33	0	2	0	0
T38	867	1	0	0
T40	8254	1	0	0
T42	27017	0	0	0
T49	5866	0	0	0
T60	1308	0	0	0
T61	1944	0	0	0
T62	946	0	0	0
T66	492	0	0	0
T95	0	1	0	0
T96	0	2	0	0
T110	0	1	0	0
T137	0	1	0	0
T175	0	3	0	0
T190	0	1	0	0
T217	0	1	0	0
T218	411	0	0	0
T219	526	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T6,T19
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T19
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T37,T38,T39

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T37,T38,T39

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T37,T38,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T37
1	0	Covered	T4,T6,T19
1	1	Covered	T37,T38,T39

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T37,T38,T39
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T37,T38,T39
0	1	Covered	T38,T39,T95
1	0	Covered	T55

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T37,T38,T39
1	-	Covered	T38,T39,T95

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T37,T38,T39
DetectSt	168	Covered	T37,T38,T39
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T37,T38,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T37,T38,T39
DebounceSt->IdleSt	163	Covered	T75,T220
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T37,T38,T39
IdleSt->DebounceSt	148	Covered	T37,T38,T39
StableSt->IdleSt	206	Covered	T38,T39,T71

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T37,T38,T39
0	1	Covered	T37,T38,T39
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T37,T38,T39
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T37,T38,T39
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T75
DebounceSt	-	0	1	1	-	-	-	Covered	T37,T38,T39
DebounceSt	-	0	1	0	-	-	-	Covered	T220
DebounceSt	-	0	0	-	-	-	-	Covered	T37,T38,T39
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T37,T38,T39
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T38,T39,T95
StableSt	-	-	-	-	-	-	0	Covered	T37,T38,T39
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9721734	80	0	0
CntIncr_A	9721734	62829	0	0
CntNoWrap_A	9721734	9034815	0	0
DetectStDropOut_A	9721734	0	0	0
DetectedOut_A	9721734	2478	0	0
DetectedPulseOut_A	9721734	39	0	0
DisabledIdleSt_A	9721734	8656289	0	0
DisabledNoDetection_A	9721734	8658735	0	0
EnterDebounceSt_A	9721734	41	0	0
EnterDetectSt_A	9721734	39	0	0
EnterStableSt_A	9721734	39	0	0
PulseIsPulse_A	9721734	39	0	0
StayInStableSt	9721734	2419	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9721734	6472	0	0
gen_low_level_sva.LowLevelEvent_A	9721734	9037396	0	0
gen_not_sticky_sva.StableStDropOut_A	9721734	18	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	80	0	0
T30	7013	0	0	0
T32	18109	0	0	0
T35	913	0	0	0
T37	125312	2	0	0
T38	0	2	0	0
T39	0	2	0	0
T47	707	0	0	0
T48	5019	0	0	0
T59	3647	0	0	0
T71	0	2	0	0
T75	0	1	0	0
T95	0	6	0	0
T101	0	2	0	0
T110	0	2	0	0
T146	0	2	0	0
T152	442	0	0	0
T153	402	0	0	0
T154	705	0	0	0
T190	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	62829	0	0
T30	7013	0	0	0
T32	18109	0	0	0
T35	913	0	0	0
T37	125312	25439	0	0
T38	0	82	0	0
T39	0	84	0	0
T47	707	0	0	0
T48	5019	0	0	0
T59	3647	0	0	0
T71	0	96	0	0
T75	0	43	0	0
T95	0	54	0	0
T101	0	25	0	0
T110	0	35222	0	0
T146	0	89	0	0
T152	442	0	0	0
T153	402	0	0	0
T154	705	0	0	0
T190	0	14	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	9034815	0	0
T1	17410	9049	0	0
T2	525	124	0	0
T4	9352	6128	0	0
T5	407	6	0	0
T6	500	99	0	0
T14	402	1	0	0
T15	405	4	0	0
T16	408	7	0	0
T19	521	120	0	0
T20	642	241	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	2478	0	0
T30	7013	0	0	0
T32	18109	0	0	0
T35	913	0	0	0
T37	125312	42	0	0
T38	0	41	0	0
T39	0	252	0	0
T47	707	0	0	0
T48	5019	0	0	0
T59	3647	0	0	0
T71	0	299	0	0
T95	0	121	0	0
T101	0	38	0	0
T110	0	44	0	0
T146	0	63	0	0
T152	442	0	0	0
T153	402	0	0	0
T154	705	0	0	0
T190	0	42	0	0
T192	0	42	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	39	0	0
T30	7013	0	0	0
T32	18109	0	0	0
T35	913	0	0	0
T37	125312	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T47	707	0	0	0
T48	5019	0	0	0
T59	3647	0	0	0
T71	0	1	0	0
T95	0	3	0	0
T101	0	1	0	0
T110	0	1	0	0
T146	0	1	0	0
T152	442	0	0	0
T153	402	0	0	0
T154	705	0	0	0
T190	0	1	0	0
T192	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	8656289	0	0
T1	17410	8244	0	0
T2	525	3	0	0
T4	9352	6128	0	0
T5	407	6	0	0
T6	500	99	0	0
T14	402	1	0	0
T15	405	4	0	0
T16	408	7	0	0
T19	521	120	0	0
T20	642	241	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	8658735	0	0
T1	17410	8266	0	0
T2	525	3	0	0
T4	9352	6138	0	0
T5	407	7	0	0
T6	500	100	0	0
T14	402	2	0	0
T15	405	5	0	0
T16	408	8	0	0
T19	521	121	0	0
T20	642	242	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	41	0	0
T30	7013	0	0	0
T32	18109	0	0	0
T35	913	0	0	0
T37	125312	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T47	707	0	0	0
T48	5019	0	0	0
T59	3647	0	0	0
T71	0	1	0	0
T75	0	1	0	0
T95	0	3	0	0
T101	0	1	0	0
T110	0	1	0	0
T146	0	1	0	0
T152	442	0	0	0
T153	402	0	0	0
T154	705	0	0	0
T190	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	39	0	0
T30	7013	0	0	0
T32	18109	0	0	0
T35	913	0	0	0
T37	125312	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T47	707	0	0	0
T48	5019	0	0	0
T59	3647	0	0	0
T71	0	1	0	0
T95	0	3	0	0
T101	0	1	0	0
T110	0	1	0	0
T146	0	1	0	0
T152	442	0	0	0
T153	402	0	0	0
T154	705	0	0	0
T190	0	1	0	0
T192	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	39	0	0
T30	7013	0	0	0
T32	18109	0	0	0
T35	913	0	0	0
T37	125312	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T47	707	0	0	0
T48	5019	0	0	0
T59	3647	0	0	0
T71	0	1	0	0
T95	0	3	0	0
T101	0	1	0	0
T110	0	1	0	0
T146	0	1	0	0
T152	442	0	0	0
T153	402	0	0	0
T154	705	0	0	0
T190	0	1	0	0
T192	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	39	0	0
T30	7013	0	0	0
T32	18109	0	0	0
T35	913	0	0	0
T37	125312	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T47	707	0	0	0
T48	5019	0	0	0
T59	3647	0	0	0
T71	0	1	0	0
T95	0	3	0	0
T101	0	1	0	0
T110	0	1	0	0
T146	0	1	0	0
T152	442	0	0	0
T153	402	0	0	0
T154	705	0	0	0
T190	0	1	0	0
T192	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	2419	0	0
T30	7013	0	0	0
T32	18109	0	0	0
T35	913	0	0	0
T37	125312	40	0	0
T38	0	40	0	0
T39	0	251	0	0
T47	707	0	0	0
T48	5019	0	0	0
T59	3647	0	0	0
T71	0	297	0	0
T95	0	117	0	0
T101	0	36	0	0
T110	0	43	0	0
T146	0	62	0	0
T152	442	0	0	0
T153	402	0	0	0
T154	705	0	0	0
T190	0	41	0	0
T192	0	40	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	6472	0	0
T1	17410	27	0	0
T2	525	0	0	0
T3	0	47	0	0
T4	9352	12	0	0
T5	407	0	0	0
T6	500	8	0	0
T8	0	28	0	0
T9	0	11	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	0	6	0	0
T19	521	4	0	0
T20	642	0	0	0
T25	0	7	0	0
T52	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	9037396	0	0
T1	17410	9073	0	0
T2	525	125	0	0
T4	9352	6138	0	0
T5	407	7	0	0
T6	500	100	0	0
T14	402	2	0	0
T15	405	5	0	0
T16	408	8	0	0
T19	521	121	0	0
T20	642	242	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	18	0	0
T38	867	1	0	0
T39	0	1	0	0
T40	8254	0	0	0
T42	27017	0	0	0
T49	5866	0	0	0
T60	1308	0	0	0
T61	1944	0	0	0
T62	946	0	0	0
T66	492	0	0	0
T95	0	2	0	0
T110	0	1	0	0
T137	0	1	0	0
T146	0	1	0	0
T175	0	1	0	0
T179	0	1	0	0
T184	0	1	0	0
T190	0	1	0	0
T218	411	0	0	0
T219	526	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T19

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T6,T19
1	1	Covered	T4,T6,T19

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T40,T33

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T40,T33

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T40,T33

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T40,T33
1	0	Covered	T4,T6,T19
1	1	Covered	T1,T40,T33

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T40,T33
0	1	Covered	T33
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T40,T33
0	1	Covered	T40,T33,T105
1	0	Covered	T55

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T40,T33
1	-	Covered	T40,T33,T105

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T40,T33
DetectSt	168	Covered	T1,T40,T33
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T40,T33

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T40,T33
DebounceSt->IdleSt	163	Covered	T75,T175,T221
DetectSt->IdleSt	186	Covered	T33
DetectSt->StableSt	191	Covered	T1,T40,T33
IdleSt->DebounceSt	148	Covered	T1,T40,T33
StableSt->IdleSt	206	Covered	T1,T40,T33

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T40,T33
0	1	Covered	T1,T40,T33
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T40,T33
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T40,T33
IdleSt	0	-	-	-	-	-	-	Covered	T4,T6,T19
DebounceSt	-	1	-	-	-	-	-	Covered	T75
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T40,T33
DebounceSt	-	0	1	0	-	-	-	Covered	T175,T221,T148
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T40,T33
DetectSt	-	-	-	-	1	-	-	Covered	T33
DetectSt	-	-	-	-	0	1	-	Covered	T1,T40,T33
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T40,T33,T105
StableSt	-	-	-	-	-	-	0	Covered	T1,T40,T33
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9721734	135	0	0
CntIncr_A	9721734	61131	0	0
CntNoWrap_A	9721734	9034760	0	0
DetectStDropOut_A	9721734	1	0	0
DetectedOut_A	9721734	5156	0	0
DetectedPulseOut_A	9721734	64	0	0
DisabledIdleSt_A	9721734	8863319	0	0
DisabledNoDetection_A	9721734	8865762	0	0
EnterDebounceSt_A	9721734	70	0	0
EnterDetectSt_A	9721734	65	0	0
EnterStableSt_A	9721734	64	0	0
PulseIsPulse_A	9721734	64	0	0
StayInStableSt	9721734	5065	0	0
gen_high_level_sva.HighLevelEvent_A	9721734	9037396	0	0
gen_not_sticky_sva.StableStDropOut_A	9721734	36	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	135	0	0
T1	17410	2	0	0
T2	525	0	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T33	0	4	0	0
T40	0	2	0	0
T41	0	2	0	0
T71	0	2	0	0
T75	0	1	0	0
T96	0	6	0	0
T105	0	4	0	0
T149	0	2	0	0
T182	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	61131	0	0
T1	17410	29	0	0
T2	525	0	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T33	0	136	0	0
T40	0	43	0	0
T41	0	12	0	0
T71	0	96	0	0
T75	0	43	0	0
T96	0	111	0	0
T105	0	84	0	0
T149	0	74	0	0
T182	0	10	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	9034760	0	0
T1	17410	9047	0	0
T2	525	124	0	0
T4	9352	6128	0	0
T5	407	6	0	0
T6	500	99	0	0
T14	402	1	0	0
T15	405	4	0	0
T16	408	7	0	0
T19	521	120	0	0
T20	642	241	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	1	0	0
T33	19622	1	0	0
T50	66136	0	0	0
T93	15445	0	0	0
T123	20853	0	0	0
T124	888	0	0	0
T160	423	0	0	0
T161	426	0	0	0
T162	438	0	0	0
T163	503	0	0	0
T164	901	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	5156	0	0
T1	17410	41	0	0
T2	525	0	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T33	0	120	0	0
T40	0	44	0	0
T41	0	39	0	0
T71	0	160	0	0
T96	0	179	0	0
T105	0	70	0	0
T146	0	62	0	0
T149	0	411	0	0
T182	0	3	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	64	0	0
T1	17410	1	0	0
T2	525	0	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T33	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T71	0	1	0	0
T96	0	3	0	0
T105	0	2	0	0
T146	0	1	0	0
T149	0	1	0	0
T182	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	8863319	0	0
T1	17410	8955	0	0
T2	525	124	0	0
T4	9352	6128	0	0
T5	407	6	0	0
T6	500	99	0	0
T14	402	1	0	0
T15	405	4	0	0
T16	408	7	0	0
T19	521	120	0	0
T20	642	241	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	8865762	0	0
T1	17410	8978	0	0
T2	525	125	0	0
T4	9352	6138	0	0
T5	407	7	0	0
T6	500	100	0	0
T14	402	2	0	0
T15	405	5	0	0
T16	408	8	0	0
T19	521	121	0	0
T20	642	242	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	70	0	0
T1	17410	1	0	0
T2	525	0	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T33	0	2	0	0
T40	0	1	0	0
T41	0	1	0	0
T71	0	1	0	0
T75	0	1	0	0
T96	0	3	0	0
T105	0	2	0	0
T149	0	1	0	0
T182	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	65	0	0
T1	17410	1	0	0
T2	525	0	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T33	0	2	0	0
T40	0	1	0	0
T41	0	1	0	0
T71	0	1	0	0
T96	0	3	0	0
T105	0	2	0	0
T146	0	1	0	0
T149	0	1	0	0
T182	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	64	0	0
T1	17410	1	0	0
T2	525	0	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T33	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T71	0	1	0	0
T96	0	3	0	0
T105	0	2	0	0
T146	0	1	0	0
T149	0	1	0	0
T182	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	64	0	0
T1	17410	1	0	0
T2	525	0	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T33	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T71	0	1	0	0
T96	0	3	0	0
T105	0	2	0	0
T146	0	1	0	0
T149	0	1	0	0
T182	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	5065	0	0
T1	17410	39	0	0
T2	525	0	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T33	0	119	0	0
T40	0	43	0	0
T41	0	37	0	0
T71	0	158	0	0
T96	0	175	0	0
T105	0	68	0	0
T146	0	61	0	0
T149	0	410	0	0
T182	0	2	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	9037396	0	0
T1	17410	9073	0	0
T2	525	125	0	0
T4	9352	6138	0	0
T5	407	7	0	0
T6	500	100	0	0
T14	402	2	0	0
T15	405	5	0	0
T16	408	8	0	0
T19	521	121	0	0
T20	642	242	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	36	0	0
T31	29866	0	0	0
T33	19622	1	0	0
T40	8254	1	0	0
T66	492	0	0	0
T67	495	0	0	0
T68	496	0	0	0
T96	0	2	0	0
T105	0	2	0	0
T123	20853	0	0	0
T130	794	0	0	0
T131	503	0	0	0
T132	511	0	0	0
T146	0	1	0	0
T147	0	1	0	0
T149	0	1	0	0
T151	0	1	0	0
T182	0	1	0	0
T183	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T6,T19
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T19
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T35,T33,T75

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T35,T33,T75

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T35,T33,T95

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T35
1	0	Covered	T4,T6,T19
1	1	Covered	T35,T33,T75

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T35,T33,T36
0	1	Covered	T95
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T35,T33,T36
0	1	Covered	T33,T36,T150
1	0	Covered	T55

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T35,T33,T36
1	-	Covered	T33,T36,T150

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T35,T33,T75
DetectSt	168	Covered	T35,T33,T95
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T35,T33,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T35,T33,T95
DebounceSt->IdleSt	163	Covered	T75,T183,T222
DetectSt->IdleSt	186	Covered	T95
DetectSt->StableSt	191	Covered	T35,T33,T36
IdleSt->DebounceSt	148	Covered	T35,T33,T75
StableSt->IdleSt	206	Covered	T33,T36,T150

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T35,T33,T75
0	1	Covered	T35,T33,T75
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T35,T33,T95
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T35,T33,T75
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T75
DebounceSt	-	0	1	1	-	-	-	Covered	T35,T33,T95
DebounceSt	-	0	1	0	-	-	-	Covered	T183,T222,T85
DebounceSt	-	0	0	-	-	-	-	Covered	T35,T33,T75
DetectSt	-	-	-	-	1	-	-	Covered	T95
DetectSt	-	-	-	-	0	1	-	Covered	T35,T33,T36
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T33,T36,T150
StableSt	-	-	-	-	-	-	0	Covered	T35,T33,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9721734	80	0	0
CntIncr_A	9721734	44108	0	0
CntNoWrap_A	9721734	9034815	0	0
DetectStDropOut_A	9721734	1	0	0
DetectedOut_A	9721734	2602	0	0
DetectedPulseOut_A	9721734	37	0	0
DisabledIdleSt_A	9721734	8683905	0	0
DisabledNoDetection_A	9721734	8686350	0	0
EnterDebounceSt_A	9721734	42	0	0
EnterDetectSt_A	9721734	38	0	0
EnterStableSt_A	9721734	37	0	0
PulseIsPulse_A	9721734	37	0	0
StayInStableSt	9721734	2543	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9721734	6378	0	0
gen_low_level_sva.LowLevelEvent_A	9721734	9037396	0	0
gen_not_sticky_sva.StableStDropOut_A	9721734	14	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	80	0	0
T30	7013	0	0	0
T32	18109	0	0	0
T33	0	4	0	0
T35	913	2	0	0
T36	0	2	0	0
T38	867	0	0	0
T47	707	0	0	0
T48	5019	0	0	0
T59	3647	0	0	0
T75	0	1	0	0
T95	0	2	0	0
T146	0	2	0	0
T150	0	4	0	0
T152	442	0	0	0
T153	402	0	0	0
T154	705	0	0	0
T167	0	2	0	0
T181	0	2	0	0
T182	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	44108	0	0
T30	7013	0	0	0
T32	18109	0	0	0
T33	0	136	0	0
T35	913	97	0	0
T36	0	41	0	0
T38	867	0	0	0
T47	707	0	0	0
T48	5019	0	0	0
T59	3647	0	0	0
T75	0	45	0	0
T95	0	18	0	0
T146	0	89	0	0
T150	0	166	0	0
T152	442	0	0	0
T153	402	0	0	0
T154	705	0	0	0
T167	0	94	0	0
T181	0	82	0	0
T182	0	10	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	9034815	0	0
T1	17410	9049	0	0
T2	525	124	0	0
T4	9352	6128	0	0
T5	407	6	0	0
T6	500	99	0	0
T14	402	1	0	0
T15	405	4	0	0
T16	408	7	0	0
T19	521	120	0	0
T20	642	241	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	1	0	0
T34	13915	0	0	0
T95	30344	1	0	0
T99	1828	0	0	0
T105	174990	0	0	0
T188	522	0	0	0
T189	25987	0	0	0
T213	426	0	0	0
T214	13354	0	0	0
T215	495	0	0	0
T216	15156	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	2602	0	0
T30	7013	0	0	0
T32	18109	0	0	0
T33	0	189	0	0
T35	913	42	0	0
T36	0	125	0	0
T38	867	0	0	0
T47	707	0	0	0
T48	5019	0	0	0
T59	3647	0	0	0
T146	0	38	0	0
T150	0	86	0	0
T152	442	0	0	0
T153	402	0	0	0
T154	705	0	0	0
T167	0	39	0	0
T181	0	309	0	0
T182	0	41	0	0
T217	0	7	0	0
T223	0	39	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	37	0	0
T30	7013	0	0	0
T32	18109	0	0	0
T33	0	2	0	0
T35	913	1	0	0
T36	0	1	0	0
T38	867	0	0	0
T47	707	0	0	0
T48	5019	0	0	0
T59	3647	0	0	0
T146	0	1	0	0
T150	0	2	0	0
T152	442	0	0	0
T153	402	0	0	0
T154	705	0	0	0
T167	0	1	0	0
T181	0	1	0	0
T182	0	1	0	0
T217	0	1	0	0
T223	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	8683905	0	0
T1	17410	8390	0	0
T2	525	3	0	0
T4	9352	6128	0	0
T5	407	6	0	0
T6	500	99	0	0
T14	402	1	0	0
T15	405	4	0	0
T16	408	7	0	0
T19	521	120	0	0
T20	642	241	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	8686350	0	0
T1	17410	8413	0	0
T2	525	3	0	0
T4	9352	6138	0	0
T5	407	7	0	0
T6	500	100	0	0
T14	402	2	0	0
T15	405	5	0	0
T16	408	8	0	0
T19	521	121	0	0
T20	642	242	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	42	0	0
T30	7013	0	0	0
T32	18109	0	0	0
T33	0	2	0	0
T35	913	1	0	0
T36	0	1	0	0
T38	867	0	0	0
T47	707	0	0	0
T48	5019	0	0	0
T59	3647	0	0	0
T75	0	1	0	0
T95	0	1	0	0
T146	0	1	0	0
T150	0	2	0	0
T152	442	0	0	0
T153	402	0	0	0
T154	705	0	0	0
T167	0	1	0	0
T181	0	1	0	0
T182	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	38	0	0
T30	7013	0	0	0
T32	18109	0	0	0
T33	0	2	0	0
T35	913	1	0	0
T36	0	1	0	0
T38	867	0	0	0
T47	707	0	0	0
T48	5019	0	0	0
T59	3647	0	0	0
T95	0	1	0	0
T146	0	1	0	0
T150	0	2	0	0
T152	442	0	0	0
T153	402	0	0	0
T154	705	0	0	0
T167	0	1	0	0
T181	0	1	0	0
T182	0	1	0	0
T223	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	37	0	0
T30	7013	0	0	0
T32	18109	0	0	0
T33	0	2	0	0
T35	913	1	0	0
T36	0	1	0	0
T38	867	0	0	0
T47	707	0	0	0
T48	5019	0	0	0
T59	3647	0	0	0
T146	0	1	0	0
T150	0	2	0	0
T152	442	0	0	0
T153	402	0	0	0
T154	705	0	0	0
T167	0	1	0	0
T181	0	1	0	0
T182	0	1	0	0
T217	0	1	0	0
T223	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	37	0	0
T30	7013	0	0	0
T32	18109	0	0	0
T33	0	2	0	0
T35	913	1	0	0
T36	0	1	0	0
T38	867	0	0	0
T47	707	0	0	0
T48	5019	0	0	0
T59	3647	0	0	0
T146	0	1	0	0
T150	0	2	0	0
T152	442	0	0	0
T153	402	0	0	0
T154	705	0	0	0
T167	0	1	0	0
T181	0	1	0	0
T182	0	1	0	0
T217	0	1	0	0
T223	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	2543	0	0
T30	7013	0	0	0
T32	18109	0	0	0
T33	0	186	0	0
T35	913	40	0	0
T36	0	124	0	0
T38	867	0	0	0
T47	707	0	0	0
T48	5019	0	0	0
T59	3647	0	0	0
T146	0	36	0	0
T150	0	84	0	0
T152	442	0	0	0
T153	402	0	0	0
T154	705	0	0	0
T167	0	37	0	0
T181	0	307	0	0
T182	0	39	0	0
T217	0	6	0	0
T223	0	37	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	6378	0	0
T1	17410	24	0	0
T2	525	0	0	0
T3	0	51	0	0
T4	9352	18	0	0
T5	407	0	0	0
T6	500	10	0	0
T8	0	32	0	0
T9	0	13	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	0	5	0	0
T19	521	3	0	0
T20	642	0	0	0
T25	0	3	0	0
T52	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	9037396	0	0
T1	17410	9073	0	0
T2	525	125	0	0
T4	9352	6138	0	0
T5	407	7	0	0
T6	500	100	0	0
T14	402	2	0	0
T15	405	5	0	0
T16	408	8	0	0
T19	521	121	0	0
T20	642	242	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	14	0	0
T33	19622	1	0	0
T36	0	1	0	0
T50	66136	0	0	0
T93	15445	0	0	0
T123	20853	0	0	0
T124	888	0	0	0
T127	0	1	0	0
T150	0	2	0	0
T160	423	0	0	0
T161	426	0	0	0
T162	438	0	0	0
T163	503	0	0	0
T164	901	0	0	0
T175	0	1	0	0
T217	0	1	0	0
T221	0	1	0	0
T224	0	1	0	0
T225	0	1	0	0
T226	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T19

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T6,T19
1	1	Covered	T4,T6,T19

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T2,T10

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T10
1	0	Covered	T4,T6,T19
1	1	Covered	T1,T2,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T10
0	1	Covered	T102,T226
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T10
0	1	Covered	T1,T33,T39
1	0	Covered	T55

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T10
1	-	Covered	T1,T33,T39

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T10
DetectSt	168	Covered	T1,T2,T10
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T2,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T10
DebounceSt->IdleSt	163	Covered	T75,T227,T185
DetectSt->IdleSt	186	Covered	T102,T226
DetectSt->StableSt	191	Covered	T1,T2,T10
IdleSt->DebounceSt	148	Covered	T1,T2,T10
StableSt->IdleSt	206	Covered	T1,T33,T39

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T10
0	1	Covered	T1,T2,T10
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T10
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T10
IdleSt	0	-	-	-	-	-	-	Covered	T4,T6,T19
DebounceSt	-	1	-	-	-	-	-	Covered	T75
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T227,T185,T148
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T10
DetectSt	-	-	-	-	1	-	-	Covered	T102,T226
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T10
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T33,T39
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9721734	144	0	0
CntIncr_A	9721734	59514	0	0
CntNoWrap_A	9721734	9034751	0	0
DetectStDropOut_A	9721734	2	0	0
DetectedOut_A	9721734	6232	0	0
DetectedPulseOut_A	9721734	68	0	0
DisabledIdleSt_A	9721734	8838080	0	0
DisabledNoDetection_A	9721734	8840520	0	0
EnterDebounceSt_A	9721734	74	0	0
EnterDetectSt_A	9721734	70	0	0
EnterStableSt_A	9721734	68	0	0
PulseIsPulse_A	9721734	68	0	0
StayInStableSt	9721734	6130	0	0
gen_high_level_sva.HighLevelEvent_A	9721734	9037396	0	0
gen_not_sticky_sva.StableStDropOut_A	9721734	33	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	144	0	0
T1	17410	8	0	0
T2	525	2	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T10	0	2	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T33	0	6	0	0
T35	0	2	0	0
T39	0	4	0	0
T41	0	2	0	0
T75	0	1	0	0
T95	0	6	0	0
T190	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	59514	0	0
T1	17410	207	0	0
T2	525	33	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T10	0	30	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T33	0	204	0	0
T35	0	97	0	0
T39	0	168	0	0
T41	0	12	0	0
T75	0	43	0	0
T95	0	54	0	0
T190	0	28	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	9034751	0	0
T1	17410	9041	0	0
T2	525	122	0	0
T4	9352	6128	0	0
T5	407	6	0	0
T6	500	99	0	0
T14	402	1	0	0
T15	405	4	0	0
T16	408	7	0	0
T19	521	120	0	0
T20	642	241	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	2	0	0
T102	204888	1	0	0
T104	1162	0	0	0
T226	0	1	0	0
T228	426	0	0	0
T229	431	0	0	0
T230	20704	0	0	0
T231	507	0	0	0
T232	426	0	0	0
T233	526	0	0	0
T234	507	0	0	0
T235	402	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	6232	0	0
T1	17410	213	0	0
T2	525	83	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T10	0	98	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T33	0	155	0	0
T35	0	139	0	0
T39	0	84	0	0
T41	0	106	0	0
T95	0	121	0	0
T96	0	172	0	0
T190	0	97	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	68	0	0
T1	17410	4	0	0
T2	525	1	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T10	0	1	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T33	0	3	0	0
T35	0	1	0	0
T39	0	2	0	0
T41	0	1	0	0
T95	0	3	0	0
T96	0	2	0	0
T190	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	8838080	0	0
T1	17410	8150	0	0
T2	525	3	0	0
T4	9352	6128	0	0
T5	407	6	0	0
T6	500	99	0	0
T14	402	1	0	0
T15	405	4	0	0
T16	408	7	0	0
T19	521	120	0	0
T20	642	241	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	8840520	0	0
T1	17410	8171	0	0
T2	525	3	0	0
T4	9352	6138	0	0
T5	407	7	0	0
T6	500	100	0	0
T14	402	2	0	0
T15	405	5	0	0
T16	408	8	0	0
T19	521	121	0	0
T20	642	242	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	74	0	0
T1	17410	4	0	0
T2	525	1	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T10	0	1	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T33	0	3	0	0
T35	0	1	0	0
T39	0	2	0	0
T41	0	1	0	0
T75	0	1	0	0
T95	0	3	0	0
T190	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	70	0	0
T1	17410	4	0	0
T2	525	1	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T10	0	1	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T33	0	3	0	0
T35	0	1	0	0
T39	0	2	0	0
T41	0	1	0	0
T95	0	3	0	0
T96	0	2	0	0
T190	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	68	0	0
T1	17410	4	0	0
T2	525	1	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T10	0	1	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T33	0	3	0	0
T35	0	1	0	0
T39	0	2	0	0
T41	0	1	0	0
T95	0	3	0	0
T96	0	2	0	0
T190	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	68	0	0
T1	17410	4	0	0
T2	525	1	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T10	0	1	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T33	0	3	0	0
T35	0	1	0	0
T39	0	2	0	0
T41	0	1	0	0
T95	0	3	0	0
T96	0	2	0	0
T190	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	6130	0	0
T1	17410	207	0	0
T2	525	81	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T10	0	96	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T33	0	151	0	0
T35	0	137	0	0
T39	0	81	0	0
T41	0	104	0	0
T95	0	117	0	0
T96	0	169	0	0
T190	0	94	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	9037396	0	0
T1	17410	9073	0	0
T2	525	125	0	0
T4	9352	6138	0	0
T5	407	7	0	0
T6	500	100	0	0
T14	402	2	0	0
T15	405	5	0	0
T16	408	8	0	0
T19	521	121	0	0
T20	642	242	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	33	0	0
T1	17410	2	0	0
T2	525	0	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T33	0	2	0	0
T39	0	1	0	0
T95	0	2	0	0
T96	0	1	0	0
T110	0	1	0	0
T137	0	2	0	0
T155	0	1	0	0
T178	0	2	0	0
T190	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T6,T19
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T19
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T33,T75

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T33,T75

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T33,T34

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T10
1	0	Covered	T4,T6,T19
1	1	Covered	T1,T33,T75

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T33,T34
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T33,T34
0	1	Covered	T1,T33,T190
1	0	Covered	T55

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T33,T34
1	-	Covered	T1,T33,T190

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T33,T75
DetectSt	168	Covered	T1,T33,T34
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T33,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T33,T34
DebounceSt->IdleSt	163	Covered	T75,T147,T178
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T1,T33,T34
IdleSt->DebounceSt	148	Covered	T1,T33,T75
StableSt->IdleSt	206	Covered	T1,T33,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T33,T75
0	1	Covered	T1,T33,T75
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T33,T34
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T33,T75
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T75
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T33,T34
DebounceSt	-	0	1	0	-	-	-	Covered	T147,T178,T199
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T33,T75
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T1,T33,T34
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T33,T190
StableSt	-	-	-	-	-	-	0	Covered	T1,T33,T34
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9721734	71	0	0
CntIncr_A	9721734	37250	0	0
CntNoWrap_A	9721734	9034824	0	0
DetectStDropOut_A	9721734	0	0	0
DetectedOut_A	9721734	61507	0	0
DetectedPulseOut_A	9721734	33	0	0
DisabledIdleSt_A	9721734	8883890	0	0
DisabledNoDetection_A	9721734	8886342	0	0
EnterDebounceSt_A	9721734	38	0	0
EnterDetectSt_A	9721734	33	0	0
EnterStableSt_A	9721734	33	0	0
PulseIsPulse_A	9721734	33	0	0
StayInStableSt	9721734	61459	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9721734	7273	0	0
gen_low_level_sva.LowLevelEvent_A	9721734	9037396	0	0
gen_not_sticky_sva.StableStDropOut_A	9721734	17	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	71	0	0
T1	17410	4	0	0
T2	525	0	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T33	0	4	0	0
T34	0	2	0	0
T75	0	1	0	0
T96	0	2	0	0
T110	0	2	0	0
T147	0	3	0	0
T178	0	3	0	0
T181	0	4	0	0
T190	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	37250	0	0
T1	17410	128	0	0
T2	525	0	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T33	0	136	0	0
T34	0	21	0	0
T75	0	45	0	0
T96	0	37	0	0
T110	0	35222	0	0
T147	0	46	0	0
T178	0	180	0	0
T181	0	164	0	0
T190	0	14	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	9034824	0	0
T1	17410	9045	0	0
T2	525	124	0	0
T4	9352	6128	0	0
T5	407	6	0	0
T6	500	99	0	0
T14	402	1	0	0
T15	405	4	0	0
T16	408	7	0	0
T19	521	120	0	0
T20	642	241	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	61507	0	0
T1	17410	80	0	0
T2	525	0	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T33	0	86	0	0
T34	0	124	0	0
T96	0	112	0	0
T110	0	59143	0	0
T137	0	181	0	0
T147	0	12	0	0
T178	0	64	0	0
T181	0	80	0	0
T190	0	7	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	33	0	0
T1	17410	2	0	0
T2	525	0	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T33	0	2	0	0
T34	0	1	0	0
T96	0	1	0	0
T110	0	1	0	0
T137	0	2	0	0
T147	0	1	0	0
T178	0	1	0	0
T181	0	2	0	0
T190	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	8883890	0	0
T1	17410	8244	0	0
T2	525	3	0	0
T4	9352	6128	0	0
T5	407	6	0	0
T6	500	99	0	0
T14	402	1	0	0
T15	405	4	0	0
T16	408	7	0	0
T19	521	120	0	0
T20	642	241	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	8886342	0	0
T1	17410	8266	0	0
T2	525	3	0	0
T4	9352	6138	0	0
T5	407	7	0	0
T6	500	100	0	0
T14	402	2	0	0
T15	405	5	0	0
T16	408	8	0	0
T19	521	121	0	0
T20	642	242	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	38	0	0
T1	17410	2	0	0
T2	525	0	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T33	0	2	0	0
T34	0	1	0	0
T75	0	1	0	0
T96	0	1	0	0
T110	0	1	0	0
T147	0	2	0	0
T178	0	2	0	0
T181	0	2	0	0
T190	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	33	0	0
T1	17410	2	0	0
T2	525	0	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T33	0	2	0	0
T34	0	1	0	0
T96	0	1	0	0
T110	0	1	0	0
T137	0	2	0	0
T147	0	1	0	0
T178	0	1	0	0
T181	0	2	0	0
T190	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	33	0	0
T1	17410	2	0	0
T2	525	0	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T33	0	2	0	0
T34	0	1	0	0
T96	0	1	0	0
T110	0	1	0	0
T137	0	2	0	0
T147	0	1	0	0
T178	0	1	0	0
T181	0	2	0	0
T190	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	33	0	0
T1	17410	2	0	0
T2	525	0	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T33	0	2	0	0
T34	0	1	0	0
T96	0	1	0	0
T110	0	1	0	0
T137	0	2	0	0
T147	0	1	0	0
T178	0	1	0	0
T181	0	2	0	0
T190	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	61459	0	0
T1	17410	77	0	0
T2	525	0	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T33	0	84	0	0
T34	0	122	0	0
T96	0	111	0	0
T110	0	59141	0	0
T137	0	178	0	0
T147	0	11	0	0
T178	0	63	0	0
T181	0	77	0	0
T190	0	6	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	7273	0	0
T1	17410	31	0	0
T2	525	0	0	0
T3	0	53	0	0
T4	9352	14	0	0
T5	407	0	0	0
T6	500	8	0	0
T7	0	10	0	0
T8	0	31	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	0	5	0	0
T18	0	3	0	0
T19	521	4	0	0
T20	642	0	0	0
T52	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	9037396	0	0
T1	17410	9073	0	0
T2	525	125	0	0
T4	9352	6138	0	0
T5	407	7	0	0
T6	500	100	0	0
T14	402	2	0	0
T15	405	5	0	0
T16	408	8	0	0
T19	521	121	0	0
T20	642	242	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	17	0	0
T1	17410	1	0	0
T2	525	0	0	0
T3	41713	0	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T33	0	2	0	0
T96	0	1	0	0
T137	0	1	0	0
T147	0	1	0	0
T175	0	1	0	0
T178	0	1	0	0
T181	0	1	0	0
T190	0	1	0	0
T236	0	1	0	0