Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T8,T13,T26
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T13,T26

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T13,T26

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T13,T26

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T13,T26
1	0	Covered	T8,T13,T26
1	1	Covered	T8,T13,T26

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T13,T26
0	1	Covered	T46,T30,T32
1	0	Covered	T30,T32,T106

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T13,T26
0	1	Covered	T8,T13,T26
1	0	Covered	T30

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T13,T26
1	-	Covered	T8,T13,T26

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T13,T26
DetectSt	168	Covered	T8,T13,T26
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T8,T13,T26

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T13,T26
DebounceSt->IdleSt	163	Covered	T48,T72,T75
DetectSt->IdleSt	186	Covered	T46,T30,T32
DetectSt->StableSt	191	Covered	T8,T13,T26
IdleSt->DebounceSt	148	Covered	T8,T13,T26
StableSt->IdleSt	206	Covered	T8,T13,T26

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T8,T13,T26
0	1	Covered	T8,T13,T26
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T13,T26
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T8,T13,T26
IdleSt	0	-	-	-	-	-	-	Covered	T8,T13,T26
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T55
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T13,T26
DebounceSt	-	0	1	0	-	-	-	Covered	T48,T72,T75
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T13,T26
DetectSt	-	-	-	-	1	-	-	Covered	T46,T30,T32
DetectSt	-	-	-	-	0	1	-	Covered	T8,T13,T26
DetectSt	-	-	-	-	0	0	-	Covered	T8,T13,T26
StableSt	-	-	-	-	-	-	1	Covered	T8,T13,T26
StableSt	-	-	-	-	-	-	0	Covered	T8,T13,T26
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9721734	3035	0	0
CntIncr_A	9721734	105439	0	0
CntNoWrap_A	9721734	9031860	0	0
DetectStDropOut_A	9721734	533	0	0
DetectedOut_A	9721734	67131	0	0
DetectedPulseOut_A	9721734	716	0	0
DisabledIdleSt_A	9721734	8601221	0	0
DisabledNoDetection_A	9721734	8603546	0	0
EnterDebounceSt_A	9721734	1559	0	0
EnterDetectSt_A	9721734	1478	0	0
EnterStableSt_A	9721734	716	0	0
PulseIsPulse_A	9721734	716	0	0
StayInStableSt	9721734	66329	0	0
gen_high_event_sva.HighLevelEvent_A	9721734	9037396	0	0
gen_high_level_sva.HighLevelEvent_A	9721734	9037396	0	0
gen_not_sticky_sva.StableStDropOut_A	9721734	629	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	3035	0	0
T8	27383	56	0	0
T9	23901	0	0	0
T10	664	0	0	0
T13	0	30	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T26	0	26	0	0
T30	0	30	0	0
T32	0	58	0	0
T42	0	52	0	0
T46	0	66	0	0
T48	0	33	0	0
T49	0	54	0	0
T52	522	0	0	0
T53	506	0	0	0
T54	522	0	0	0
T57	607	0	0	0
T72	0	34	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	105439	0	0
T8	27383	1988	0	0
T9	23901	0	0	0
T10	664	0	0	0
T13	0	840	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T26	0	2132	0	0
T30	0	853	0	0
T32	0	1752	0	0
T42	0	2080	0	0
T46	0	2540	0	0
T48	0	1225	0	0
T49	0	1755	0	0
T52	522	0	0	0
T53	506	0	0	0
T54	522	0	0	0
T57	607	0	0	0
T72	0	6462	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	9031860	0	0
T1	17410	9049	0	0
T2	525	124	0	0
T4	9352	6128	0	0
T5	407	6	0	0
T6	500	99	0	0
T14	402	1	0	0
T15	405	4	0	0
T16	408	7	0	0
T19	521	120	0	0
T20	642	241	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	533	0	0
T30	0	9	0	0
T32	0	14	0	0
T46	6466	33	0	0
T48	0	8	0	0
T49	0	27	0	0
T56	776274	0	0	0
T58	312572	0	0	0
T64	2468	0	0	0
T65	492	0	0	0
T75	0	1	0	0
T106	0	5	0	0
T107	0	10	0	0
T108	0	10	0	0
T116	503	0	0	0
T117	559	0	0	0
T118	536	0	0	0
T119	521	0	0	0
T120	421	0	0	0
T237	0	12	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	67131	0	0
T8	27383	3153	0	0
T9	23901	0	0	0
T10	664	0	0	0
T13	0	2096	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T26	0	3140	0	0
T30	0	1	0	0
T42	0	3470	0	0
T52	522	0	0	0
T53	506	0	0	0
T54	522	0	0	0
T57	607	0	0	0
T72	0	726	0	0
T75	0	402	0	0
T121	0	913	0	0
T122	0	93	0	0
T214	0	2404	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	716	0	0
T8	27383	28	0	0
T9	23901	0	0	0
T10	664	0	0	0
T13	0	15	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T26	0	13	0	0
T30	0	1	0	0
T42	0	26	0	0
T52	522	0	0	0
T53	506	0	0	0
T54	522	0	0	0
T57	607	0	0	0
T72	0	14	0	0
T75	0	5	0	0
T121	0	10	0	0
T122	0	8	0	0
T214	0	28	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	8601221	0	0
T1	17410	9049	0	0
T2	525	124	0	0
T4	9352	6128	0	0
T5	407	6	0	0
T6	500	99	0	0
T14	402	1	0	0
T15	405	4	0	0
T16	408	7	0	0
T19	521	120	0	0
T20	642	241	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	8603546	0	0
T1	17410	9073	0	0
T2	525	125	0	0
T4	9352	6138	0	0
T5	407	7	0	0
T6	500	100	0	0
T14	402	2	0	0
T15	405	5	0	0
T16	408	8	0	0
T19	521	121	0	0
T20	642	242	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	1559	0	0
T8	27383	28	0	0
T9	23901	0	0	0
T10	664	0	0	0
T13	0	15	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T26	0	13	0	0
T30	0	15	0	0
T32	0	29	0	0
T42	0	26	0	0
T46	0	33	0	0
T48	0	25	0	0
T49	0	27	0	0
T52	522	0	0	0
T53	506	0	0	0
T54	522	0	0	0
T57	607	0	0	0
T72	0	20	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	1478	0	0
T8	27383	28	0	0
T9	23901	0	0	0
T10	664	0	0	0
T13	0	15	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T26	0	13	0	0
T30	0	15	0	0
T32	0	29	0	0
T42	0	26	0	0
T46	0	33	0	0
T48	0	8	0	0
T49	0	27	0	0
T52	522	0	0	0
T53	506	0	0	0
T54	522	0	0	0
T57	607	0	0	0
T72	0	14	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	716	0	0
T8	27383	28	0	0
T9	23901	0	0	0
T10	664	0	0	0
T13	0	15	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T26	0	13	0	0
T30	0	1	0	0
T42	0	26	0	0
T52	522	0	0	0
T53	506	0	0	0
T54	522	0	0	0
T57	607	0	0	0
T72	0	14	0	0
T75	0	5	0	0
T121	0	10	0	0
T122	0	8	0	0
T214	0	28	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	716	0	0
T8	27383	28	0	0
T9	23901	0	0	0
T10	664	0	0	0
T13	0	15	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T26	0	13	0	0
T30	0	1	0	0
T42	0	26	0	0
T52	522	0	0	0
T53	506	0	0	0
T54	522	0	0	0
T57	607	0	0	0
T72	0	14	0	0
T75	0	5	0	0
T121	0	10	0	0
T122	0	8	0	0
T214	0	28	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	66329	0	0
T8	27383	3119	0	0
T9	23901	0	0	0
T10	664	0	0	0
T13	0	2078	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T26	0	3125	0	0
T42	0	3437	0	0
T52	522	0	0	0
T53	506	0	0	0
T54	522	0	0	0
T57	607	0	0	0
T72	0	712	0	0
T75	0	397	0	0
T121	0	903	0	0
T122	0	85	0	0
T203	0	212	0	0
T214	0	2374	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	9037396	0	0
T1	17410	9073	0	0
T2	525	125	0	0
T4	9352	6138	0	0
T5	407	7	0	0
T6	500	100	0	0
T14	402	2	0	0
T15	405	5	0	0
T16	408	8	0	0
T19	521	121	0	0
T20	642	242	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	9037396	0	0
T1	17410	9073	0	0
T2	525	125	0	0
T4	9352	6138	0	0
T5	407	7	0	0
T6	500	100	0	0
T14	402	2	0	0
T15	405	5	0	0
T16	408	8	0	0
T19	521	121	0	0
T20	642	242	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	629	0	0
T8	27383	22	0	0
T9	23901	0	0	0
T10	664	0	0	0
T13	0	12	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T26	0	11	0	0
T42	0	19	0	0
T52	522	0	0	0
T53	506	0	0	0
T54	522	0	0	0
T57	607	0	0	0
T72	0	14	0	0
T75	0	5	0	0
T121	0	10	0	0
T122	0	8	0	0
T203	0	1	0	0
T214	0	26	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T3
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T1,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T4,T1,T3

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T3,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T3
1	0	Covered	T4,T1,T3
1	1	Covered	T4,T1,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T8
0	1	Covered	T3,T33,T109
1	0	Covered	T75,T55

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T8
0	1	Covered	T1,T3,T8
1	0	Covered	T55

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T3,T8
1	-	Covered	T1,T3,T8

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T1,T3
DetectSt	168	Covered	T1,T3,T8
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T3,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T3,T8
DebounceSt->IdleSt	163	Covered	T4,T1,T64
DetectSt->IdleSt	186	Covered	T3,T33,T75
DetectSt->StableSt	191	Covered	T1,T3,T8
IdleSt->DebounceSt	148	Covered	T4,T1,T3
StableSt->IdleSt	206	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T1,T3
0	1	Covered	T4,T1,T3
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T8
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T1,T3
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T55
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T3,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T4,T1,T64
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T1,T3
DetectSt	-	-	-	-	1	-	-	Covered	T3,T33,T75
DetectSt	-	-	-	-	0	1	-	Covered	T1,T3,T8
DetectSt	-	-	-	-	0	0	-	Covered	T1,T3,T8
StableSt	-	-	-	-	-	-	1	Covered	T1,T3,T8
StableSt	-	-	-	-	-	-	0	Covered	T1,T3,T8
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9721734	1010	0	0
CntIncr_A	9721734	55736	0	0
CntNoWrap_A	9721734	9033885	0	0
DetectStDropOut_A	9721734	40	0	0
DetectedOut_A	9721734	19236	0	0
DetectedPulseOut_A	9721734	419	0	0
DisabledIdleSt_A	9721734	8599687	0	0
DisabledNoDetection_A	9721734	8601402	0	0
EnterDebounceSt_A	9721734	547	0	0
EnterDetectSt_A	9721734	465	0	0
EnterStableSt_A	9721734	419	0	0
PulseIsPulse_A	9721734	419	0	0
StayInStableSt	9721734	18797	0	0
gen_high_level_sva.HighLevelEvent_A	9721734	9037396	0	0
gen_not_sticky_sva.StableStDropOut_A	9721734	394	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	1010	0	0
T1	17410	4	0	0
T2	525	0	0	0
T3	0	8	0	0
T4	9352	1	0	0
T5	407	0	0	0
T6	500	0	0	0
T8	0	8	0	0
T9	0	6	0	0
T11	0	4	0	0
T13	0	6	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T19	521	0	0	0
T20	642	0	0	0
T26	0	4	0	0
T45	0	6	0	0
T64	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	55736	0	0
T1	17410	183	0	0
T2	525	0	0	0
T3	0	402	0	0
T4	9352	20	0	0
T5	407	0	0	0
T6	500	0	0	0
T8	0	304	0	0
T9	0	447	0	0
T11	0	206	0	0
T13	0	162	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T19	521	0	0	0
T20	642	0	0	0
T26	0	316	0	0
T45	0	399	0	0
T64	0	20	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	9033885	0	0
T1	17410	9045	0	0
T2	525	124	0	0
T4	9352	6127	0	0
T5	407	6	0	0
T6	500	99	0	0
T14	402	1	0	0
T15	405	4	0	0
T16	408	7	0	0
T19	521	120	0	0
T20	642	241	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	40	0	0
T3	41713	2	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T9	23901	0	0	0
T10	664	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T33	0	4	0	0
T52	522	0	0	0
T53	506	0	0	0
T84	0	1	0	0
T95	0	4	0	0
T109	0	1	0	0
T110	0	3	0	0
T111	0	8	0	0
T112	0	2	0	0
T113	0	2	0	0
T115	0	13	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	19236	0	0
T1	17410	49	0	0
T2	525	0	0	0
T3	41713	64	0	0
T7	1548	0	0	0
T8	27383	361	0	0
T9	0	136	0	0
T11	0	162	0	0
T13	0	455	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T26	0	162	0	0
T40	0	3	0	0
T42	0	905	0	0
T45	0	276	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	419	0	0
T1	17410	1	0	0
T2	525	0	0	0
T3	41713	2	0	0
T7	1548	0	0	0
T8	27383	4	0	0
T9	0	3	0	0
T11	0	2	0	0
T13	0	3	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T26	0	2	0	0
T40	0	1	0	0
T42	0	7	0	0
T45	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	8599687	0	0
T1	17410	7963	0	0
T2	525	124	0	0
T4	9352	6087	0	0
T5	407	6	0	0
T6	500	99	0	0
T14	402	1	0	0
T15	405	4	0	0
T16	408	7	0	0
T19	521	120	0	0
T20	642	241	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	8601402	0	0
T1	17410	7983	0	0
T2	525	125	0	0
T4	9352	6096	0	0
T5	407	7	0	0
T6	500	100	0	0
T14	402	2	0	0
T15	405	5	0	0
T16	408	8	0	0
T19	521	121	0	0
T20	642	242	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	547	0	0
T1	17410	3	0	0
T2	525	0	0	0
T3	0	4	0	0
T4	9352	1	0	0
T5	407	0	0	0
T6	500	0	0	0
T8	0	4	0	0
T9	0	3	0	0
T11	0	2	0	0
T13	0	3	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T19	521	0	0	0
T20	642	0	0	0
T26	0	2	0	0
T45	0	3	0	0
T64	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	465	0	0
T1	17410	1	0	0
T2	525	0	0	0
T3	41713	4	0	0
T7	1548	0	0	0
T8	27383	4	0	0
T9	0	3	0	0
T11	0	2	0	0
T13	0	3	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T26	0	2	0	0
T40	0	1	0	0
T42	0	7	0	0
T45	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	419	0	0
T1	17410	1	0	0
T2	525	0	0	0
T3	41713	2	0	0
T7	1548	0	0	0
T8	27383	4	0	0
T9	0	3	0	0
T11	0	2	0	0
T13	0	3	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T26	0	2	0	0
T40	0	1	0	0
T42	0	7	0	0
T45	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	419	0	0
T1	17410	1	0	0
T2	525	0	0	0
T3	41713	2	0	0
T7	1548	0	0	0
T8	27383	4	0	0
T9	0	3	0	0
T11	0	2	0	0
T13	0	3	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T26	0	2	0	0
T40	0	1	0	0
T42	0	7	0	0
T45	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	18797	0	0
T1	17410	48	0	0
T2	525	0	0	0
T3	41713	62	0	0
T7	1548	0	0	0
T8	27383	357	0	0
T9	0	133	0	0
T11	0	160	0	0
T13	0	450	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T26	0	158	0	0
T40	0	2	0	0
T42	0	898	0	0
T45	0	273	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	9037396	0	0
T1	17410	9073	0	0
T2	525	125	0	0
T4	9352	6138	0	0
T5	407	7	0	0
T6	500	100	0	0
T14	402	2	0	0
T15	405	5	0	0
T16	408	8	0	0
T19	521	121	0	0
T20	642	242	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	394	0	0
T1	17410	1	0	0
T2	525	0	0	0
T3	41713	2	0	0
T7	1548	0	0	0
T8	27383	4	0	0
T9	0	3	0	0
T11	0	2	0	0
T13	0	1	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T31	0	1	0	0
T40	0	1	0	0
T42	0	7	0	0
T45	0	3	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T8,T13,T26
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T13,T26

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T13,T26

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T13,T26

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T13,T26
1	0	Covered	T8,T13,T26
1	1	Covered	T8,T13,T26

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T13,T26
0	1	Covered	T46,T32,T48
1	0	Covered	T13,T32,T42

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T26,T30
0	1	Covered	T8,T26,T30
1	0	Covered	T98

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T26,T30
1	-	Covered	T8,T26,T30

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T13,T26
DetectSt	168	Covered	T8,T13,T26
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T8,T26,T30

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T13,T26
DebounceSt->IdleSt	163	Covered	T48,T72,T75
DetectSt->IdleSt	186	Covered	T13,T46,T32
DetectSt->StableSt	191	Covered	T8,T26,T30
IdleSt->DebounceSt	148	Covered	T8,T13,T26
StableSt->IdleSt	206	Covered	T8,T26,T30

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T8,T13,T26
0	1	Covered	T8,T13,T26
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T13,T26
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T8,T13,T26
IdleSt	0	-	-	-	-	-	-	Covered	T8,T13,T26
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T55
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T13,T26
DebounceSt	-	0	1	0	-	-	-	Covered	T48,T72,T75
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T13,T26
DetectSt	-	-	-	-	1	-	-	Covered	T13,T46,T32
DetectSt	-	-	-	-	0	1	-	Covered	T8,T26,T30
DetectSt	-	-	-	-	0	0	-	Covered	T8,T13,T26
StableSt	-	-	-	-	-	-	1	Covered	T8,T26,T30
StableSt	-	-	-	-	-	-	0	Covered	T8,T26,T30
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9721734	2921	0	0
CntIncr_A	9721734	101650	0	0
CntNoWrap_A	9721734	9031974	0	0
DetectStDropOut_A	9721734	396	0	0
DetectedOut_A	9721734	79685	0	0
DetectedPulseOut_A	9721734	820	0	0
DisabledIdleSt_A	9721734	8592465	0	0
DisabledNoDetection_A	9721734	8594778	0	0
EnterDebounceSt_A	9721734	1510	0	0
EnterDetectSt_A	9721734	1412	0	0
EnterStableSt_A	9721734	820	0	0
PulseIsPulse_A	9721734	820	0	0
StayInStableSt	9721734	78768	0	0
gen_high_event_sva.HighLevelEvent_A	9721734	9037396	0	0
gen_high_level_sva.HighLevelEvent_A	9721734	9037396	0	0
gen_not_sticky_sva.StableStDropOut_A	9721734	717	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	2921	0	0
T8	27383	24	0	0
T9	23901	0	0	0
T10	664	0	0	0
T13	0	14	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T26	0	10	0	0
T30	0	22	0	0
T32	0	58	0	0
T42	0	10	0	0
T46	0	22	0	0
T48	0	36	0	0
T49	0	54	0	0
T52	522	0	0	0
T53	506	0	0	0
T54	522	0	0	0
T57	607	0	0	0
T72	0	28	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	101650	0	0
T8	27383	876	0	0
T9	23901	0	0	0
T10	664	0	0	0
T13	0	472	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T26	0	790	0	0
T30	0	616	0	0
T32	0	1752	0	0
T42	0	470	0	0
T46	0	842	0	0
T48	0	1470	0	0
T49	0	1755	0	0
T52	522	0	0	0
T53	506	0	0	0
T54	522	0	0	0
T57	607	0	0	0
T72	0	5376	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	9031974	0	0
T1	17410	9049	0	0
T2	525	124	0	0
T4	9352	6128	0	0
T5	407	6	0	0
T6	500	99	0	0
T14	402	1	0	0
T15	405	4	0	0
T16	408	7	0	0
T19	521	120	0	0
T20	642	241	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	396	0	0
T32	0	14	0	0
T46	6466	11	0	0
T48	0	6	0	0
T49	0	27	0	0
T56	776274	0	0	0
T58	312572	0	0	0
T64	2468	0	0	0
T65	492	0	0	0
T75	0	1	0	0
T106	0	14	0	0
T107	0	24	0	0
T108	0	10	0	0
T116	503	0	0	0
T117	559	0	0	0
T118	536	0	0	0
T119	521	0	0	0
T120	421	0	0	0
T238	0	2	0	0
T239	0	5	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	79685	0	0
T8	27383	1629	0	0
T9	23901	0	0	0
T10	664	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T26	0	545	0	0
T30	0	1550	0	0
T52	522	0	0	0
T53	506	0	0	0
T54	522	0	0	0
T57	607	0	0	0
T72	0	845	0	0
T75	0	432	0	0
T121	0	2660	0	0
T122	0	696	0	0
T203	0	646	0	0
T214	0	1777	0	0
T240	0	1183	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	820	0	0
T8	27383	12	0	0
T9	23901	0	0	0
T10	664	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T26	0	5	0	0
T30	0	11	0	0
T52	522	0	0	0
T53	506	0	0	0
T54	522	0	0	0
T57	607	0	0	0
T72	0	11	0	0
T75	0	5	0	0
T121	0	22	0	0
T122	0	26	0	0
T203	0	6	0	0
T214	0	31	0	0
T240	0	16	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	8592465	0	0
T1	17410	9049	0	0
T2	525	124	0	0
T4	9352	6128	0	0
T5	407	6	0	0
T6	500	99	0	0
T14	402	1	0	0
T15	405	4	0	0
T16	408	7	0	0
T19	521	120	0	0
T20	642	241	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	8594778	0	0
T1	17410	9073	0	0
T2	525	125	0	0
T4	9352	6138	0	0
T5	407	7	0	0
T6	500	100	0	0
T14	402	2	0	0
T15	405	5	0	0
T16	408	8	0	0
T19	521	121	0	0
T20	642	242	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	1510	0	0
T8	27383	12	0	0
T9	23901	0	0	0
T10	664	0	0	0
T13	0	7	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T26	0	5	0	0
T30	0	11	0	0
T32	0	29	0	0
T42	0	5	0	0
T46	0	11	0	0
T48	0	30	0	0
T49	0	27	0	0
T52	522	0	0	0
T53	506	0	0	0
T54	522	0	0	0
T57	607	0	0	0
T72	0	18	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	1412	0	0
T8	27383	12	0	0
T9	23901	0	0	0
T10	664	0	0	0
T13	0	7	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T26	0	5	0	0
T30	0	11	0	0
T32	0	29	0	0
T42	0	5	0	0
T46	0	11	0	0
T48	0	6	0	0
T49	0	27	0	0
T52	522	0	0	0
T53	506	0	0	0
T54	522	0	0	0
T57	607	0	0	0
T72	0	11	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	820	0	0
T8	27383	12	0	0
T9	23901	0	0	0
T10	664	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T26	0	5	0	0
T30	0	11	0	0
T52	522	0	0	0
T53	506	0	0	0
T54	522	0	0	0
T57	607	0	0	0
T72	0	11	0	0
T75	0	5	0	0
T121	0	22	0	0
T122	0	26	0	0
T203	0	6	0	0
T214	0	31	0	0
T240	0	16	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	820	0	0
T8	27383	12	0	0
T9	23901	0	0	0
T10	664	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T26	0	5	0	0
T30	0	11	0	0
T52	522	0	0	0
T53	506	0	0	0
T54	522	0	0	0
T57	607	0	0	0
T72	0	11	0	0
T75	0	5	0	0
T121	0	22	0	0
T122	0	26	0	0
T203	0	6	0	0
T214	0	31	0	0
T240	0	16	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	78768	0	0
T8	27383	1614	0	0
T9	23901	0	0	0
T10	664	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T26	0	540	0	0
T30	0	1539	0	0
T52	522	0	0	0
T53	506	0	0	0
T54	522	0	0	0
T57	607	0	0	0
T72	0	834	0	0
T75	0	427	0	0
T121	0	2635	0	0
T122	0	669	0	0
T203	0	637	0	0
T214	0	1745	0	0
T240	0	1163	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	9037396	0	0
T1	17410	9073	0	0
T2	525	125	0	0
T4	9352	6138	0	0
T5	407	7	0	0
T6	500	100	0	0
T14	402	2	0	0
T15	405	5	0	0
T16	408	8	0	0
T19	521	121	0	0
T20	642	242	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	9037396	0	0
T1	17410	9073	0	0
T2	525	125	0	0
T4	9352	6138	0	0
T5	407	7	0	0
T6	500	100	0	0
T14	402	2	0	0
T15	405	5	0	0
T16	408	8	0	0
T19	521	121	0	0
T20	642	242	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	717	0	0
T8	27383	9	0	0
T9	23901	0	0	0
T10	664	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T26	0	5	0	0
T30	0	11	0	0
T52	522	0	0	0
T53	506	0	0	0
T54	522	0	0	0
T57	607	0	0	0
T72	0	11	0	0
T75	0	5	0	0
T121	0	19	0	0
T122	0	25	0	0
T203	0	3	0	0
T214	0	30	0	0
T240	0	12	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T3,T8,T9
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T9
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T8,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T3,T8,T9

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T8,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T9
1	0	Covered	T4,T1,T3
1	1	Covered	T3,T8,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T9
0	1	Covered	T3,T93,T241
1	0	Covered	T75,T55

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T9
0	1	Covered	T3,T8,T9
1	0	Covered	T75,T94,T55

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T8,T9
1	-	Covered	T3,T8,T9

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T8,T9
DetectSt	168	Covered	T3,T8,T9
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T3,T8,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T8,T9
DebounceSt->IdleSt	163	Covered	T9,T45,T242
DetectSt->IdleSt	186	Covered	T3,T93,T75
DetectSt->StableSt	191	Covered	T3,T8,T9
IdleSt->DebounceSt	148	Covered	T3,T8,T9
StableSt->IdleSt	206	Covered	T3,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T8,T9
0	1	Covered	T3,T8,T9
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T8,T9
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T8,T9
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T55
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T8,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T9,T45,T242
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T8,T9
DetectSt	-	-	-	-	1	-	-	Covered	T3,T93,T75
DetectSt	-	-	-	-	0	1	-	Covered	T3,T8,T9
DetectSt	-	-	-	-	0	0	-	Covered	T3,T8,T9
StableSt	-	-	-	-	-	-	1	Covered	T3,T8,T9
StableSt	-	-	-	-	-	-	0	Covered	T3,T8,T9
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9721734	951	0	0
CntIncr_A	9721734	53622	0	0
CntNoWrap_A	9721734	9033944	0	0
DetectStDropOut_A	9721734	49	0	0
DetectedOut_A	9721734	20016	0	0
DetectedPulseOut_A	9721734	390	0	0
DisabledIdleSt_A	9721734	8597653	0	0
DisabledNoDetection_A	9721734	8599425	0	0
EnterDebounceSt_A	9721734	508	0	0
EnterDetectSt_A	9721734	444	0	0
EnterStableSt_A	9721734	390	0	0
PulseIsPulse_A	9721734	390	0	0
StayInStableSt	9721734	19600	0	0
gen_high_level_sva.HighLevelEvent_A	9721734	9037396	0	0
gen_not_sticky_sva.StableStDropOut_A	9721734	359	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	951	0	0
T3	41713	23	0	0
T7	1548	0	0	0
T8	27383	6	0	0
T9	23901	15	0	0
T10	664	0	0	0
T11	0	2	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T30	0	8	0	0
T31	0	10	0	0
T33	0	10	0	0
T45	0	19	0	0
T52	522	0	0	0
T53	506	0	0	0
T93	0	4	0	0
T123	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	53622	0	0
T3	41713	1003	0	0
T7	1548	0	0	0
T8	27383	219	0	0
T9	23901	1391	0	0
T10	664	0	0	0
T11	0	124	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T30	0	304	0	0
T31	0	905	0	0
T33	0	640	0	0
T45	0	1380	0	0
T52	522	0	0	0
T53	506	0	0	0
T93	0	370	0	0
T123	0	321	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	9033944	0	0
T1	17410	9049	0	0
T2	525	124	0	0
T4	9352	6128	0	0
T5	407	6	0	0
T6	500	99	0	0
T14	402	1	0	0
T15	405	4	0	0
T16	408	7	0	0
T19	521	120	0	0
T20	642	241	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	49	0	0
T3	41713	6	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T9	23901	0	0	0
T10	664	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T52	522	0	0	0
T53	506	0	0	0
T93	0	2	0	0
T110	0	3	0	0
T241	0	6	0	0
T243	0	1	0	0
T244	0	2	0	0
T245	0	10	0	0
T246	0	1	0	0
T247	0	1	0	0
T248	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	20016	0	0
T3	41713	132	0	0
T7	1548	0	0	0
T8	27383	278	0	0
T9	23901	69	0	0
T10	664	0	0	0
T11	0	60	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T30	0	276	0	0
T31	0	29	0	0
T33	0	206	0	0
T45	0	747	0	0
T52	522	0	0	0
T53	506	0	0	0
T123	0	12	0	0
T242	0	582	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	390	0	0
T3	41713	5	0	0
T7	1548	0	0	0
T8	27383	3	0	0
T9	23901	7	0	0
T10	664	0	0	0
T11	0	1	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T30	0	4	0	0
T31	0	5	0	0
T33	0	5	0	0
T45	0	9	0	0
T52	522	0	0	0
T53	506	0	0	0
T123	0	3	0	0
T242	0	10	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	8597653	0	0
T1	17410	9049	0	0
T2	525	124	0	0
T4	9352	6128	0	0
T5	407	6	0	0
T6	500	99	0	0
T14	402	1	0	0
T15	405	4	0	0
T16	408	7	0	0
T19	521	120	0	0
T20	642	241	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	8599425	0	0
T1	17410	9073	0	0
T2	525	125	0	0
T4	9352	6138	0	0
T5	407	7	0	0
T6	500	100	0	0
T14	402	2	0	0
T15	405	5	0	0
T16	408	8	0	0
T19	521	121	0	0
T20	642	242	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	508	0	0
T3	41713	12	0	0
T7	1548	0	0	0
T8	27383	3	0	0
T9	23901	8	0	0
T10	664	0	0	0
T11	0	1	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T30	0	4	0	0
T31	0	5	0	0
T33	0	5	0	0
T45	0	10	0	0
T52	522	0	0	0
T53	506	0	0	0
T93	0	2	0	0
T123	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	444	0	0
T3	41713	12	0	0
T7	1548	0	0	0
T8	27383	3	0	0
T9	23901	7	0	0
T10	664	0	0	0
T11	0	1	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T30	0	4	0	0
T31	0	5	0	0
T33	0	5	0	0
T45	0	9	0	0
T52	522	0	0	0
T53	506	0	0	0
T93	0	2	0	0
T123	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	390	0	0
T3	41713	5	0	0
T7	1548	0	0	0
T8	27383	3	0	0
T9	23901	7	0	0
T10	664	0	0	0
T11	0	1	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T30	0	4	0	0
T31	0	5	0	0
T33	0	5	0	0
T45	0	9	0	0
T52	522	0	0	0
T53	506	0	0	0
T123	0	3	0	0
T242	0	10	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	390	0	0
T3	41713	5	0	0
T7	1548	0	0	0
T8	27383	3	0	0
T9	23901	7	0	0
T10	664	0	0	0
T11	0	1	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T30	0	4	0	0
T31	0	5	0	0
T33	0	5	0	0
T45	0	9	0	0
T52	522	0	0	0
T53	506	0	0	0
T123	0	3	0	0
T242	0	10	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	19600	0	0
T3	41713	127	0	0
T7	1548	0	0	0
T8	27383	273	0	0
T9	23901	62	0	0
T10	664	0	0	0
T11	0	59	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T30	0	272	0	0
T31	0	24	0	0
T33	0	201	0	0
T45	0	738	0	0
T52	522	0	0	0
T53	506	0	0	0
T123	0	9	0	0
T242	0	572	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	9037396	0	0
T1	17410	9073	0	0
T2	525	125	0	0
T4	9352	6138	0	0
T5	407	7	0	0
T6	500	100	0	0
T14	402	2	0	0
T15	405	5	0	0
T16	408	8	0	0
T19	521	121	0	0
T20	642	242	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	359	0	0
T3	41713	5	0	0
T7	1548	0	0	0
T8	27383	1	0	0
T9	23901	7	0	0
T10	664	0	0	0
T11	0	1	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T30	0	4	0	0
T31	0	5	0	0
T33	0	5	0	0
T45	0	9	0	0
T52	522	0	0	0
T53	506	0	0	0
T123	0	3	0	0
T242	0	10	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T8,T13,T26
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T13,T26

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T13,T26

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T13,T26

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T13,T26
1	0	Covered	T8,T13,T26
1	1	Covered	T8,T13,T26

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T13,T26
0	1	Covered	T26,T46,T30
1	0	Covered	T26,T30,T32

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T13,T42
0	1	Covered	T8,T13,T42
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T13,T42
1	-	Covered	T8,T13,T42

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T13,T26
DetectSt	168	Covered	T8,T13,T26
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T8,T13,T42

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T13,T26
DebounceSt->IdleSt	163	Covered	T48,T72,T75
DetectSt->IdleSt	186	Covered	T26,T46,T30
DetectSt->StableSt	191	Covered	T8,T13,T42
IdleSt->DebounceSt	148	Covered	T8,T13,T26
StableSt->IdleSt	206	Covered	T8,T13,T42

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T8,T13,T26
0	1	Covered	T8,T13,T26
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T13,T26
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T8,T13,T26
IdleSt	0	-	-	-	-	-	-	Covered	T8,T13,T26
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T55
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T13,T26
DebounceSt	-	0	1	0	-	-	-	Covered	T48,T72,T75
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T13,T26
DetectSt	-	-	-	-	1	-	-	Covered	T26,T46,T30
DetectSt	-	-	-	-	0	1	-	Covered	T8,T13,T42
DetectSt	-	-	-	-	0	0	-	Covered	T8,T13,T26
StableSt	-	-	-	-	-	-	1	Covered	T8,T13,T42
StableSt	-	-	-	-	-	-	0	Covered	T8,T13,T42
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9721734	3225	0	0
CntIncr_A	9721734	109192	0	0
CntNoWrap_A	9721734	9031670	0	0
DetectStDropOut_A	9721734	513	0	0
DetectedOut_A	9721734	69049	0	0
DetectedPulseOut_A	9721734	803	0	0
DisabledIdleSt_A	9721734	8599618	0	0
DisabledNoDetection_A	9721734	8601924	0	0
EnterDebounceSt_A	9721734	1648	0	0
EnterDetectSt_A	9721734	1580	0	0
EnterStableSt_A	9721734	803	0	0
PulseIsPulse_A	9721734	803	0	0
StayInStableSt	9721734	68141	0	0
gen_high_event_sva.HighLevelEvent_A	9721734	9037396	0	0
gen_high_level_sva.HighLevelEvent_A	9721734	9037396	0	0
gen_not_sticky_sva.StableStDropOut_A	9721734	698	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	3225	0	0
T8	27383	56	0	0
T9	23901	0	0	0
T10	664	0	0	0
T13	0	40	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T26	0	32	0	0
T30	0	16	0	0
T32	0	18	0	0
T42	0	20	0	0
T46	0	22	0	0
T48	0	7	0	0
T49	0	60	0	0
T52	522	0	0	0
T53	506	0	0	0
T54	522	0	0	0
T57	607	0	0	0
T72	0	20	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	109192	0	0
T8	27383	1876	0	0
T9	23901	0	0	0
T10	664	0	0	0
T13	0	980	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T26	0	3457	0	0
T30	0	451	0	0
T32	0	548	0	0
T42	0	880	0	0
T46	0	842	0	0
T48	0	343	0	0
T49	0	1952	0	0
T52	522	0	0	0
T53	506	0	0	0
T54	522	0	0	0
T57	607	0	0	0
T72	0	4146	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	9031670	0	0
T1	17410	9049	0	0
T2	525	124	0	0
T4	9352	6128	0	0
T5	407	6	0	0
T6	500	99	0	0
T14	402	1	0	0
T15	405	4	0	0
T16	408	7	0	0
T19	521	120	0	0
T20	642	241	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	513	0	0
T26	22699	8	0	0
T30	0	7	0	0
T46	6466	11	0	0
T49	0	30	0	0
T56	776274	0	0	0
T58	312572	0	0	0
T64	2468	0	0	0
T75	0	1	0	0
T107	0	24	0	0
T116	503	0	0	0
T117	559	0	0	0
T118	536	0	0	0
T119	521	0	0	0
T120	421	0	0	0
T237	0	21	0	0
T238	0	4	0	0
T239	0	9	0	0
T249	0	17	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	69049	0	0
T8	27383	3265	0	0
T9	23901	0	0	0
T10	664	0	0	0
T13	0	1692	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T42	0	833	0	0
T52	522	0	0	0
T53	506	0	0	0
T54	522	0	0	0
T57	607	0	0	0
T72	0	526	0	0
T75	0	436	0	0
T106	0	1789	0	0
T108	0	2087	0	0
T121	0	436	0	0
T122	0	1164	0	0
T214	0	805	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	803	0	0
T8	27383	28	0	0
T9	23901	0	0	0
T10	664	0	0	0
T13	0	20	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T42	0	10	0	0
T52	522	0	0	0
T53	506	0	0	0
T54	522	0	0	0
T57	607	0	0	0
T72	0	7	0	0
T75	0	5	0	0
T106	0	27	0	0
T108	0	23	0	0
T121	0	9	0	0
T122	0	12	0	0
T214	0	18	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	8599618	0	0
T1	17410	9049	0	0
T2	525	124	0	0
T4	9352	6128	0	0
T5	407	6	0	0
T6	500	99	0	0
T14	402	1	0	0
T15	405	4	0	0
T16	408	7	0	0
T19	521	120	0	0
T20	642	241	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	8601924	0	0
T1	17410	9073	0	0
T2	525	125	0	0
T4	9352	6138	0	0
T5	407	7	0	0
T6	500	100	0	0
T14	402	2	0	0
T15	405	5	0	0
T16	408	8	0	0
T19	521	121	0	0
T20	642	242	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	1648	0	0
T8	27383	28	0	0
T9	23901	0	0	0
T10	664	0	0	0
T13	0	20	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T26	0	16	0	0
T30	0	8	0	0
T32	0	9	0	0
T42	0	10	0	0
T46	0	11	0	0
T48	0	7	0	0
T49	0	30	0	0
T52	522	0	0	0
T53	506	0	0	0
T54	522	0	0	0
T57	607	0	0	0
T72	0	14	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	1580	0	0
T8	27383	28	0	0
T9	23901	0	0	0
T10	664	0	0	0
T13	0	20	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T26	0	16	0	0
T30	0	8	0	0
T32	0	9	0	0
T42	0	10	0	0
T46	0	11	0	0
T49	0	30	0	0
T52	522	0	0	0
T53	506	0	0	0
T54	522	0	0	0
T57	607	0	0	0
T72	0	7	0	0
T106	0	27	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	803	0	0
T8	27383	28	0	0
T9	23901	0	0	0
T10	664	0	0	0
T13	0	20	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T42	0	10	0	0
T52	522	0	0	0
T53	506	0	0	0
T54	522	0	0	0
T57	607	0	0	0
T72	0	7	0	0
T75	0	5	0	0
T106	0	27	0	0
T108	0	23	0	0
T121	0	9	0	0
T122	0	12	0	0
T214	0	18	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	803	0	0
T8	27383	28	0	0
T9	23901	0	0	0
T10	664	0	0	0
T13	0	20	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T42	0	10	0	0
T52	522	0	0	0
T53	506	0	0	0
T54	522	0	0	0
T57	607	0	0	0
T72	0	7	0	0
T75	0	5	0	0
T106	0	27	0	0
T108	0	23	0	0
T121	0	9	0	0
T122	0	12	0	0
T214	0	18	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	68141	0	0
T8	27383	3231	0	0
T9	23901	0	0	0
T10	664	0	0	0
T13	0	1670	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T42	0	821	0	0
T52	522	0	0	0
T53	506	0	0	0
T54	522	0	0	0
T57	607	0	0	0
T72	0	519	0	0
T75	0	431	0	0
T106	0	1761	0	0
T108	0	2059	0	0
T121	0	427	0	0
T122	0	1152	0	0
T214	0	787	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	9037396	0	0
T1	17410	9073	0	0
T2	525	125	0	0
T4	9352	6138	0	0
T5	407	7	0	0
T6	500	100	0	0
T14	402	2	0	0
T15	405	5	0	0
T16	408	8	0	0
T19	521	121	0	0
T20	642	242	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	9037396	0	0
T1	17410	9073	0	0
T2	525	125	0	0
T4	9352	6138	0	0
T5	407	7	0	0
T6	500	100	0	0
T14	402	2	0	0
T15	405	5	0	0
T16	408	8	0	0
T19	521	121	0	0
T20	642	242	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	698	0	0
T8	27383	22	0	0
T9	23901	0	0	0
T10	664	0	0	0
T13	0	18	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T42	0	8	0	0
T52	522	0	0	0
T53	506	0	0	0
T54	522	0	0	0
T57	607	0	0	0
T72	0	7	0	0
T75	0	5	0	0
T106	0	26	0	0
T108	0	18	0	0
T121	0	9	0	0
T122	0	12	0	0
T214	0	18	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T3,T8
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T8
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T3,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T3,T8

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T3,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T8
1	0	Covered	T4,T1,T3
1	1	Covered	T1,T3,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T8
0	1	Covered	T3,T76,T210
1	0	Covered	T75,T55

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T8
0	1	Covered	T1,T3,T8
1	0	Covered	T55

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T3,T8
1	-	Covered	T1,T3,T8

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T3,T8
DetectSt	168	Covered	T1,T3,T8
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T3,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T3,T8
DebounceSt->IdleSt	163	Covered	T3,T9,T31
DetectSt->IdleSt	186	Covered	T3,T75,T76
DetectSt->StableSt	191	Covered	T1,T3,T8
IdleSt->DebounceSt	148	Covered	T1,T3,T8
StableSt->IdleSt	206	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T3,T8
0	1	Covered	T1,T3,T8
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T8
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T3,T8
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T55
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T3,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T3,T9,T31
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T3,T8
DetectSt	-	-	-	-	1	-	-	Covered	T3,T75,T76
DetectSt	-	-	-	-	0	1	-	Covered	T1,T3,T8
DetectSt	-	-	-	-	0	0	-	Covered	T1,T3,T8
StableSt	-	-	-	-	-	-	1	Covered	T1,T3,T8
StableSt	-	-	-	-	-	-	0	Covered	T1,T3,T8
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9721734	894	0	0
CntIncr_A	9721734	48692	0	0
CntNoWrap_A	9721734	9034001	0	0
DetectStDropOut_A	9721734	62	0	0
DetectedOut_A	9721734	19168	0	0
DetectedPulseOut_A	9721734	351	0	0
DisabledIdleSt_A	9721734	8599069	0	0
DisabledNoDetection_A	9721734	8600833	0	0
EnterDebounceSt_A	9721734	477	0	0
EnterDetectSt_A	9721734	419	0	0
EnterStableSt_A	9721734	351	0	0
PulseIsPulse_A	9721734	351	0	0
StayInStableSt	9721734	18788	0	0
gen_high_level_sva.HighLevelEvent_A	9721734	9037396	0	0
gen_not_sticky_sva.StableStDropOut_A	9721734	321	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	894	0	0
T1	17410	2	0	0
T2	525	0	0	0
T3	41713	19	0	0
T7	1548	0	0	0
T8	27383	4	0	0
T9	0	5	0	0
T11	0	12	0	0
T13	0	4	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T31	0	23	0	0
T33	0	10	0	0
T42	0	2	0	0
T123	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	48692	0	0
T1	17410	181	0	0
T2	525	0	0	0
T3	41713	826	0	0
T7	1548	0	0	0
T8	27383	196	0	0
T9	0	440	0	0
T11	0	912	0	0
T13	0	150	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T31	0	1266	0	0
T33	0	565	0	0
T42	0	92	0	0
T123	0	90	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	9034001	0	0
T1	17410	9047	0	0
T2	525	124	0	0
T4	9352	6128	0	0
T5	407	6	0	0
T6	500	99	0	0
T14	402	1	0	0
T15	405	4	0	0
T16	408	7	0	0
T19	521	120	0	0
T20	642	241	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	62	0	0
T3	41713	4	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T9	23901	0	0	0
T10	664	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T52	522	0	0	0
T53	506	0	0	0
T76	0	4	0	0
T110	0	2	0	0
T138	0	1	0	0
T155	0	9	0	0
T210	0	4	0	0
T241	0	3	0	0
T250	0	1	0	0
T251	0	1	0	0
T252	0	5	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	19168	0	0
T1	17410	10	0	0
T2	525	0	0	0
T3	41713	76	0	0
T7	1548	0	0	0
T8	27383	136	0	0
T9	0	44	0	0
T11	0	194	0	0
T13	0	264	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T31	0	879	0	0
T33	0	281	0	0
T42	0	91	0	0
T123	0	21	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	351	0	0
T1	17410	1	0	0
T2	525	0	0	0
T3	41713	5	0	0
T7	1548	0	0	0
T8	27383	2	0	0
T9	0	2	0	0
T11	0	6	0	0
T13	0	2	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T31	0	11	0	0
T33	0	5	0	0
T42	0	1	0	0
T123	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	8599069	0	0
T1	17410	8023	0	0
T2	525	124	0	0
T4	9352	6128	0	0
T5	407	6	0	0
T6	500	99	0	0
T14	402	1	0	0
T15	405	4	0	0
T16	408	7	0	0
T19	521	120	0	0
T20	642	241	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	8600833	0	0
T1	17410	8045	0	0
T2	525	125	0	0
T4	9352	6138	0	0
T5	407	7	0	0
T6	500	100	0	0
T14	402	2	0	0
T15	405	5	0	0
T16	408	8	0	0
T19	521	121	0	0
T20	642	242	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	477	0	0
T1	17410	1	0	0
T2	525	0	0	0
T3	41713	10	0	0
T7	1548	0	0	0
T8	27383	2	0	0
T9	0	3	0	0
T11	0	6	0	0
T13	0	2	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T31	0	12	0	0
T33	0	5	0	0
T42	0	1	0	0
T123	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	419	0	0
T1	17410	1	0	0
T2	525	0	0	0
T3	41713	9	0	0
T7	1548	0	0	0
T8	27383	2	0	0
T9	0	2	0	0
T11	0	6	0	0
T13	0	2	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T31	0	11	0	0
T33	0	5	0	0
T42	0	1	0	0
T123	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	351	0	0
T1	17410	1	0	0
T2	525	0	0	0
T3	41713	5	0	0
T7	1548	0	0	0
T8	27383	2	0	0
T9	0	2	0	0
T11	0	6	0	0
T13	0	2	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T31	0	11	0	0
T33	0	5	0	0
T42	0	1	0	0
T123	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	351	0	0
T1	17410	1	0	0
T2	525	0	0	0
T3	41713	5	0	0
T7	1548	0	0	0
T8	27383	2	0	0
T9	0	2	0	0
T11	0	6	0	0
T13	0	2	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T31	0	11	0	0
T33	0	5	0	0
T42	0	1	0	0
T123	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	18788	0	0
T1	17410	9	0	0
T2	525	0	0	0
T3	41713	71	0	0
T7	1548	0	0	0
T8	27383	134	0	0
T9	0	42	0	0
T11	0	188	0	0
T13	0	262	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T31	0	868	0	0
T33	0	276	0	0
T42	0	89	0	0
T123	0	20	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	9037396	0	0
T1	17410	9073	0	0
T2	525	125	0	0
T4	9352	6138	0	0
T5	407	7	0	0
T6	500	100	0	0
T14	402	2	0	0
T15	405	5	0	0
T16	408	8	0	0
T19	521	121	0	0
T20	642	242	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	321	0	0
T1	17410	1	0	0
T2	525	0	0	0
T3	41713	5	0	0
T7	1548	0	0	0
T8	27383	2	0	0
T9	0	2	0	0
T11	0	6	0	0
T13	0	2	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T31	0	11	0	0
T33	0	5	0	0
T93	0	9	0	0
T123	0	1	0	0