Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T8,T13,T26
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T13,T26

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T13,T26

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T13,T26

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T13,T26
1	0	Covered	T8,T13,T26
1	1	Covered	T8,T13,T26

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T13,T26
0	1	Covered	T13,T46,T30
1	0	Covered	T13,T30,T106

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T26,T32
0	1	Covered	T8,T26,T32
1	0	Covered	T97

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T26,T32
1	-	Covered	T8,T26,T32

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T13,T26
DetectSt	168	Covered	T8,T13,T26
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T8,T26,T32

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T13,T26
DebounceSt->IdleSt	163	Covered	T48,T72,T75
DetectSt->IdleSt	186	Covered	T13,T46,T30
DetectSt->StableSt	191	Covered	T8,T26,T32
IdleSt->DebounceSt	148	Covered	T8,T13,T26
StableSt->IdleSt	206	Covered	T8,T26,T32

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T8,T13,T26
0	1	Covered	T8,T13,T26
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T13,T26
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T8,T13,T26
IdleSt	0	-	-	-	-	-	-	Covered	T8,T13,T26
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T55
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T13,T26
DebounceSt	-	0	1	0	-	-	-	Covered	T48,T72,T75
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T13,T26
DetectSt	-	-	-	-	1	-	-	Covered	T13,T46,T30
DetectSt	-	-	-	-	0	1	-	Covered	T8,T26,T32
DetectSt	-	-	-	-	0	0	-	Covered	T8,T13,T26
StableSt	-	-	-	-	-	-	1	Covered	T8,T26,T32
StableSt	-	-	-	-	-	-	0	Covered	T8,T26,T32
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9721734	2717	0	0
CntIncr_A	9721734	93955	0	0
CntNoWrap_A	9721734	9032178	0	0
DetectStDropOut_A	9721734	370	0	0
DetectedOut_A	9721734	69937	0	0
DetectedPulseOut_A	9721734	751	0	0
DisabledIdleSt_A	9721734	8597536	0	0
DisabledNoDetection_A	9721734	8599825	0	0
EnterDebounceSt_A	9721734	1395	0	0
EnterDetectSt_A	9721734	1324	0	0
EnterStableSt_A	9721734	751	0	0
PulseIsPulse_A	9721734	751	0	0
StayInStableSt	9721734	69065	0	0
gen_high_event_sva.HighLevelEvent_A	9721734	9037396	0	0
gen_high_level_sva.HighLevelEvent_A	9721734	9037396	0	0
gen_not_sticky_sva.StableStDropOut_A	9721734	610	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	2717	0	0
T8	27383	50	0	0
T9	23901	0	0	0
T10	664	0	0	0
T13	0	60	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T26	0	12	0	0
T30	0	12	0	0
T32	0	30	0	0
T42	0	36	0	0
T46	0	56	0	0
T48	0	17	0	0
T49	0	36	0	0
T52	522	0	0	0
T53	506	0	0	0
T54	522	0	0	0
T57	607	0	0	0
T72	0	30	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	93955	0	0
T8	27383	2250	0	0
T9	23901	0	0	0
T10	664	0	0	0
T13	0	2031	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T26	0	924	0	0
T30	0	341	0	0
T32	0	870	0	0
T42	0	1008	0	0
T46	0	2151	0	0
T48	0	735	0	0
T49	0	1160	0	0
T52	522	0	0	0
T53	506	0	0	0
T54	522	0	0	0
T57	607	0	0	0
T72	0	7207	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	9032178	0	0
T1	17410	9049	0	0
T2	525	124	0	0
T4	9352	6128	0	0
T5	407	6	0	0
T6	500	99	0	0
T14	402	1	0	0
T15	405	4	0	0
T16	408	7	0	0
T19	521	120	0	0
T20	642	241	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	370	0	0
T13	17130	10	0	0
T24	1115	0	0	0
T30	0	3	0	0
T43	691	0	0	0
T44	626	0	0	0
T46	0	28	0	0
T48	0	2	0	0
T49	0	18	0	0
T63	1417	0	0	0
T69	502	0	0	0
T70	505	0	0	0
T72	0	9	0	0
T75	0	1	0	0
T106	0	4	0	0
T107	0	22	0	0
T135	402	0	0	0
T136	503	0	0	0
T238	0	2	0	0
T253	422	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	69937	0	0
T8	27383	2561	0	0
T9	23901	0	0	0
T10	664	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T26	0	1113	0	0
T32	0	2392	0	0
T42	0	1845	0	0
T52	522	0	0	0
T53	506	0	0	0
T54	522	0	0	0
T57	607	0	0	0
T75	0	448	0	0
T121	0	102	0	0
T122	0	333	0	0
T203	0	484	0	0
T214	0	115	0	0
T240	0	2984	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	751	0	0
T8	27383	25	0	0
T9	23901	0	0	0
T10	664	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T26	0	6	0	0
T32	0	15	0	0
T42	0	18	0	0
T52	522	0	0	0
T53	506	0	0	0
T54	522	0	0	0
T57	607	0	0	0
T75	0	5	0	0
T121	0	5	0	0
T122	0	14	0	0
T203	0	6	0	0
T214	0	8	0	0
T240	0	31	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	8597536	0	0
T1	17410	9049	0	0
T2	525	124	0	0
T4	9352	6128	0	0
T5	407	6	0	0
T6	500	99	0	0
T14	402	1	0	0
T15	405	4	0	0
T16	408	7	0	0
T19	521	120	0	0
T20	642	241	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	8599825	0	0
T1	17410	9073	0	0
T2	525	125	0	0
T4	9352	6138	0	0
T5	407	7	0	0
T6	500	100	0	0
T14	402	2	0	0
T15	405	5	0	0
T16	408	8	0	0
T19	521	121	0	0
T20	642	242	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	1395	0	0
T8	27383	25	0	0
T9	23901	0	0	0
T10	664	0	0	0
T13	0	30	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T26	0	6	0	0
T30	0	6	0	0
T32	0	15	0	0
T42	0	18	0	0
T46	0	28	0	0
T48	0	15	0	0
T49	0	18	0	0
T52	522	0	0	0
T53	506	0	0	0
T54	522	0	0	0
T57	607	0	0	0
T72	0	22	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	1324	0	0
T8	27383	25	0	0
T9	23901	0	0	0
T10	664	0	0	0
T13	0	30	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T26	0	6	0	0
T30	0	6	0	0
T32	0	15	0	0
T42	0	18	0	0
T46	0	28	0	0
T48	0	2	0	0
T49	0	18	0	0
T52	522	0	0	0
T53	506	0	0	0
T54	522	0	0	0
T57	607	0	0	0
T72	0	9	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	751	0	0
T8	27383	25	0	0
T9	23901	0	0	0
T10	664	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T26	0	6	0	0
T32	0	15	0	0
T42	0	18	0	0
T52	522	0	0	0
T53	506	0	0	0
T54	522	0	0	0
T57	607	0	0	0
T75	0	5	0	0
T121	0	5	0	0
T122	0	14	0	0
T203	0	6	0	0
T214	0	8	0	0
T240	0	31	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	751	0	0
T8	27383	25	0	0
T9	23901	0	0	0
T10	664	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T26	0	6	0	0
T32	0	15	0	0
T42	0	18	0	0
T52	522	0	0	0
T53	506	0	0	0
T54	522	0	0	0
T57	607	0	0	0
T75	0	5	0	0
T121	0	5	0	0
T122	0	14	0	0
T203	0	6	0	0
T214	0	8	0	0
T240	0	31	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	69065	0	0
T8	27383	2531	0	0
T9	23901	0	0	0
T10	664	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T26	0	1106	0	0
T32	0	2372	0	0
T42	0	1825	0	0
T52	522	0	0	0
T53	506	0	0	0
T54	522	0	0	0
T57	607	0	0	0
T75	0	443	0	0
T121	0	97	0	0
T122	0	319	0	0
T203	0	475	0	0
T214	0	107	0	0
T240	0	2949	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	9037396	0	0
T1	17410	9073	0	0
T2	525	125	0	0
T4	9352	6138	0	0
T5	407	7	0	0
T6	500	100	0	0
T14	402	2	0	0
T15	405	5	0	0
T16	408	8	0	0
T19	521	121	0	0
T20	642	242	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	9037396	0	0
T1	17410	9073	0	0
T2	525	125	0	0
T4	9352	6138	0	0
T5	407	7	0	0
T6	500	100	0	0
T14	402	2	0	0
T15	405	5	0	0
T16	408	8	0	0
T19	521	121	0	0
T20	642	242	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	610	0	0
T8	27383	20	0	0
T9	23901	0	0	0
T10	664	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T26	0	5	0	0
T32	0	10	0	0
T42	0	16	0	0
T52	522	0	0	0
T53	506	0	0	0
T54	522	0	0	0
T57	607	0	0	0
T75	0	5	0	0
T121	0	5	0	0
T122	0	14	0	0
T203	0	3	0	0
T214	0	8	0	0
T240	0	27	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T3,T8
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T8
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T3,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T3,T8

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T3,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T8
1	0	Covered	T4,T1,T3
1	1	Covered	T1,T3,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T8
0	1	Covered	T3,T123,T254
1	0	Covered	T75,T55

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T8
0	1	Covered	T1,T3,T8
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T3,T8
1	-	Covered	T1,T3,T8

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T3,T8
DetectSt	168	Covered	T1,T3,T8
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T3,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T3,T8
DebounceSt->IdleSt	163	Covered	T3,T45,T32
DetectSt->IdleSt	186	Covered	T3,T123,T75
DetectSt->StableSt	191	Covered	T1,T3,T8
IdleSt->DebounceSt	148	Covered	T1,T3,T8
StableSt->IdleSt	206	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T3,T8
0	1	Covered	T1,T3,T8
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T8
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T3,T8
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T55
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T3,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T3,T45,T32
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T3,T8
DetectSt	-	-	-	-	1	-	-	Covered	T3,T123,T75
DetectSt	-	-	-	-	0	1	-	Covered	T1,T3,T8
DetectSt	-	-	-	-	0	0	-	Covered	T1,T3,T8
StableSt	-	-	-	-	-	-	1	Covered	T1,T3,T8
StableSt	-	-	-	-	-	-	0	Covered	T1,T3,T8
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9721734	871	0	0
CntIncr_A	9721734	49113	0	0
CntNoWrap_A	9721734	9034024	0	0
DetectStDropOut_A	9721734	88	0	0
DetectedOut_A	9721734	17288	0	0
DetectedPulseOut_A	9721734	319	0	0
DisabledIdleSt_A	9721734	8608345	0	0
DisabledNoDetection_A	9721734	8610095	0	0
EnterDebounceSt_A	9721734	460	0	0
EnterDetectSt_A	9721734	414	0	0
EnterStableSt_A	9721734	319	0	0
PulseIsPulse_A	9721734	319	0	0
StayInStableSt	9721734	16942	0	0
gen_high_level_sva.HighLevelEvent_A	9721734	9037396	0	0
gen_not_sticky_sva.StableStDropOut_A	9721734	289	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	871	0	0
T1	17410	2	0	0
T2	525	0	0	0
T3	41713	30	0	0
T7	1548	0	0	0
T8	27383	8	0	0
T9	0	6	0	0
T11	0	2	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T26	0	2	0	0
T31	0	8	0	0
T32	0	12	0	0
T42	0	2	0	0
T45	0	13	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	49113	0	0
T1	17410	98	0	0
T2	525	0	0	0
T3	41713	1269	0	0
T7	1548	0	0	0
T8	27383	460	0	0
T9	0	342	0	0
T11	0	162	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T26	0	163	0	0
T31	0	564	0	0
T32	0	414	0	0
T42	0	93	0	0
T45	0	915	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	9034024	0	0
T1	17410	9047	0	0
T2	525	124	0	0
T4	9352	6128	0	0
T5	407	6	0	0
T6	500	99	0	0
T14	402	1	0	0
T15	405	4	0	0
T16	408	7	0	0
T19	521	120	0	0
T20	642	241	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	88	0	0
T3	41713	1	0	0
T7	1548	0	0	0
T8	27383	0	0	0
T9	23901	0	0	0
T10	664	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T25	486	0	0	0
T52	522	0	0	0
T53	506	0	0	0
T123	0	1	0	0
T155	0	5	0	0
T241	0	1	0	0
T245	0	10	0	0
T246	0	1	0	0
T250	0	2	0	0
T254	0	3	0	0
T255	0	8	0	0
T256	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	17288	0	0
T1	17410	93	0	0
T2	525	0	0	0
T3	41713	225	0	0
T7	1548	0	0	0
T8	27383	208	0	0
T9	0	241	0	0
T11	0	22	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T26	0	77	0	0
T31	0	182	0	0
T32	0	429	0	0
T42	0	90	0	0
T45	0	530	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	319	0	0
T1	17410	1	0	0
T2	525	0	0	0
T3	41713	13	0	0
T7	1548	0	0	0
T8	27383	4	0	0
T9	0	3	0	0
T11	0	1	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T26	0	1	0	0
T31	0	4	0	0
T32	0	5	0	0
T42	0	1	0	0
T45	0	6	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	8608345	0	0
T1	17410	8023	0	0
T2	525	124	0	0
T4	9352	6128	0	0
T5	407	6	0	0
T6	500	99	0	0
T14	402	1	0	0
T15	405	4	0	0
T16	408	7	0	0
T19	521	120	0	0
T20	642	241	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	8610095	0	0
T1	17410	8045	0	0
T2	525	125	0	0
T4	9352	6138	0	0
T5	407	7	0	0
T6	500	100	0	0
T14	402	2	0	0
T15	405	5	0	0
T16	408	8	0	0
T19	521	121	0	0
T20	642	242	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	460	0	0
T1	17410	1	0	0
T2	525	0	0	0
T3	41713	16	0	0
T7	1548	0	0	0
T8	27383	4	0	0
T9	0	3	0	0
T11	0	1	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T26	0	1	0	0
T31	0	4	0	0
T32	0	7	0	0
T42	0	1	0	0
T45	0	7	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	414	0	0
T1	17410	1	0	0
T2	525	0	0	0
T3	41713	15	0	0
T7	1548	0	0	0
T8	27383	4	0	0
T9	0	3	0	0
T11	0	1	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T26	0	1	0	0
T31	0	4	0	0
T32	0	5	0	0
T42	0	1	0	0
T45	0	6	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	319	0	0
T1	17410	1	0	0
T2	525	0	0	0
T3	41713	13	0	0
T7	1548	0	0	0
T8	27383	4	0	0
T9	0	3	0	0
T11	0	1	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T26	0	1	0	0
T31	0	4	0	0
T32	0	5	0	0
T42	0	1	0	0
T45	0	6	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	319	0	0
T1	17410	1	0	0
T2	525	0	0	0
T3	41713	13	0	0
T7	1548	0	0	0
T8	27383	4	0	0
T9	0	3	0	0
T11	0	1	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T26	0	1	0	0
T31	0	4	0	0
T32	0	5	0	0
T42	0	1	0	0
T45	0	6	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	16942	0	0
T1	17410	92	0	0
T2	525	0	0	0
T3	41713	212	0	0
T7	1548	0	0	0
T8	27383	204	0	0
T9	0	238	0	0
T11	0	21	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T26	0	75	0	0
T31	0	178	0	0
T32	0	424	0	0
T42	0	88	0	0
T45	0	524	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	9037396	0	0
T1	17410	9073	0	0
T2	525	125	0	0
T4	9352	6138	0	0
T5	407	7	0	0
T6	500	100	0	0
T14	402	2	0	0
T15	405	5	0	0
T16	408	8	0	0
T19	521	121	0	0
T20	642	242	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9721734	289	0	0
T1	17410	1	0	0
T2	525	0	0	0
T3	41713	13	0	0
T7	1548	0	0	0
T8	27383	4	0	0
T9	0	3	0	0
T11	0	1	0	0
T14	402	0	0	0
T15	405	0	0	0
T16	408	0	0	0
T17	522	0	0	0
T18	61537	0	0	0
T31	0	4	0	0
T32	0	5	0	0
T33	0	2	0	0
T45	0	6	0	0
T93	0	2	0	0