Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1280293521	9603	0	0
auto_block_debounce_ctl_rd_A	1280293521	1728	0	0
auto_block_out_ctl_rd_A	1280293521	2218	0	0
com_det_ctl_0_rd_A	1280293521	4046	0	0
com_det_ctl_1_rd_A	1280293521	3954	0	0
com_det_ctl_2_rd_A	1280293521	4093	0	0
com_det_ctl_3_rd_A	1280293521	4362	0	0
com_out_ctl_0_rd_A	1280293521	4313	0	0
com_out_ctl_1_rd_A	1280293521	4446	0	0
com_out_ctl_2_rd_A	1280293521	4476	0	0
com_out_ctl_3_rd_A	1280293521	4741	0	0
com_pre_det_ctl_0_rd_A	1280293521	1290	0	0
com_pre_det_ctl_1_rd_A	1280293521	1237	0	0
com_pre_det_ctl_2_rd_A	1280293521	1345	0	0
com_pre_det_ctl_3_rd_A	1280293521	1354	0	0
com_pre_sel_ctl_0_rd_A	1280293521	4461	0	0
com_pre_sel_ctl_1_rd_A	1280293521	4374	0	0
com_pre_sel_ctl_2_rd_A	1280293521	4574	0	0
com_pre_sel_ctl_3_rd_A	1280293521	4746	0	0
com_sel_ctl_0_rd_A	1280293521	4415	0	0
com_sel_ctl_1_rd_A	1280293521	4446	0	0
com_sel_ctl_2_rd_A	1280293521	4892	0	0
com_sel_ctl_3_rd_A	1280293521	4680	0	0
ec_rst_ctl_rd_A	1280293521	2705	0	0
intr_enable_rd_A	1280293521	2165	0	0
key_intr_ctl_rd_A	1280293521	2749	0	0
key_intr_debounce_ctl_rd_A	1280293521	1388	0	0
key_invert_ctl_rd_A	1280293521	5137	0	0
pin_allowed_ctl_rd_A	1280293521	5964	0	0
pin_out_ctl_rd_A	1280293521	4800	0	0
pin_out_value_rd_A	1280293521	4629	0	0
regwen_rd_A	1280293521	1618	0	0
ulp_ac_debounce_ctl_rd_A	1280293521	1531	0	0
ulp_ctl_rd_A	1280293521	1531	0	0
ulp_lid_debounce_ctl_rd_A	1280293521	1542	0	0
ulp_pwrb_debounce_ctl_rd_A	1280293521	1418	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280293521	9603	0	0
T1	834120	18	0	0
T2	48988	0	0	0
T3	0	13	0	0
T4	416183	20	0	0
T5	50855	0	0	0
T6	22532	0	0	0
T14	201092	0	0	0
T15	50692	0	0	0
T16	48969	0	0	0
T19	247955	0	0	0
T20	67485	0	0	0
T34	0	4	0	0
T36	0	5	0	0
T40	0	14	0	0
T41	0	5	0	0
T59	0	14	0	0
T109	0	11	0	0
T265	0	9	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280293521	1728	0	0
T3	583991	42	0	0
T7	65026	0	0	0
T8	342298	0	0	0
T9	298761	0	0	0
T10	79733	0	0	0
T17	261230	0	0	0
T18	301539	4	0	0
T25	216359	0	0	0
T34	0	1	0	0
T36	0	26	0	0
T41	0	22	0	0
T44	0	4	0	0
T51	0	12	0	0
T52	253295	0	0	0
T53	60803	0	0	0
T59	0	14	0	0
T261	0	13	0	0
T266	0	1	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280293521	2218	0	0
T3	583991	31	0	0
T7	65026	0	0	0
T8	342298	0	0	0
T9	298761	0	0	0
T10	79733	0	0	0
T17	261230	0	0	0
T18	301539	8	0	0
T25	216359	0	0	0
T34	0	16	0	0
T36	0	20	0	0
T41	0	13	0	0
T44	0	3	0	0
T51	0	11	0	0
T52	253295	0	0	0
T53	60803	0	0	0
T59	0	10	0	0
T261	0	18	0	0
T266	0	3	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280293521	4046	0	0
T3	583991	184	0	0
T7	65026	0	0	0
T8	342298	0	0	0
T9	298761	71	0	0
T10	79733	0	0	0
T17	261230	0	0	0
T18	301539	0	0	0
T25	216359	0	0	0
T30	0	33	0	0
T34	0	8	0	0
T41	0	15	0	0
T45	0	61	0	0
T52	253295	0	0	0
T53	60803	0	0	0
T59	0	21	0	0
T122	0	48	0	0
T214	0	43	0	0
T242	0	67	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280293521	3954	0	0
T3	583991	153	0	0
T7	65026	0	0	0
T8	342298	0	0	0
T9	298761	69	0	0
T10	79733	0	0	0
T17	261230	0	0	0
T18	301539	0	0	0
T25	216359	0	0	0
T30	0	30	0	0
T34	0	5	0	0
T41	0	13	0	0
T45	0	64	0	0
T52	253295	0	0	0
T53	60803	0	0	0
T59	0	30	0	0
T122	0	46	0	0
T214	0	29	0	0
T242	0	82	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280293521	4093	0	0
T3	583991	203	0	0
T7	65026	0	0	0
T8	342298	0	0	0
T9	298761	59	0	0
T10	79733	0	0	0
T17	261230	0	0	0
T18	301539	0	0	0
T25	216359	0	0	0
T30	0	13	0	0
T34	0	12	0	0
T41	0	19	0	0
T45	0	74	0	0
T52	253295	0	0	0
T53	60803	0	0	0
T59	0	24	0	0
T122	0	42	0	0
T214	0	7	0	0
T242	0	64	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280293521	4362	0	0
T3	583991	209	0	0
T7	65026	0	0	0
T8	342298	0	0	0
T9	298761	82	0	0
T10	79733	0	0	0
T17	261230	0	0	0
T18	301539	0	0	0
T25	216359	0	0	0
T30	0	35	0	0
T34	0	5	0	0
T41	0	5	0	0
T45	0	98	0	0
T52	253295	0	0	0
T53	60803	0	0	0
T59	0	8	0	0
T122	0	45	0	0
T214	0	43	0	0
T242	0	64	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280293521	4313	0	0
T3	583991	198	0	0
T7	65026	0	0	0
T8	342298	0	0	0
T9	298761	66	0	0
T10	79733	0	0	0
T17	261230	0	0	0
T18	301539	0	0	0
T25	216359	0	0	0
T30	0	24	0	0
T34	0	16	0	0
T41	0	7	0	0
T45	0	63	0	0
T52	253295	0	0	0
T53	60803	0	0	0
T59	0	14	0	0
T122	0	24	0	0
T214	0	55	0	0
T242	0	50	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280293521	4446	0	0
T3	583991	198	0	0
T7	65026	0	0	0
T8	342298	0	0	0
T9	298761	83	0	0
T10	79733	0	0	0
T17	261230	0	0	0
T18	301539	0	0	0
T25	216359	0	0	0
T30	0	19	0	0
T34	0	21	0	0
T41	0	8	0	0
T45	0	81	0	0
T52	253295	0	0	0
T53	60803	0	0	0
T59	0	25	0	0
T122	0	44	0	0
T214	0	27	0	0
T242	0	88	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280293521	4476	0	0
T3	583991	212	0	0
T7	65026	0	0	0
T8	342298	0	0	0
T9	298761	77	0	0
T10	79733	0	0	0
T17	261230	0	0	0
T18	301539	0	0	0
T25	216359	0	0	0
T30	0	32	0	0
T34	0	18	0	0
T41	0	8	0	0
T45	0	60	0	0
T52	253295	0	0	0
T53	60803	0	0	0
T59	0	20	0	0
T122	0	23	0	0
T214	0	35	0	0
T242	0	74	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280293521	4741	0	0
T3	583991	205	0	0
T7	65026	0	0	0
T8	342298	0	0	0
T9	298761	70	0	0
T10	79733	0	0	0
T17	261230	0	0	0
T18	301539	0	0	0
T25	216359	0	0	0
T30	0	29	0	0
T34	0	11	0	0
T41	0	15	0	0
T45	0	82	0	0
T52	253295	0	0	0
T53	60803	0	0	0
T59	0	32	0	0
T122	0	25	0	0
T214	0	57	0	0
T242	0	100	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280293521	1290	0	0
T3	583991	28	0	0
T7	65026	0	0	0
T8	342298	0	0	0
T9	298761	0	0	0
T10	79733	0	0	0
T17	261230	0	0	0
T18	301539	0	0	0
T25	216359	0	0	0
T34	0	20	0	0
T36	0	14	0	0
T41	0	15	0	0
T52	253295	0	0	0
T53	60803	0	0	0
T59	0	20	0	0
T110	0	8	0	0
T267	0	18	0	0
T268	0	1	0	0
T269	0	30	0	0
T270	0	4	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280293521	1237	0	0
T3	583991	20	0	0
T7	65026	0	0	0
T8	342298	0	0	0
T9	298761	0	0	0
T10	79733	0	0	0
T17	261230	0	0	0
T18	301539	0	0	0
T25	216359	0	0	0
T34	0	6	0	0
T36	0	6	0	0
T41	0	5	0	0
T52	253295	0	0	0
T53	60803	0	0	0
T59	0	25	0	0
T110	0	1	0	0
T267	0	12	0	0
T268	0	6	0	0
T269	0	8	0	0
T270	0	7	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280293521	1345	0	0
T3	583991	25	0	0
T7	65026	0	0	0
T8	342298	0	0	0
T9	298761	0	0	0
T10	79733	0	0	0
T17	261230	0	0	0
T18	301539	0	0	0
T25	216359	0	0	0
T34	0	3	0	0
T36	0	5	0	0
T41	0	7	0	0
T52	253295	0	0	0
T53	60803	0	0	0
T59	0	8	0	0
T110	0	12	0	0
T267	0	7	0	0
T268	0	3	0	0
T269	0	19	0	0
T270	0	13	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280293521	1354	0	0
T3	583991	15	0	0
T7	65026	0	0	0
T8	342298	0	0	0
T9	298761	0	0	0
T10	79733	0	0	0
T17	261230	0	0	0
T18	301539	0	0	0
T25	216359	0	0	0
T34	0	13	0	0
T36	0	6	0	0
T41	0	5	0	0
T52	253295	0	0	0
T53	60803	0	0	0
T59	0	16	0	0
T110	0	8	0	0
T267	0	14	0	0
T268	0	7	0	0
T269	0	21	0	0
T270	0	16	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280293521	4461	0	0
T3	583991	198	0	0
T7	65026	0	0	0
T8	342298	0	0	0
T9	298761	72	0	0
T10	79733	0	0	0
T17	261230	0	0	0
T18	301539	0	0	0
T25	216359	0	0	0
T30	0	30	0	0
T34	0	5	0	0
T41	0	5	0	0
T45	0	56	0	0
T52	253295	0	0	0
T53	60803	0	0	0
T59	0	28	0	0
T122	0	21	0	0
T214	0	54	0	0
T242	0	79	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280293521	4374	0	0
T3	583991	216	0	0
T7	65026	0	0	0
T8	342298	0	0	0
T9	298761	80	0	0
T10	79733	0	0	0
T17	261230	0	0	0
T18	301539	0	0	0
T25	216359	0	0	0
T30	0	29	0	0
T34	0	16	0	0
T41	0	8	0	0
T45	0	69	0	0
T52	253295	0	0	0
T53	60803	0	0	0
T59	0	37	0	0
T122	0	44	0	0
T214	0	20	0	0
T242	0	59	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280293521	4574	0	0
T3	583991	188	0	0
T7	65026	0	0	0
T8	342298	0	0	0
T9	298761	64	0	0
T10	79733	0	0	0
T17	261230	0	0	0
T18	301539	0	0	0
T25	216359	0	0	0
T30	0	15	0	0
T34	0	12	0	0
T41	0	20	0	0
T45	0	44	0	0
T52	253295	0	0	0
T53	60803	0	0	0
T59	0	29	0	0
T122	0	28	0	0
T214	0	35	0	0
T242	0	71	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280293521	4746	0	0
T3	583991	238	0	0
T7	65026	0	0	0
T8	342298	0	0	0
T9	298761	62	0	0
T10	79733	0	0	0
T17	261230	0	0	0
T18	301539	0	0	0
T25	216359	0	0	0
T30	0	28	0	0
T34	0	18	0	0
T41	0	9	0	0
T45	0	96	0	0
T52	253295	0	0	0
T53	60803	0	0	0
T59	0	27	0	0
T122	0	33	0	0
T214	0	18	0	0
T242	0	85	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280293521	4415	0	0
T3	583991	237	0	0
T7	65026	0	0	0
T8	342298	0	0	0
T9	298761	59	0	0
T10	79733	0	0	0
T17	261230	0	0	0
T18	301539	0	0	0
T25	216359	0	0	0
T30	0	16	0	0
T34	0	8	0	0
T41	0	11	0	0
T45	0	77	0	0
T52	253295	0	0	0
T53	60803	0	0	0
T59	0	18	0	0
T122	0	36	0	0
T214	0	46	0	0
T242	0	57	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280293521	4446	0	0
T3	583991	176	0	0
T7	65026	0	0	0
T8	342298	0	0	0
T9	298761	72	0	0
T10	79733	0	0	0
T17	261230	0	0	0
T18	301539	0	0	0
T25	216359	0	0	0
T30	0	6	0	0
T34	0	8	0	0
T41	0	22	0	0
T45	0	66	0	0
T52	253295	0	0	0
T53	60803	0	0	0
T59	0	13	0	0
T122	0	17	0	0
T214	0	34	0	0
T242	0	80	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280293521	4892	0	0
T3	583991	212	0	0
T7	65026	0	0	0
T8	342298	0	0	0
T9	298761	74	0	0
T10	79733	0	0	0
T17	261230	0	0	0
T18	301539	0	0	0
T25	216359	0	0	0
T30	0	14	0	0
T34	0	14	0	0
T41	0	13	0	0
T45	0	67	0	0
T52	253295	0	0	0
T53	60803	0	0	0
T59	0	13	0	0
T122	0	17	0	0
T214	0	54	0	0
T242	0	82	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280293521	4680	0	0
T3	583991	199	0	0
T7	65026	0	0	0
T8	342298	0	0	0
T9	298761	73	0	0
T10	79733	0	0	0
T17	261230	0	0	0
T18	301539	0	0	0
T25	216359	0	0	0
T30	0	5	0	0
T34	0	4	0	0
T41	0	10	0	0
T45	0	80	0	0
T52	253295	0	0	0
T53	60803	0	0	0
T59	0	34	0	0
T122	0	25	0	0
T214	0	42	0	0
T242	0	40	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280293521	2705	0	0
T3	583991	57	0	0
T7	65026	0	0	0
T8	342298	0	0	0
T9	298761	30	0	0
T10	79733	0	0	0
T17	261230	0	0	0
T18	301539	0	0	0
T25	216359	0	0	0
T34	0	20	0	0
T41	0	15	0	0
T45	0	43	0	0
T52	253295	0	0	0
T53	60803	0	0	0
T59	0	29	0	0
T64	0	9	0	0
T71	0	10	0	0
T122	0	10	0	0
T242	0	78	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280293521	2165	0	0
T3	583991	42	0	0
T7	65026	0	0	0
T8	342298	0	0	0
T9	298761	0	0	0
T10	79733	0	0	0
T17	261230	0	0	0
T18	301539	0	0	0
T25	216359	0	0	0
T34	0	9	0	0
T36	0	22	0	0
T41	0	8	0	0
T52	253295	0	0	0
T53	60803	0	0	0
T59	0	16	0	0
T110	0	19	0	0
T267	0	37	0	0
T268	0	15	0	0
T269	0	24	0	0
T270	0	4	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280293521	2749	0	0
T3	583991	28	0	0
T7	65026	0	0	0
T8	342298	0	0	0
T9	298761	0	0	0
T10	79733	0	0	0
T17	261230	0	0	0
T18	301539	0	0	0
T25	216359	0	0	0
T34	0	13	0	0
T36	0	9	0	0
T41	0	11	0	0
T52	253295	0	0	0
T53	60803	0	0	0
T59	0	13	0	0
T110	0	9	0	0
T151	0	4	0	0
T182	0	8	0	0
T183	0	8	0	0
T191	0	2	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280293521	1388	0	0
T3	583991	21	0	0
T7	65026	0	0	0
T8	342298	0	0	0
T9	298761	0	0	0
T10	79733	0	0	0
T17	261230	0	0	0
T18	301539	0	0	0
T25	216359	0	0	0
T34	0	7	0	0
T36	0	7	0	0
T41	0	14	0	0
T52	253295	0	0	0
T53	60803	0	0	0
T59	0	27	0	0
T110	0	7	0	0
T267	0	9	0	0
T268	0	2	0	0
T269	0	19	0	0
T270	0	3	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280293521	5137	0	0
T3	583991	88	0	0
T7	65026	0	0	0
T8	342298	0	0	0
T9	298761	0	0	0
T10	79733	0	0	0
T17	261230	0	0	0
T18	301539	0	0	0
T25	216359	71	0	0
T41	0	64	0	0
T52	253295	0	0	0
T53	60803	0	0	0
T59	0	21	0	0
T63	0	29	0	0
T64	0	55	0	0
T66	0	70	0	0
T67	0	81	0	0
T68	0	80	0	0
T187	0	64	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280293521	5964	0	0
T3	583991	28	0	0
T7	65026	0	0	0
T8	342298	0	0	0
T9	298761	0	0	0
T10	79733	0	0	0
T17	261230	0	0	0
T18	301539	0	0	0
T25	216359	0	0	0
T34	0	160	0	0
T36	0	11	0	0
T41	0	52	0	0
T52	253295	0	0	0
T53	60803	0	0	0
T59	0	21	0	0
T69	0	34	0	0
T71	0	95	0	0
T116	0	64	0	0
T143	0	42	0	0
T271	0	74	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280293521	4800	0	0
T3	583991	25	0	0
T7	65026	0	0	0
T8	342298	0	0	0
T9	298761	0	0	0
T10	79733	0	0	0
T17	261230	0	0	0
T18	301539	0	0	0
T25	216359	0	0	0
T34	0	170	0	0
T36	0	9	0	0
T41	0	49	0	0
T52	253295	0	0	0
T53	60803	0	0	0
T59	0	17	0	0
T69	0	40	0	0
T71	0	78	0	0
T116	0	81	0	0
T143	0	46	0	0
T271	0	56	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280293521	4629	0	0
T3	583991	29	0	0
T7	65026	0	0	0
T8	342298	0	0	0
T9	298761	0	0	0
T10	79733	0	0	0
T17	261230	0	0	0
T18	301539	0	0	0
T25	216359	0	0	0
T34	0	106	0	0
T36	0	7	0	0
T41	0	35	0	0
T52	253295	0	0	0
T53	60803	0	0	0
T59	0	20	0	0
T69	0	39	0	0
T71	0	61	0	0
T116	0	80	0	0
T143	0	42	0	0
T271	0	67	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280293521	1618	0	0
T3	583991	19	0	0
T7	65026	0	0	0
T8	342298	0	0	0
T9	298761	0	0	0
T10	79733	0	0	0
T17	261230	0	0	0
T18	301539	0	0	0
T25	216359	0	0	0
T34	0	7	0	0
T36	0	4	0	0
T41	0	6	0	0
T52	253295	0	0	0
T53	60803	0	0	0
T59	0	32	0	0
T110	0	12	0	0
T157	0	16	0	0
T267	0	2	0	0
T269	0	27	0	0
T270	0	8	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280293521	1531	0	0
T3	583991	27	0	0
T7	65026	0	0	0
T8	342298	0	0	0
T9	298761	0	0	0
T10	79733	0	0	0
T17	261230	0	0	0
T18	301539	0	0	0
T25	216359	0	0	0
T34	0	19	0	0
T36	0	4	0	0
T41	0	6	0	0
T52	253295	0	0	0
T53	60803	0	0	0
T59	0	28	0	0
T74	0	9	0	0
T110	0	18	0	0
T267	0	27	0	0
T272	0	1	0	0
T273	0	2	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280293521	1531	0	0
T3	583991	20	0	0
T7	65026	0	0	0
T8	342298	0	0	0
T9	298761	0	0	0
T10	79733	0	0	0
T17	261230	0	0	0
T18	301539	0	0	0
T25	216359	0	0	0
T34	0	18	0	0
T36	0	6	0	0
T41	0	8	0	0
T52	253295	0	0	0
T53	60803	0	0	0
T59	0	16	0	0
T74	0	6	0	0
T110	0	20	0	0
T267	0	15	0	0
T268	0	5	0	0
T272	0	6	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280293521	1542	0	0
T3	583991	30	0	0
T7	65026	0	0	0
T8	342298	0	0	0
T9	298761	0	0	0
T10	79733	0	0	0
T17	261230	0	0	0
T18	301539	0	0	0
T25	216359	0	0	0
T34	0	7	0	0
T36	0	17	0	0
T41	0	16	0	0
T52	253295	0	0	0
T53	60803	0	0	0
T59	0	29	0	0
T74	0	10	0	0
T110	0	15	0	0
T267	0	21	0	0
T272	0	3	0	0
T273	0	7	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280293521	1418	0	0
T3	583991	31	0	0
T7	65026	0	0	0
T8	342298	0	0	0
T9	298761	0	0	0
T10	79733	0	0	0
T17	261230	0	0	0
T18	301539	0	0	0
T25	216359	0	0	0
T34	0	11	0	0
T36	0	7	0	0
T41	0	18	0	0
T52	253295	0	0	0
T53	60803	0	0	0
T59	0	35	0	0
T74	0	9	0	0
T110	0	12	0	0
T267	0	15	0	0
T272	0	1	0	0
T273	0	7	0	0