Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
93.90	93.90	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	93.90	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.90	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	5	57	91.94

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	5	26	83.87	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2103

1

T2

6

T7

3

T9

21

auto[1]

681

1

T2

14

T6

1

T7

1

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2109

1

T2

11

T6

1

T7

4

auto[1]

675

1

T2

9

T9

5

T43

6

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2111

1

T2

7

T7

3

T9

36

auto[1]

673

1

T2

13

T6

1

T7

1

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2027

1

T2

13

T7

4

T9

27

auto[1]

757

1

T2

7

T6

1

T9

9

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2524

1

T2

20

T6

1

T7

4

auto[1]

260

1

T10

5

T33

3

T47

3

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2561

1

T2

20

T6

1

T7

3

auto[1]

223

1

T7

1

T10

5

T72

6

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2545

1

T2

20

T6

1

T7

4

auto[1]

239

1

T9

20

T33

8

T72

13

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2562

1

T2

20

T6

1

T7

3

auto[1]

222

1

T7

1

T9

5

T10

15

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2525

1

T2

20

T6

1

T7

3

auto[1]

259

1

T7

1

T9

11

T10

15

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2189

1

T2

19

T7

4

T9

36

auto[1]

595

1

T2

1

T6

1

T32

1

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	5	26	83.87	5
Automatically Generated Cross Bins	31	5	26	83.87	5
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	900	1			T2	19		T6	1		T11	3
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	112	1			T47	2		T358	1		T359	3
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	84	1			T33	8		T345	3		T360	8
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	26	1			T33	3		T47	1		T81	7
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	68	1			T119	4		T260	4		T358	1
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	27	1			T141	4		T361	1		T362	1
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	27	1			T10	5		T33	4		T72	2
auto[0]	auto[0]	auto[1]	auto[1]	auto[1]	3	1			T348	3		-	-		-	-
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	116	1			T9	6		T33	8		T141	4
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	22	1			T72	7		T260	1		T363	3
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	27	1			T9	3		T364	4		T365	6
auto[0]	auto[1]	auto[0]	auto[1]	auto[1]	9	1			T346	3		T364	1		T350	5
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	16	1			T260	1		T366	4		T361	1
auto[0]	auto[1]	auto[1]	auto[1]	auto[0]	6	1			T9	3		T350	3		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	77	1			T141	10		T349	4		T367	2
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	14	1			T119	2		T259	4		T368	3
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	31	1			T260	4		T262	4		T360	7
auto[1]	auto[0]	auto[0]	auto[1]	auto[1]	4	1			T368	1		T347	3		-	-
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	25	1			T141	2		T349	2		T367	2
auto[1]	auto[0]	auto[1]	auto[0]	auto[1]	4	1			T340	2		T348	2		-	-
auto[1]	auto[0]	auto[1]	auto[1]	auto[0]	3	1			T7	1		T342	2		-	-
auto[1]	auto[0]	auto[1]	auto[1]	auto[1]	2	1			T340	2		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	17	1			T72	6		T369	3		T346	3
auto[1]	auto[1]	auto[0]	auto[0]	auto[1]	3	1			T347	3		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[1]	auto[0]	1	1			T352	1		-	-		-	-
auto[1]	auto[1]	auto[1]	auto[0]	auto[0]	2	1			T262	2		-	-		-	-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

129

1

T9

3

T10

5

T11

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

53

1

T171

6

T262

2

T96

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

67

1

T43

3

T72

6

T268

6

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

200

1

T32

9

T33

3

T47

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

77

1

T9

6

T32

4

T91

6

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

74

1

T127

6

T119

2

T260

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

17

1

T88

5

T175

1

T287

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

121

1

T142

14

T360

8

T340

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

66

1

T2

5

T7

1

T11

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

30

1

T122

3

T340

2

T274

6

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

48

1

T2

1

T32

1

T349

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

42

1

T2

5

T11

1

T175

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

24

1

T268

3

T280

1

T363

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

36

1

T122

3

T95

4

T280

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

8

1

T6

1

T336

2

T275

3

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

134

1

T9

3

T47

1

T175

14

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

65

1

T2

7

T93

6

T340

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

46

1

T141

4

T260

1

T344

4

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

26

1

T119

4

T338

5

T370

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

57

1

T268

6

T91

3

T93

6

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

29

1

T43

3

T33

8

T142

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

36

1

T72

7

T287

1

T280

4

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

10

1

T122

2

T109

1

T339

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

72

1

T90

5

T338

9

T337

9

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

20

1

T33

8

T260

4

T271

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

68

1

T337

3

T270

1

T344

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

6

1

T95

2

T358

1

T149

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

35

1

T88

6

T337

4

T344

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

13

1

T2

1

T109

1

T371

3

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

9

1

T287

2

T269

3

T341

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

8

1

T269

1

T98

1

T339

3

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded