Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1045

1

T23

12

T67

10

T227

9

auto[1]

969

1

T23

8

T67

10

T227

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

479

1

T23

6

T67

6

T227

5

from_0to1

482

1

T23

5

T67

5

T227

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1041

1

T23

9

T67

14

T227

13

auto[1]

973

1

T23

11

T67

6

T227

7

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1019

1

T23

10

T67

5

T227

8

auto[1]

995

1

T23

10

T67

15

T227

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

62

1

T227

2

T229

1

T49

1

auto[0]

from_1to0

auto[0]

auto[1]

68

1

T23

2

T67

1

T194

2

auto[0]

from_1to0

auto[1]

auto[0]

76

1

T23

1

T227

1

T229

2

auto[0]

from_1to0

auto[1]

auto[1]

68

1

T23

1

T67

1

T227

1

auto[0]

from_0to1

auto[0]

auto[0]

62

1

T67

1

T49

1

T194

1

auto[0]

from_0to1

auto[0]

auto[1]

70

1

T23

1

T67

1

T229

1

auto[0]

from_0to1

auto[1]

auto[0]

55

1

T23

2

T49

2

T194

5

auto[0]

from_0to1

auto[1]

auto[1]

57

1

T23

1

T67

1

T227

2

auto[1]

from_1to0

auto[0]

auto[0]

50

1

T67

1

T229

1

T49

3

auto[1]

from_1to0

auto[0]

auto[1]

51

1

T23

1

T67

2

T227

1

auto[1]

from_1to0

auto[1]

auto[0]

46

1

T23

1

T49

1

T194

1

auto[1]

from_1to0

auto[1]

auto[1]

58

1

T67

1

T49

2

T74

1

auto[1]

from_0to1

auto[0]

auto[0]

57

1

T227

2

T49

3

T194

1

auto[1]

from_0to1

auto[0]

auto[1]

54

1

T23

1

T227

1

T49

1

auto[1]

from_0to1

auto[1]

auto[0]

60

1

T229

2

T49

1

T127

1

auto[1]

from_0to1

auto[1]

auto[1]

67

1

T67

2

T227

1

T229

3

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

996

1

T23

9

T67

9

T227

11

auto[1]

1018

1

T23

11

T67

11

T227

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

501

1

T23

5

T67

5

T227

4

from_0to1

499

1

T23

5

T67

6

T227

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1031

1

T23

9

T67

10

T227

16

auto[1]

983

1

T23

11

T67

10

T227

4

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

986

1

T23

16

T67

6

T227

8

auto[1]

1028

1

T23

4

T67

14

T227

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

55

1

T67

1

T49

1

T194

2

auto[0]

from_1to0

auto[0]

auto[1]

74

1

T227

1

T194

2

T74

1

auto[0]

from_1to0

auto[1]

auto[0]

59

1

T23

3

T229

1

T49

3

auto[0]

from_1to0

auto[1]

auto[1]

43

1

T67

1

T227

1

T229

1

auto[0]

from_0to1

auto[0]

auto[0]

70

1

T23

1

T229

2

T49

1

auto[0]

from_0to1

auto[0]

auto[1]

59

1

T67

1

T227

2

T194

3

auto[0]

from_0to1

auto[1]

auto[0]

56

1

T23

2

T229

1

T49

1

auto[0]

from_0to1

auto[1]

auto[1]

63

1

T67

1

T49

1

T194

1

auto[1]

from_1to0

auto[0]

auto[0]

68

1

T67

2

T227

1

T49

1

auto[1]

from_1to0

auto[0]

auto[1]

74

1

T23

1

T67

1

T227

1

auto[1]

from_1to0

auto[1]

auto[0]

66

1

T23

1

T229

2

T49

2

auto[1]

from_1to0

auto[1]

auto[1]

62

1

T229

2

T49

1

T194

1

auto[1]

from_0to1

auto[0]

auto[0]

69

1

T67

1

T227

1

T229

1

auto[1]

from_0to1

auto[0]

auto[1]

69

1

T227

2

T49

1

T140

1

auto[1]

from_0to1

auto[1]

auto[0]

51

1

T23

2

T229

1

T49

1

auto[1]

from_0to1

auto[1]

auto[1]

62

1

T67

3

T229

2

T49

3

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1013

1

T23

13

T67

13

T227

12

auto[1]

1001

1

T23

7

T67

7

T227

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

474

1

T23

4

T67

4

T227

6

from_0to1

479

1

T23

4

T67

4

T227

7

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1026

1

T23

11

T67

10

T227

11

auto[1]

988

1

T23

9

T67

10

T227

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

975

1

T23

9

T67

8

T227

8

auto[1]

1039

1

T23

11

T67

12

T227

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

59

1

T227

1

T49

1

T194

1

auto[0]

from_1to0

auto[0]

auto[1]

66

1

T23

2

T67

1

T229

1

auto[0]

from_1to0

auto[1]

auto[0]

50

1

T67

1

T49

1

T194

1

auto[0]

from_1to0

auto[1]

auto[1]

57

1

T67

1

T227

2

T49

2

auto[0]

from_0to1

auto[0]

auto[0]

71

1

T23

1

T67

1

T227

2

auto[0]

from_0to1

auto[0]

auto[1]

72

1

T23

1

T67

1

T227

1

auto[0]

from_0to1

auto[1]

auto[0]

58

1

T227

1

T229

2

T194

1

auto[0]

from_0to1

auto[1]

auto[1]

49

1

T23

1

T49

4

T194

1

auto[1]

from_1to0

auto[0]

auto[0]

59

1

T67

1

T49

1

T194

2

auto[1]

from_1to0

auto[0]

auto[1]

57

1

T23

1

T227

2

T229

1

auto[1]

from_1to0

auto[1]

auto[0]

48

1

T23

1

T227

1

T229

1

auto[1]

from_1to0

auto[1]

auto[1]

78

1

T49

4

T194

2

T63

3

auto[1]

from_0to1

auto[0]

auto[0]

55

1

T67

1

T49

2

T194

1

auto[1]

from_0to1

auto[0]

auto[1]

69

1

T67

1

T49

1

T74

1

auto[1]

from_0to1

auto[1]

auto[0]

50

1

T23

1

T194

1

T127

2

auto[1]

from_0to1

auto[1]

auto[1]

55

1

T227

3

T49

1

T194

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

962

1

T23

6

T67

8

T227

10

auto[1]

1052

1

T23

14

T67

12

T227

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

509

1

T23

6

T67

4

T227

4

from_0to1

502

1

T23

7

T67

3

T227

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

972

1

T23

9

T67

8

T227

14

auto[1]

1042

1

T23

11

T67

12

T227

6

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1016

1

T23

12

T67

8

T227

10

auto[1]

998

1

T23

8

T67

12

T227

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

61

1

T74

1

T140

2

T314

1

auto[0]

from_1to0

auto[0]

auto[1]

60

1

T227

2

T194

2

T140

1

auto[0]

from_1to0

auto[1]

auto[0]

60

1

T23

1

T229

2

T194

1

auto[0]

from_1to0

auto[1]

auto[1]

68

1

T67

1

T227

1

T194

2

auto[0]

from_0to1

auto[0]

auto[0]

65

1

T23

2

T194

1

T127

1

auto[0]

from_0to1

auto[0]

auto[1]

47

1

T67

1

T227

1

T194

2

auto[0]

from_0to1

auto[1]

auto[0]

63

1

T23

1

T227

1

T127

2

auto[0]

from_0to1

auto[1]

auto[1]

53

1

T23

1

T67

1

T227

1

auto[1]

from_1to0

auto[0]

auto[0]

49

1

T23

1

T227

1

T49

2

auto[1]

from_1to0

auto[0]

auto[1]

54

1

T49

1

T127

3

T140

1

auto[1]

from_1to0

auto[1]

auto[0]

79

1

T23

2

T67

2

T49

1

auto[1]

from_1to0

auto[1]

auto[1]

78

1

T23

2

T67

1

T229

1

auto[1]

from_0to1

auto[0]

auto[0]

71

1

T23

1

T227

1

T49

2

auto[1]

from_0to1

auto[0]

auto[1]

69

1

T227

1

T229

1

T49

2

auto[1]

from_0to1

auto[1]

auto[0]

60

1

T67

1

T49

1

T194

1

auto[1]

from_0to1

auto[1]

auto[1]

74

1

T23

2

T229

1

T194

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

967

1

T23

9

T67

13

T227

8

auto[1]

1047

1

T23

11

T67

7

T227

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

499

1

T23

6

T67

6

T227

3

from_0to1

496

1

T23

5

T67

6

T227

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

996

1

T23

8

T67

14

T227

6

auto[1]

1018

1

T23

12

T67

6

T227

14

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1016

1

T23

11

T67

13

T227

6

auto[1]

998

1

T23

9

T67

7

T227

14

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

56

1

T67

2

T229

2

T49

1

auto[0]

from_1to0

auto[0]

auto[1]

67

1

T23

1

T67

1

T49

2

auto[0]

from_1to0

auto[1]

auto[0]

67

1

T23

1

T67

2

T49

1

auto[0]

from_1to0

auto[1]

auto[1]

64

1

T229

1

T74

1

T140

1

auto[0]

from_0to1

auto[0]

auto[0]

47

1

T23

1

T194

1

T127

1

auto[0]

from_0to1

auto[0]

auto[1]

61

1

T67

1

T49

1

T74

1

auto[0]

from_0to1

auto[1]

auto[0]

44

1

T67

1

T229

1

T194

1

auto[0]

from_0to1

auto[1]

auto[1]

61

1

T23

1

T229

2

T49

2

auto[1]

from_1to0

auto[0]

auto[0]

65

1

T194

1

T74

1

T140

1

auto[1]

from_1to0

auto[0]

auto[1]

56

1

T194

2

T127

1

T74

1

auto[1]

from_1to0

auto[1]

auto[0]

58

1

T23

3

T67

1

T227

1

auto[1]

from_1to0

auto[1]

auto[1]

66

1

T23

1

T227

2

T229

1

auto[1]

from_0to1

auto[0]

auto[0]

75

1

T23

1

T67

3

T49

1

auto[1]

from_0to1

auto[0]

auto[1]

66

1

T227

1

T49

1

T194

3

auto[1]

from_0to1

auto[1]

auto[0]

76

1

T229

1

T49

2

T194

3

auto[1]

from_0to1

auto[1]

auto[1]

66

1

T23

2

T67

1

T227

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1042

1

T23

10

T67

7

T227

13

auto[1]

972

1

T23

10

T67

13

T227

7

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

501

1

T23

5

T67

5

T227

3

from_0to1

494

1

T23

4

T67

4

T227

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

967

1

T23

10

T67

12

T227

8

auto[1]

1047

1

T23

10

T67

8

T227

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

971

1

T23

11

T67

13

T227

13

auto[1]

1043

1

T23

9

T67

7

T227

7

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

58

1

T23

1

T67

1

T49

1

auto[0]

from_1to0

auto[0]

auto[1]

57

1

T23

1

T229

1

T49

2

auto[0]

from_1to0

auto[1]

auto[0]

66

1

T227

2

T229

1

T194

1

auto[0]

from_1to0

auto[1]

auto[1]

74

1

T23

1

T67

1

T227

1

auto[0]

from_0to1

auto[0]

auto[0]

50

1

T229

1

T194

1

T74

1

auto[0]

from_0to1

auto[0]

auto[1]

75

1

T67

1

T194

2

T74

2

auto[0]

from_0to1

auto[1]

auto[0]

67

1

T23

1

T227

2

T49

1

auto[0]

from_0to1

auto[1]

auto[1]

67

1

T23

2

T227

1

T194

1

auto[1]

from_1to0

auto[0]

auto[0]

64

1

T23

2

T67

2

T140

2

auto[1]

from_1to0

auto[0]

auto[1]

60

1

T67

1

T127

1

T74

1

auto[1]

from_1to0

auto[1]

auto[0]

58

1

T229

2

T194

1

T127

2

auto[1]

from_1to0

auto[1]

auto[1]

64

1

T49

3

T194

2

T75

1

auto[1]

from_0to1

auto[0]

auto[0]

55

1

T67

2

T227

1

T49

2

auto[1]

from_0to1

auto[0]

auto[1]

49

1

T229

1

T49

2

T127

1

auto[1]

from_0to1

auto[1]

auto[0]

57

1

T229

1

T194

1

T74

1

auto[1]

from_0to1

auto[1]

auto[1]

74

1

T23

1

T67

1

T229

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1012

1

T23

9

T67

11

T227

7

auto[1]

1002

1

T23

11

T67

9

T227

13

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

482

1

T23

6

T67

7

T227

6

from_0to1

474

1

T23

7

T67

6

T227

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1024

1

T23

13

T67

12

T227

8

auto[1]

990

1

T23

7

T67

8

T227

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1004

1

T23

13

T67

11

T227

6

auto[1]

1010

1

T23

7

T67

9

T227

14

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

66

1

T23

3

T67

1

T229

2

auto[0]

from_1to0

auto[0]

auto[1]

60

1

T67

1

T227

1

T49

1

auto[0]

from_1to0

auto[1]

auto[0]

61

1

T49

2

T140

1

T314

1

auto[0]

from_1to0

auto[1]

auto[1]

65

1

T67

2

T227

2

T127

1

auto[0]

from_0to1

auto[0]

auto[0]

67

1

T23

2

T67

3

T49

3

auto[0]

from_0to1

auto[0]

auto[1]

49

1

T23

1

T49

1

T194

1

auto[0]

from_0to1

auto[1]

auto[0]

50

1

T227

1

T49

1

T194

1

auto[0]

from_0to1

auto[1]

auto[1]

60

1

T227

2

T49

1

T194

4

auto[1]

from_1to0

auto[0]

auto[0]

58

1

T23

1

T229

1

T49

1

auto[1]

from_1to0

auto[0]

auto[1]

56

1

T67

3

T227

1

T229

1

auto[1]

from_1to0

auto[1]

auto[0]

60

1

T23

1

T227

2

T49

2

auto[1]

from_1to0

auto[1]

auto[1]

56

1

T23

1

T229

1

T151

1

auto[1]

from_0to1

auto[0]

auto[0]

70

1

T23

1

T67

1

T229

2

auto[1]

from_0to1

auto[0]

auto[1]

59

1

T23

2

T227

1

T229

1

auto[1]

from_0to1

auto[1]

auto[0]

56

1

T67

1

T227

1

T49

2

auto[1]

from_0to1

auto[1]

auto[1]

63

1

T23

1

T67

1

T229

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

979

1

T23

7

T67

8

T227

10

auto[1]

1035

1

T23

13

T67

12

T227

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

481

1

T23

4

T67

4

T227

4

from_0to1

474

1

T23

4

T67

4

T227

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

983

1

T23

8

T67

9

T227

10

auto[1]

1031

1

T23

12

T67

11

T227

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1023

1

T23

12

T67

12

T227

11

auto[1]

991

1

T23

8

T67

8

T227

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

54

1

T229

2

T49

2

T194

3

auto[0]

from_1to0

auto[0]

auto[1]

54

1

T23

2

T67

1

T229

2

auto[0]

from_1to0

auto[1]

auto[0]

56

1

T67

1

T227

1

T49

1

auto[0]

from_1to0

auto[1]

auto[1]

67

1

T23

1

T49

4

T194

2

auto[0]

from_0to1

auto[0]

auto[0]

58

1

T67

2

T227

1

T194

1

auto[0]

from_0to1

auto[0]

auto[1]

43

1

T49

1

T194

1

T127

1

auto[0]

from_0to1

auto[1]

auto[0]

65

1

T67

1

T227

1

T229

1

auto[0]

from_0to1

auto[1]

auto[1]

53

1

T67

1

T49

2

T194

2

auto[1]

from_1to0

auto[0]

auto[0]

69

1

T67

1

T229

1

T49

2

auto[1]

from_1to0

auto[0]

auto[1]

62

1

T23

1

T227

1

T194

3

auto[1]

from_1to0

auto[1]

auto[0]

57

1

T49

1

T140

1

T151

1

auto[1]

from_1to0

auto[1]

auto[1]

62

1

T67

1

T227

2

T49

1

auto[1]

from_0to1

auto[0]

auto[0]

60

1

T227

2

T229

2

T49

1

auto[1]

from_0to1

auto[0]

auto[1]

56

1

T229

1

T49

1

T194

1

auto[1]

from_0to1

auto[1]

auto[0]

72

1

T23

2

T227

1

T229

1

auto[1]

from_0to1

auto[1]

auto[1]

67

1

T23

2

T49

2

T194

1