Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	158413	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

123277

1

T5

2

T1

3

T2

491

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	142342	1			T5	2		T1	7		T2	817
values[0x0]	69195	1			T5	4		T1	4		T2	84
values[0x1]	70153	1			T1	1		T2	91		T12	30

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	128703	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

152987

1

T5

2

T1

4

T2

591

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1192	1			T2	2		T3	2		T7	7
valid_sources[0x01]	1084	1			T2	5		T15	3		T6	2
valid_sources[0x02]	1116	1			T2	10		T3	2		T15	2
valid_sources[0x03]	915	1			T2	1		T25	2		T7	4
valid_sources[0x04]	960	1			T2	5		T25	2		T6	1
valid_sources[0x05]	1720	1			T2	10		T3	1		T6	1
valid_sources[0x06]	904	1			T25	2		T66	1		T10	16
valid_sources[0x07]	889	1			T2	6		T25	1		T6	1
valid_sources[0x08]	849	1			T3	1		T25	3		T23	10
valid_sources[0x09]	1041	1			T2	1		T13	3		T6	1
valid_sources[0x0a]	910	1			T2	3		T3	1		T6	3
valid_sources[0x0b]	960	1			T2	7		T3	1		T14	1
valid_sources[0x0c]	920	1			T2	4		T3	1		T25	11
valid_sources[0x0d]	987	1			T2	7		T3	1		T6	2
valid_sources[0x0e]	831	1			T2	3		T3	3		T6	1
valid_sources[0x0f]	852	1			T2	1		T3	6		T25	7
valid_sources[0x10]	1297	1			T2	2		T25	4		T6	1
valid_sources[0x11]	2164	1			T2	17		T3	1		T6	1
valid_sources[0x12]	1835	1			T2	6		T3	2		T6	1
valid_sources[0x13]	1087	1			T2	6		T6	1		T120	6
valid_sources[0x14]	1196	1			T2	7		T3	1		T6	1
valid_sources[0x15]	1668	1			T2	8		T13	1		T25	2
valid_sources[0x16]	950	1			T2	4		T3	4		T14	1
valid_sources[0x17]	879	1			T2	2		T3	3		T25	5
valid_sources[0x18]	1247	1			T2	5		T3	2		T25	6
valid_sources[0x19]	866	1			T2	2		T3	1		T25	4
valid_sources[0x1a]	854	1			T2	10		T66	1		T67	1
valid_sources[0x1b]	918	1			T2	11		T3	2		T14	1
valid_sources[0x1c]	912	1			T2	6		T3	1		T6	1
valid_sources[0x1d]	1004	1			T3	2		T6	1		T7	14
valid_sources[0x1e]	835	1			T3	2		T25	1		T6	4
valid_sources[0x1f]	1090	1			T2	7		T3	3		T14	1
valid_sources[0x20]	838	1			T2	1		T3	3		T6	1
valid_sources[0x21]	1767	1			T2	1		T3	1		T25	4
valid_sources[0x22]	1054	1			T2	3		T3	1		T6	1
valid_sources[0x23]	968	1			T2	7		T25	2		T6	1
valid_sources[0x24]	1119	1			T2	9		T14	1		T15	1
valid_sources[0x25]	817	1			T2	1		T6	6		T7	1
valid_sources[0x26]	825	1			T2	7		T7	4		T10	4
valid_sources[0x27]	2213	1			T2	8		T3	1		T25	4
valid_sources[0x28]	1154	1			T2	8		T3	1		T66	1
valid_sources[0x29]	2232	1			T2	14		T3	4		T15	1
valid_sources[0x2a]	864	1			T2	7		T3	4		T10	7
valid_sources[0x2b]	981	1			T2	1		T25	3		T10	5
valid_sources[0x2c]	1451	1			T2	2		T25	3		T6	6
valid_sources[0x2d]	825	1			T25	2		T7	3		T120	4
valid_sources[0x2e]	1077	1			T5	1		T3	2		T15	5
valid_sources[0x2f]	1713	1			T2	2		T3	2		T67	1
valid_sources[0x30]	872	1			T2	5		T13	2		T3	5
valid_sources[0x31]	856	1			T2	4		T3	1		T25	9
valid_sources[0x32]	775	1			T2	6		T3	3		T10	2
valid_sources[0x33]	978	1			T25	2		T6	1		T7	3
valid_sources[0x34]	1744	1			T2	2		T14	1		T25	2
valid_sources[0x35]	971	1			T2	1		T3	2		T51	1
valid_sources[0x36]	852	1			T2	6		T3	2		T50	1
valid_sources[0x37]	862	1			T2	3		T3	2		T67	2
valid_sources[0x38]	893	1			T2	2		T3	8		T15	2
valid_sources[0x39]	808	1			T2	1		T3	1		T50	1
valid_sources[0x3a]	847	1			T15	2		T66	1		T41	4
valid_sources[0x3b]	1139	1			T2	1		T3	5		T6	2
valid_sources[0x3c]	991	1			T2	5		T14	1		T6	2
valid_sources[0x3d]	1425	1			T15	2		T25	5		T50	1
valid_sources[0x3e]	909	1			T2	7		T3	6		T14	2
valid_sources[0x3f]	962	1			T2	9		T67	1		T10	2
valid_sources[0x40]	971	1			T2	4		T3	2		T25	3
valid_sources[0x41]	829	1			T2	5		T3	2		T14	1
valid_sources[0x42]	2818	1			T3	2		T25	4		T7	2
valid_sources[0x43]	1253	1			T2	3		T25	9		T6	4
valid_sources[0x44]	991	1			T2	4		T3	1		T25	1
valid_sources[0x45]	841	1			T2	3		T3	1		T14	1
valid_sources[0x46]	1025	1			T2	1		T7	14		T66	1
valid_sources[0x47]	974	1			T2	1		T3	3		T6	2
valid_sources[0x48]	1165	1			T3	2		T25	4		T6	1
valid_sources[0x49]	941	1			T25	1		T6	1		T10	2
valid_sources[0x4a]	862	1			T2	10		T30	3		T124	12
valid_sources[0x4b]	898	1			T2	7		T25	3		T65	1
valid_sources[0x4c]	975	1			T2	1		T3	1		T14	1
valid_sources[0x4d]	862	1			T25	4		T7	2		T30	1
valid_sources[0x4e]	939	1			T3	1		T10	11		T70	2
valid_sources[0x4f]	853	1			T2	7		T16	4		T25	1
valid_sources[0x50]	956	1			T25	2		T6	1		T7	10
valid_sources[0x51]	1194	1			T2	4		T3	2		T14	1
valid_sources[0x52]	828	1			T2	8		T3	2		T25	3
valid_sources[0x53]	916	1			T2	7		T3	1		T15	3
valid_sources[0x54]	903	1			T3	2		T6	2		T23	5
valid_sources[0x55]	964	1			T2	1		T25	2		T6	2
valid_sources[0x56]	876	1			T2	6		T6	1		T125	3
valid_sources[0x57]	1017	1			T2	3		T14	1		T25	4
valid_sources[0x58]	862	1			T3	1		T25	1		T6	2
valid_sources[0x59]	1121	1			T2	14		T25	1		T67	1
valid_sources[0x5a]	1160	1			T6	2		T7	1		T10	3
valid_sources[0x5b]	834	1			T2	2		T7	3		T23	5
valid_sources[0x5c]	982	1			T2	1		T6	1		T7	2
valid_sources[0x5d]	1293	1			T3	1		T14	1		T25	1
valid_sources[0x5e]	1012	1			T2	7		T3	1		T25	1
valid_sources[0x5f]	1050	1			T2	5		T25	3		T6	4
valid_sources[0x60]	841	1			T2	8		T3	1		T25	1
valid_sources[0x61]	858	1			T2	4		T3	2		T14	1
valid_sources[0x62]	929	1			T3	1		T25	3		T65	5
valid_sources[0x63]	1179	1			T2	2		T3	2		T6	1
valid_sources[0x64]	1007	1			T3	1		T10	1		T46	2
valid_sources[0x65]	1163	1			T2	3		T25	2		T7	3
valid_sources[0x66]	1704	1			T2	5		T7	7		T66	1
valid_sources[0x67]	1368	1			T6	1		T23	7		T67	1
valid_sources[0x68]	1191	1			T2	5		T3	1		T7	1
valid_sources[0x69]	1080	1			T2	5		T3	1		T6	1
valid_sources[0x6a]	949	1			T3	4		T25	2		T7	12
valid_sources[0x6b]	948	1			T2	3		T8	1		T65	3
valid_sources[0x6c]	1369	1			T2	1		T3	1		T25	2
valid_sources[0x6d]	1039	1			T2	1		T14	1		T6	3
valid_sources[0x6e]	1414	1			T2	2		T25	3		T6	2
valid_sources[0x6f]	728	1			T2	3		T6	1		T7	10
valid_sources[0x70]	941	1			T2	4		T3	1		T25	3
valid_sources[0x71]	1323	1			T2	2		T3	2		T14	1
valid_sources[0x72]	975	1			T2	1		T15	6		T25	7
valid_sources[0x73]	824	1			T2	2		T14	1		T50	1
valid_sources[0x74]	841	1			T2	2		T3	1		T25	5
valid_sources[0x75]	955	1			T2	7		T3	1		T25	6
valid_sources[0x76]	1060	1			T2	2		T3	1		T25	3
valid_sources[0x77]	1031	1			T3	4		T14	1		T25	5
valid_sources[0x78]	890	1			T2	3		T25	3		T6	1
valid_sources[0x79]	1971	1			T2	7		T3	1		T6	1
valid_sources[0x7a]	1135	1			T5	1		T2	1		T3	1
valid_sources[0x7b]	1009	1			T2	8		T3	2		T25	2
valid_sources[0x7c]	852	1			T2	6		T65	1		T10	2
valid_sources[0x7d]	1314	1			T3	1		T6	2		T7	5
valid_sources[0x7e]	1055	1			T2	3		T25	3		T66	2
valid_sources[0x7f]	1186	1			T2	5		T14	1		T25	4
valid_sources[0x80]	847	1			T2	6		T25	2		T6	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

65134

1

T5

1

T1

3

T2

421

values[0x0]

all_enables

biggest_size

34031

1

T5

1

T2

45

T12

10

values[0x1]

all_enables

biggest_size

24112

1

T2

25

T12

5

T13

1