Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.41	93.48	95.24		83.33	90.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.41	93.48	95.24		83.33	90.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T12,T3
1	Covered	T5,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T12,T3
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T3,T17,T41

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T2	VC_COV_UNR
1	Covered	T3,T17,T41

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T17,T42,T44

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T17,T41
1	0	Covered	T2,T12,T3
1	1	Covered	T3,T17,T41

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T17,T42,T44
0	1	Covered	T96
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T17,T42,T44
0	1	Covered	T17,T42,T44
1	0	Covered	T52

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T17,T42,T44
1	-	Covered	T17,T42,T44

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T17,T41
DetectSt	168	Covered	T17,T42,T44
IdleSt	163	Covered	T5,T1,T2
StableSt	191	Covered	T17,T42,T44

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T17,T42,T44
DebounceSt->IdleSt	163	Covered	T3,T41,T49
DetectSt->IdleSt	186	Covered	T96
DetectSt->StableSt	191	Covered	T17,T42,T44
IdleSt->DebounceSt	148	Covered	T3,T17,T41
StableSt->IdleSt	206	Covered	T17,T42,T44

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T17,T41
0	1	Covered	T3,T17,T41
0	0	Excluded	T5,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T17,T42,T44
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T17,T41
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T3
DebounceSt	-	0	1	1	-	-	-	Covered	T17,T42,T44
DebounceSt	-	0	1	0	-	-	-	Covered	T41,T49,T127
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T17,T41
DetectSt	-	-	-	-	1	-	-	Covered	T96
DetectSt	-	-	-	-	0	1	-	Covered	T17,T42,T44
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T17,T42,T44
StableSt	-	-	-	-	-	-	0	Covered	T17,T42,T44
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5804184	310	0	0
CntIncr_A	5804184	355670	0	0
CntNoWrap_A	5804184	5190996	0	0
DetectStDropOut_A	5804184	1	0	0
DetectedOut_A	5804184	950	0	0
DetectedPulseOut_A	5804184	139	0	0
DisabledIdleSt_A	5804184	4828461	0	0
DisabledNoDetection_A	5804184	4830676	0	0
EnterDebounceSt_A	5804184	174	0	0
EnterDetectSt_A	5804184	140	0	0
EnterStableSt_A	5804184	139	0	0
PulseIsPulse_A	5804184	139	0	0
StayInStableSt	5804184	811	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5804184	6832	0	0
gen_low_level_sva.LowLevelEvent_A	5804184	5193579	0	0
gen_not_sticky_sva.StableStDropOut_A	5804184	138	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	310	0	0
T3	7662	1	0	0
T4	707	0	0	0
T6	8924	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	2	0	0
T25	5118	0	0	0
T40	0	2	0	0
T41	0	1	0	0
T42	0	4	0	0
T44	0	2	0	0
T45	0	4	0	0
T48	0	4	0	0
T49	0	3	0	0
T50	402	0	0	0
T51	604	0	0	0
T87	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	355670	0	0
T3	7662	32	0	0
T4	707	0	0	0
T6	8924	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	62	0	0
T25	5118	0	0	0
T40	0	10	0	0
T41	0	71	0	0
T42	0	155	0	0
T44	0	97	0	0
T45	0	153	0	0
T48	0	141	0	0
T49	0	141	0	0
T50	402	0	0	0
T51	604	0	0	0
T87	0	45	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	5190996	0	0
T1	486	85	0	0
T2	25810	24162	0	0
T3	7662	7260	0	0
T5	402	1	0	0
T12	527	126	0	0
T13	404	3	0	0
T14	493	92	0	0
T15	526	125	0	0
T16	406	5	0	0
T17	718	315	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	1	0	0
T96	71725	1	0	0
T97	5370	0	0	0
T109	12950	0	0	0
T110	784	0	0	0
T111	506	0	0	0
T112	16778	0	0	0
T113	670	0	0	0
T114	8854	0	0	0
T115	677	0	0	0
T116	403	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	950	0	0
T4	707	0	0	0
T6	8924	0	0	0
T7	8003	0	0	0
T17	718	5	0	0
T23	508	0	0	0
T25	5118	0	0	0
T30	1065	0	0	0
T40	0	5	0	0
T42	0	23	0	0
T44	0	4	0	0
T45	0	7	0	0
T48	0	16	0	0
T49	0	8	0	0
T50	402	0	0	0
T51	604	0	0	0
T87	0	3	0	0
T117	0	15	0	0
T118	0	10	0	0
T120	438	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	139	0	0
T4	707	0	0	0
T6	8924	0	0	0
T7	8003	0	0	0
T17	718	1	0	0
T23	508	0	0	0
T25	5118	0	0	0
T30	1065	0	0	0
T40	0	1	0	0
T42	0	2	0	0
T44	0	1	0	0
T45	0	2	0	0
T48	0	2	0	0
T49	0	1	0	0
T50	402	0	0	0
T51	604	0	0	0
T87	0	1	0	0
T117	0	2	0	0
T118	0	1	0	0
T120	438	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	4828461	0	0
T1	486	85	0	0
T2	25810	24162	0	0
T3	7662	7223	0	0
T5	402	1	0	0
T12	527	126	0	0
T13	404	3	0	0
T14	493	92	0	0
T15	526	125	0	0
T16	406	5	0	0
T17	718	202	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	4830676	0	0
T1	486	86	0	0
T2	25810	24171	0	0
T3	7662	7224	0	0
T5	402	2	0	0
T12	527	127	0	0
T13	404	4	0	0
T14	493	93	0	0
T15	526	126	0	0
T16	406	6	0	0
T17	718	203	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	174	0	0
T3	7662	1	0	0
T4	707	0	0	0
T6	8924	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	1	0	0
T25	5118	0	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	2	0	0
T44	0	1	0	0
T45	0	2	0	0
T48	0	2	0	0
T49	0	2	0	0
T50	402	0	0	0
T51	604	0	0	0
T87	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	140	0	0
T4	707	0	0	0
T6	8924	0	0	0
T7	8003	0	0	0
T17	718	1	0	0
T23	508	0	0	0
T25	5118	0	0	0
T30	1065	0	0	0
T40	0	1	0	0
T42	0	2	0	0
T44	0	1	0	0
T45	0	2	0	0
T48	0	2	0	0
T49	0	1	0	0
T50	402	0	0	0
T51	604	0	0	0
T87	0	1	0	0
T117	0	2	0	0
T118	0	1	0	0
T120	438	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	139	0	0
T4	707	0	0	0
T6	8924	0	0	0
T7	8003	0	0	0
T17	718	1	0	0
T23	508	0	0	0
T25	5118	0	0	0
T30	1065	0	0	0
T40	0	1	0	0
T42	0	2	0	0
T44	0	1	0	0
T45	0	2	0	0
T48	0	2	0	0
T49	0	1	0	0
T50	402	0	0	0
T51	604	0	0	0
T87	0	1	0	0
T117	0	2	0	0
T118	0	1	0	0
T120	438	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	139	0	0
T4	707	0	0	0
T6	8924	0	0	0
T7	8003	0	0	0
T17	718	1	0	0
T23	508	0	0	0
T25	5118	0	0	0
T30	1065	0	0	0
T40	0	1	0	0
T42	0	2	0	0
T44	0	1	0	0
T45	0	2	0	0
T48	0	2	0	0
T49	0	1	0	0
T50	402	0	0	0
T51	604	0	0	0
T87	0	1	0	0
T117	0	2	0	0
T118	0	1	0	0
T120	438	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	811	0	0
T4	707	0	0	0
T6	8924	0	0	0
T7	8003	0	0	0
T17	718	4	0	0
T23	508	0	0	0
T25	5118	0	0	0
T30	1065	0	0	0
T40	0	4	0	0
T42	0	21	0	0
T44	0	3	0	0
T45	0	5	0	0
T48	0	14	0	0
T49	0	7	0	0
T50	402	0	0	0
T51	604	0	0	0
T87	0	2	0	0
T117	0	13	0	0
T118	0	9	0	0
T120	438	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	6832	0	0
T2	25810	20	0	0
T3	7662	23	0	0
T4	707	0	0	0
T6	0	8	0	0
T7	0	21	0	0
T12	527	5	0	0
T13	404	0	0	0
T14	493	7	0	0
T15	526	4	0	0
T16	406	0	0	0
T17	718	3	0	0
T25	5118	25	0	0
T30	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	5193579	0	0
T1	486	86	0	0
T2	25810	24171	0	0
T3	7662	7262	0	0
T5	402	2	0	0
T12	527	127	0	0
T13	404	4	0	0
T14	493	93	0	0
T15	526	126	0	0
T16	406	6	0	0
T17	718	318	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	138	0	0
T4	707	0	0	0
T6	8924	0	0	0
T7	8003	0	0	0
T17	718	1	0	0
T23	508	0	0	0
T25	5118	0	0	0
T30	1065	0	0	0
T40	0	1	0	0
T42	0	2	0	0
T44	0	1	0	0
T45	0	2	0	0
T48	0	2	0	0
T49	0	1	0	0
T50	402	0	0	0
T51	604	0	0	0
T87	0	1	0	0
T117	0	2	0	0
T118	0	1	0	0
T120	438	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T12,T3
1	Covered	T5,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T12,T3
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T3,T8,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T2	VC_COV_UNR
1	Covered	T3,T8,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T8,T31,T57

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T11
1	0	Covered	T2,T12,T3
1	1	Covered	T3,T8,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T31,T57
0	1	Covered	T57,T84,T85
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T31,T57
0	1	Unreachable
1	0	Covered	T8,T31,T57

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T8,T11
DetectSt	168	Covered	T8,T31,T57
IdleSt	163	Covered	T5,T1,T2
StableSt	191	Covered	T8,T31,T57

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T31,T57
DebounceSt->IdleSt	163	Covered	T3,T11,T74
DetectSt->IdleSt	186	Covered	T57,T84,T85
DetectSt->StableSt	191	Covered	T8,T31,T57
IdleSt->DebounceSt	148	Covered	T3,T8,T11
StableSt->IdleSt	206	Covered	T8,T31,T57

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T8,T11
0	1	Covered	T3,T8,T11
0	0	Excluded	T5,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T31,T57
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T8,T11
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T3,T52
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T31,T57
DebounceSt	-	0	1	0	-	-	-	Covered	T11,T74,T78
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T8,T11
DetectSt	-	-	-	-	1	-	-	Covered	T57,T84,T85
DetectSt	-	-	-	-	0	1	-	Covered	T8,T31,T57
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T31,T57
StableSt	-	-	-	-	-	-	0	Covered	T8,T31,T57
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5804184	154	0	0
CntIncr_A	5804184	60614	0	0
CntNoWrap_A	5804184	5191152	0	0
DetectStDropOut_A	5804184	7	0	0
DetectedOut_A	5804184	132822	0	0
DetectedPulseOut_A	5804184	56	0	0
DisabledIdleSt_A	5804184	4396525	0	0
DisabledNoDetection_A	5804184	4398797	0	0
EnterDebounceSt_A	5804184	92	0	0
EnterDetectSt_A	5804184	63	0	0
EnterStableSt_A	5804184	56	0	0
PulseIsPulse_A	5804184	56	0	0
StayInStableSt	5804184	132766	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5804184	6832	0	0
gen_low_level_sva.LowLevelEvent_A	5804184	5193579	0	0
gen_sticky_sva.StableStDropOut_A	5804184	597546	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	154	0	0
T3	7662	1	0	0
T4	707	0	0	0
T6	8924	0	0	0
T8	0	2	0	0
T11	0	1	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T31	0	2	0	0
T50	402	0	0	0
T51	604	0	0	0
T57	0	6	0	0
T74	0	3	0	0
T75	0	2	0	0
T76	0	2	0	0
T77	0	2	0	0
T78	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	60614	0	0
T3	7662	27	0	0
T4	707	0	0	0
T6	8924	0	0	0
T8	0	78	0	0
T11	0	82	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T31	0	79	0	0
T50	402	0	0	0
T51	604	0	0	0
T57	0	270	0	0
T74	0	186	0	0
T75	0	45	0	0
T76	0	97	0	0
T77	0	76	0	0
T78	0	296	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	5191152	0	0
T1	486	85	0	0
T2	25810	24162	0	0
T3	7662	7260	0	0
T5	402	1	0	0
T12	527	126	0	0
T13	404	3	0	0
T14	493	92	0	0
T15	526	125	0	0
T16	406	5	0	0
T17	718	317	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	7	0	0
T35	547	0	0	0
T36	4076	0	0	0
T37	478	0	0	0
T49	2964	0	0	0
T57	2075	2	0	0
T84	0	1	0	0
T85	0	1	0	0
T87	734	0	0	0
T128	0	3	0	0
T129	403	0	0	0
T130	772	0	0	0
T131	406	0	0	0
T132	1355	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	132822	0	0
T8	2340	376	0	0
T9	32017	0	0	0
T31	0	240	0	0
T53	518	0	0	0
T54	1436	0	0	0
T57	0	92	0	0
T65	535	0	0	0
T66	522	0	0	0
T74	0	188	0	0
T75	0	39	0	0
T76	0	19	0	0
T77	0	321	0	0
T82	0	122686	0	0
T83	0	420	0	0
T93	0	451	0	0
T121	426	0	0	0
T124	421	0	0	0
T125	405	0	0	0
T126	404	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	56	0	0
T8	2340	1	0	0
T9	32017	0	0	0
T31	0	1	0	0
T53	518	0	0	0
T54	1436	0	0	0
T57	0	1	0	0
T65	535	0	0	0
T66	522	0	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0
T77	0	1	0	0
T82	0	2	0	0
T83	0	1	0	0
T93	0	2	0	0
T121	426	0	0	0
T124	421	0	0	0
T125	405	0	0	0
T126	404	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	4396525	0	0
T1	486	85	0	0
T2	25810	24162	0	0
T3	7662	7227	0	0
T5	402	1	0	0
T12	527	126	0	0
T13	404	3	0	0
T14	493	92	0	0
T15	526	125	0	0
T16	406	5	0	0
T17	718	317	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	4398797	0	0
T1	486	86	0	0
T2	25810	24171	0	0
T3	7662	7227	0	0
T5	402	2	0	0
T12	527	127	0	0
T13	404	4	0	0
T14	493	93	0	0
T15	526	126	0	0
T16	406	6	0	0
T17	718	318	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	92	0	0
T3	7662	2	0	0
T4	707	0	0	0
T6	8924	0	0	0
T8	0	1	0	0
T11	0	1	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T31	0	1	0	0
T50	402	0	0	0
T51	604	0	0	0
T57	0	3	0	0
T74	0	2	0	0
T75	0	1	0	0
T76	0	1	0	0
T77	0	1	0	0
T78	0	4	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	63	0	0
T8	2340	1	0	0
T9	32017	0	0	0
T31	0	1	0	0
T53	518	0	0	0
T54	1436	0	0	0
T57	0	3	0	0
T65	535	0	0	0
T66	522	0	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0
T77	0	1	0	0
T82	0	2	0	0
T83	0	1	0	0
T93	0	2	0	0
T121	426	0	0	0
T124	421	0	0	0
T125	405	0	0	0
T126	404	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	56	0	0
T8	2340	1	0	0
T9	32017	0	0	0
T31	0	1	0	0
T53	518	0	0	0
T54	1436	0	0	0
T57	0	1	0	0
T65	535	0	0	0
T66	522	0	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0
T77	0	1	0	0
T82	0	2	0	0
T83	0	1	0	0
T93	0	2	0	0
T121	426	0	0	0
T124	421	0	0	0
T125	405	0	0	0
T126	404	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	56	0	0
T8	2340	1	0	0
T9	32017	0	0	0
T31	0	1	0	0
T53	518	0	0	0
T54	1436	0	0	0
T57	0	1	0	0
T65	535	0	0	0
T66	522	0	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0
T77	0	1	0	0
T82	0	2	0	0
T83	0	1	0	0
T93	0	2	0	0
T121	426	0	0	0
T124	421	0	0	0
T125	405	0	0	0
T126	404	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	132766	0	0
T8	2340	375	0	0
T9	32017	0	0	0
T31	0	239	0	0
T53	518	0	0	0
T54	1436	0	0	0
T57	0	91	0	0
T65	535	0	0	0
T66	522	0	0	0
T74	0	187	0	0
T75	0	38	0	0
T76	0	18	0	0
T77	0	320	0	0
T82	0	122684	0	0
T83	0	419	0	0
T93	0	449	0	0
T121	426	0	0	0
T124	421	0	0	0
T125	405	0	0	0
T126	404	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	6832	0	0
T2	25810	20	0	0
T3	7662	23	0	0
T4	707	0	0	0
T6	0	8	0	0
T7	0	21	0	0
T12	527	5	0	0
T13	404	0	0	0
T14	493	7	0	0
T15	526	4	0	0
T16	406	0	0	0
T17	718	3	0	0
T25	5118	25	0	0
T30	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	5193579	0	0
T1	486	86	0	0
T2	25810	24171	0	0
T3	7662	7262	0	0
T5	402	2	0	0
T12	527	127	0	0
T13	404	4	0	0
T14	493	93	0	0
T15	526	126	0	0
T16	406	6	0	0
T17	718	318	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	597546	0	0
T8	2340	374	0	0
T9	32017	0	0	0
T31	0	183	0	0
T53	518	0	0	0
T54	1436	0	0	0
T57	0	153	0	0
T65	535	0	0	0
T66	522	0	0	0
T74	0	192	0	0
T75	0	25	0	0
T76	0	46	0	0
T77	0	88	0	0
T82	0	121	0	0
T83	0	241683	0	0
T93	0	115	0	0
T121	426	0	0	0
T124	421	0	0	0
T125	405	0	0	0
T126	404	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T1,T2,T12

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T1,T2,T12
1	1	Covered	T1,T2,T12

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T3,T8,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T2	VC_COV_UNR
1	Covered	T3,T8,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T8,T31,T74

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T11
1	0	Covered	T1,T2,T12
1	1	Covered	T3,T8,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T31,T74
0	1	Covered	T74,T77,T83
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T31,T74
0	1	Unreachable
1	0	Covered	T8,T31,T74

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T8,T11
DetectSt	168	Covered	T8,T31,T74
IdleSt	163	Covered	T5,T1,T2
StableSt	191	Covered	T8,T31,T74

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T31,T74
DebounceSt->IdleSt	163	Covered	T3,T11,T57
DetectSt->IdleSt	186	Covered	T74,T77,T83
DetectSt->StableSt	191	Covered	T8,T31,T74
IdleSt->DebounceSt	148	Covered	T3,T8,T11
StableSt->IdleSt	206	Covered	T8,T31,T74

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T8,T11
0	1	Covered	T3,T8,T11
0	0	Excluded	T5,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T31,T74
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T8,T11
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T12
DebounceSt	-	1	-	-	-	-	-	Covered	T3,T52
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T31,T74
DebounceSt	-	0	1	0	-	-	-	Covered	T11,T57,T75
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T8,T11
DetectSt	-	-	-	-	1	-	-	Covered	T74,T77,T83
DetectSt	-	-	-	-	0	1	-	Covered	T8,T31,T74
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T31,T74
StableSt	-	-	-	-	-	-	0	Covered	T8,T31,T74
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5804184	183	0	0
CntIncr_A	5804184	150685	0	0
CntNoWrap_A	5804184	5191123	0	0
DetectStDropOut_A	5804184	22	0	0
DetectedOut_A	5804184	104814	0	0
DetectedPulseOut_A	5804184	50	0	0
DisabledIdleSt_A	5804184	4396525	0	0
DisabledNoDetection_A	5804184	4398797	0	0
EnterDebounceSt_A	5804184	112	0	0
EnterDetectSt_A	5804184	72	0	0
EnterStableSt_A	5804184	50	0	0
PulseIsPulse_A	5804184	50	0	0
StayInStableSt	5804184	104764	0	0
gen_high_level_sva.HighLevelEvent_A	5804184	5193579	0	0
gen_sticky_sva.StableStDropOut_A	5804184	493679	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	183	0	0
T3	7662	1	0	0
T4	707	0	0	0
T6	8924	0	0	0
T8	0	2	0	0
T11	0	1	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T31	0	2	0	0
T50	402	0	0	0
T51	604	0	0	0
T57	0	4	0	0
T74	0	4	0	0
T75	0	1	0	0
T76	0	2	0	0
T77	0	4	0	0
T78	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	150685	0	0
T3	7662	27	0	0
T4	707	0	0	0
T6	8924	0	0	0
T8	0	93	0	0
T11	0	46	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T31	0	71	0	0
T50	402	0	0	0
T51	604	0	0	0
T57	0	264	0	0
T74	0	118	0	0
T75	0	10	0	0
T76	0	21	0	0
T77	0	70	0	0
T78	0	95	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	5191123	0	0
T1	486	85	0	0
T2	25810	24162	0	0
T3	7662	7260	0	0
T5	402	1	0	0
T12	527	126	0	0
T13	404	3	0	0
T14	493	92	0	0
T15	526	125	0	0
T16	406	5	0	0
T17	718	317	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	22	0	0
T60	18303	0	0	0
T74	3157	1	0	0
T77	0	1	0	0
T83	0	2	0	0
T93	0	1	0	0
T100	0	3	0	0
T133	0	4	0	0
T134	0	1	0	0
T135	0	4	0	0
T136	0	3	0	0
T137	0	2	0	0
T138	723	0	0	0
T139	459	0	0	0
T140	503	0	0	0
T141	29446	0	0	0
T142	22014	0	0	0
T143	425	0	0	0
T144	1036	0	0	0
T145	406	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	104814	0	0
T8	2340	645	0	0
T9	32017	0	0	0
T31	0	360	0	0
T53	518	0	0	0
T54	1436	0	0	0
T65	535	0	0	0
T66	522	0	0	0
T74	0	122	0	0
T76	0	13	0	0
T77	0	72	0	0
T78	0	316	0	0
T82	0	230	0	0
T83	0	96825	0	0
T93	0	256	0	0
T121	426	0	0	0
T123	0	38	0	0
T124	421	0	0	0
T125	405	0	0	0
T126	404	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	50	0	0
T8	2340	1	0	0
T9	32017	0	0	0
T31	0	1	0	0
T53	518	0	0	0
T54	1436	0	0	0
T65	535	0	0	0
T66	522	0	0	0
T74	0	1	0	0
T76	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0
T82	0	2	0	0
T83	0	1	0	0
T93	0	1	0	0
T121	426	0	0	0
T123	0	1	0	0
T124	421	0	0	0
T125	405	0	0	0
T126	404	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	4396525	0	0
T1	486	85	0	0
T2	25810	24162	0	0
T3	7662	7227	0	0
T5	402	1	0	0
T12	527	126	0	0
T13	404	3	0	0
T14	493	92	0	0
T15	526	125	0	0
T16	406	5	0	0
T17	718	317	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	4398797	0	0
T1	486	86	0	0
T2	25810	24171	0	0
T3	7662	7227	0	0
T5	402	2	0	0
T12	527	127	0	0
T13	404	4	0	0
T14	493	93	0	0
T15	526	126	0	0
T16	406	6	0	0
T17	718	318	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	112	0	0
T3	7662	2	0	0
T4	707	0	0	0
T6	8924	0	0	0
T8	0	1	0	0
T11	0	1	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T31	0	1	0	0
T50	402	0	0	0
T51	604	0	0	0
T57	0	4	0	0
T74	0	2	0	0
T75	0	1	0	0
T76	0	1	0	0
T77	0	2	0	0
T78	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	72	0	0
T8	2340	1	0	0
T9	32017	0	0	0
T31	0	1	0	0
T53	518	0	0	0
T54	1436	0	0	0
T65	535	0	0	0
T66	522	0	0	0
T74	0	2	0	0
T76	0	1	0	0
T77	0	2	0	0
T78	0	1	0	0
T82	0	2	0	0
T83	0	3	0	0
T93	0	2	0	0
T121	426	0	0	0
T123	0	1	0	0
T124	421	0	0	0
T125	405	0	0	0
T126	404	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	50	0	0
T8	2340	1	0	0
T9	32017	0	0	0
T31	0	1	0	0
T53	518	0	0	0
T54	1436	0	0	0
T65	535	0	0	0
T66	522	0	0	0
T74	0	1	0	0
T76	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0
T82	0	2	0	0
T83	0	1	0	0
T93	0	1	0	0
T121	426	0	0	0
T123	0	1	0	0
T124	421	0	0	0
T125	405	0	0	0
T126	404	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	50	0	0
T8	2340	1	0	0
T9	32017	0	0	0
T31	0	1	0	0
T53	518	0	0	0
T54	1436	0	0	0
T65	535	0	0	0
T66	522	0	0	0
T74	0	1	0	0
T76	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0
T82	0	2	0	0
T83	0	1	0	0
T93	0	1	0	0
T121	426	0	0	0
T123	0	1	0	0
T124	421	0	0	0
T125	405	0	0	0
T126	404	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	104764	0	0
T8	2340	644	0	0
T9	32017	0	0	0
T31	0	359	0	0
T53	518	0	0	0
T54	1436	0	0	0
T65	535	0	0	0
T66	522	0	0	0
T74	0	121	0	0
T76	0	12	0	0
T77	0	71	0	0
T78	0	315	0	0
T82	0	228	0	0
T83	0	96824	0	0
T93	0	255	0	0
T121	426	0	0	0
T123	0	37	0	0
T124	421	0	0	0
T125	405	0	0	0
T126	404	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	5193579	0	0
T1	486	86	0	0
T2	25810	24171	0	0
T3	7662	7262	0	0
T5	402	2	0	0
T12	527	127	0	0
T13	404	4	0	0
T14	493	93	0	0
T15	526	126	0	0
T16	406	6	0	0
T17	718	318	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	493679	0	0
T8	2340	83	0	0
T9	32017	0	0	0
T31	0	75	0	0
T53	518	0	0	0
T54	1436	0	0	0
T65	535	0	0	0
T66	522	0	0	0
T74	0	276	0	0
T76	0	135	0	0
T77	0	250	0	0
T78	0	331	0	0
T82	0	156063	0	0
T83	0	62	0	0
T93	0	263	0	0
T121	426	0	0	0
T123	0	93317	0	0
T124	421	0	0	0
T125	405	0	0	0
T126	404	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T2,T12,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T3,T8,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T2	VC_COV_UNR
1	Covered	T3,T8,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T8,T11,T31

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T11
1	0	Covered	T2,T12,T3
1	1	Covered	T3,T8,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T11,T31
0	1	Covered	T8,T75,T82
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T11,T31
0	1	Unreachable
1	0	Covered	T8,T11,T31

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T8,T11
DetectSt	168	Covered	T8,T11,T31
IdleSt	163	Covered	T5,T1,T2
StableSt	191	Covered	T8,T11,T31

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T11,T31
DebounceSt->IdleSt	163	Covered	T3,T76,T123
DetectSt->IdleSt	186	Covered	T8,T75,T82
DetectSt->StableSt	191	Covered	T8,T11,T31
IdleSt->DebounceSt	148	Covered	T3,T8,T11
StableSt->IdleSt	206	Covered	T8,T11,T31

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T8,T11
0	1	Covered	T3,T8,T11
0	0	Excluded	T5,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T11,T31
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T8,T11
IdleSt	0	-	-	-	-	-	-	Covered	T2,T12,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T3,T52
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T11,T31
DebounceSt	-	0	1	0	-	-	-	Covered	T76,T123,T146
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T8,T11
DetectSt	-	-	-	-	1	-	-	Covered	T8,T75,T82
DetectSt	-	-	-	-	0	1	-	Covered	T8,T11,T31
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T11,T31
StableSt	-	-	-	-	-	-	0	Covered	T8,T11,T31
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5804184	174	0	0
CntIncr_A	5804184	188135	0	0
CntNoWrap_A	5804184	5191132	0	0
DetectStDropOut_A	5804184	15	0	0
DetectedOut_A	5804184	174961	0	0
DetectedPulseOut_A	5804184	46	0	0
DisabledIdleSt_A	5804184	4396525	0	0
DisabledNoDetection_A	5804184	4398797	0	0
EnterDebounceSt_A	5804184	114	0	0
EnterDetectSt_A	5804184	61	0	0
EnterStableSt_A	5804184	46	0	0
PulseIsPulse_A	5804184	46	0	0
StayInStableSt	5804184	174915	0	0
gen_high_event_sva.HighLevelEvent_A	5804184	5193579	0	0
gen_high_level_sva.HighLevelEvent_A	5804184	5193579	0	0
gen_sticky_sva.StableStDropOut_A	5804184	378060	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	174	0	0
T3	7662	1	0	0
T4	707	0	0	0
T6	8924	0	0	0
T8	0	6	0	0
T11	0	2	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T31	0	2	0	0
T50	402	0	0	0
T51	604	0	0	0
T57	0	2	0	0
T74	0	2	0	0
T75	0	2	0	0
T76	0	1	0	0
T77	0	2	0	0
T78	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	188135	0	0
T3	7662	29	0	0
T4	707	0	0	0
T6	8924	0	0	0
T8	0	270	0	0
T11	0	40	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T31	0	14	0	0
T50	402	0	0	0
T51	604	0	0	0
T57	0	19	0	0
T74	0	85	0	0
T75	0	24	0	0
T76	0	28	0	0
T77	0	64	0	0
T78	0	12	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	5191132	0	0
T1	486	85	0	0
T2	25810	24162	0	0
T3	7662	7260	0	0
T5	402	1	0	0
T12	527	126	0	0
T13	404	3	0	0
T14	493	92	0	0
T15	526	125	0	0
T16	406	5	0	0
T17	718	317	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	15	0	0
T8	2340	2	0	0
T9	32017	0	0	0
T53	518	0	0	0
T54	1436	0	0	0
T65	535	0	0	0
T66	522	0	0	0
T75	0	1	0	0
T82	0	1	0	0
T96	0	3	0	0
T121	426	0	0	0
T124	421	0	0	0
T125	405	0	0	0
T126	404	0	0	0
T128	0	1	0	0
T133	0	3	0	0
T137	0	2	0	0
T147	0	1	0	0
T148	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	174961	0	0
T8	2340	92	0	0
T9	32017	0	0	0
T11	0	17	0	0
T31	0	52	0	0
T53	518	0	0	0
T54	1436	0	0	0
T57	0	91	0	0
T65	535	0	0	0
T66	522	0	0	0
T74	0	492	0	0
T77	0	266	0	0
T78	0	51	0	0
T82	0	109	0	0
T83	0	471	0	0
T93	0	172	0	0
T121	426	0	0	0
T124	421	0	0	0
T125	405	0	0	0
T126	404	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	46	0	0
T8	2340	1	0	0
T9	32017	0	0	0
T11	0	1	0	0
T31	0	1	0	0
T53	518	0	0	0
T54	1436	0	0	0
T57	0	1	0	0
T65	535	0	0	0
T66	522	0	0	0
T74	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0
T82	0	2	0	0
T83	0	1	0	0
T93	0	2	0	0
T121	426	0	0	0
T124	421	0	0	0
T125	405	0	0	0
T126	404	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	4396525	0	0
T1	486	85	0	0
T2	25810	24162	0	0
T3	7662	7227	0	0
T5	402	1	0	0
T12	527	126	0	0
T13	404	3	0	0
T14	493	92	0	0
T15	526	125	0	0
T16	406	5	0	0
T17	718	317	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	4398797	0	0
T1	486	86	0	0
T2	25810	24171	0	0
T3	7662	7227	0	0
T5	402	2	0	0
T12	527	127	0	0
T13	404	4	0	0
T14	493	93	0	0
T15	526	126	0	0
T16	406	6	0	0
T17	718	318	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	114	0	0
T3	7662	2	0	0
T4	707	0	0	0
T6	8924	0	0	0
T8	0	3	0	0
T11	0	1	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T31	0	1	0	0
T50	402	0	0	0
T51	604	0	0	0
T57	0	1	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	61	0	0
T8	2340	3	0	0
T9	32017	0	0	0
T11	0	1	0	0
T31	0	1	0	0
T53	518	0	0	0
T54	1436	0	0	0
T57	0	1	0	0
T65	535	0	0	0
T66	522	0	0	0
T74	0	1	0	0
T75	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0
T82	0	3	0	0
T83	0	1	0	0
T121	426	0	0	0
T124	421	0	0	0
T125	405	0	0	0
T126	404	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	46	0	0
T8	2340	1	0	0
T9	32017	0	0	0
T11	0	1	0	0
T31	0	1	0	0
T53	518	0	0	0
T54	1436	0	0	0
T57	0	1	0	0
T65	535	0	0	0
T66	522	0	0	0
T74	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0
T82	0	2	0	0
T83	0	1	0	0
T93	0	2	0	0
T121	426	0	0	0
T124	421	0	0	0
T125	405	0	0	0
T126	404	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	46	0	0
T8	2340	1	0	0
T9	32017	0	0	0
T11	0	1	0	0
T31	0	1	0	0
T53	518	0	0	0
T54	1436	0	0	0
T57	0	1	0	0
T65	535	0	0	0
T66	522	0	0	0
T74	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0
T82	0	2	0	0
T83	0	1	0	0
T93	0	2	0	0
T121	426	0	0	0
T124	421	0	0	0
T125	405	0	0	0
T126	404	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	174915	0	0
T8	2340	91	0	0
T9	32017	0	0	0
T11	0	16	0	0
T31	0	51	0	0
T53	518	0	0	0
T54	1436	0	0	0
T57	0	90	0	0
T65	535	0	0	0
T66	522	0	0	0
T74	0	491	0	0
T77	0	265	0	0
T78	0	50	0	0
T82	0	107	0	0
T83	0	470	0	0
T93	0	170	0	0
T121	426	0	0	0
T124	421	0	0	0
T125	405	0	0	0
T126	404	0	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	5193579	0	0
T1	486	86	0	0
T2	25810	24171	0	0
T3	7662	7262	0	0
T5	402	2	0	0
T12	527	127	0	0
T13	404	4	0	0
T14	493	93	0	0
T15	526	126	0	0
T16	406	6	0	0
T17	718	318	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	5193579	0	0
T1	486	86	0	0
T2	25810	24171	0	0
T3	7662	7262	0	0
T5	402	2	0	0
T12	527	127	0	0
T13	404	4	0	0
T14	493	93	0	0
T15	526	126	0	0
T16	406	6	0	0
T17	718	318	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	378060	0	0
T8	2340	255	0	0
T9	32017	0	0	0
T11	0	66	0	0
T31	0	449	0	0
T53	518	0	0	0
T54	1436	0	0	0
T57	0	535	0	0
T65	535	0	0	0
T66	522	0	0	0
T74	0	45	0	0
T77	0	173	0	0
T78	0	683	0	0
T82	0	124932	0	0
T83	0	241613	0	0
T93	0	455	0	0
T121	426	0	0	0
T124	421	0	0	0
T125	405	0	0	0
T126	404	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T5,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T1,T2,T12
1	1	Covered	T5,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T1,T2,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T2	VC_COV_UNR
1	Covered	T1,T2,T3

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T1,T2,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T1,T2
1	1	Covered	T1,T2,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T149,T150
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T34,T39,T151
1	0	Covered	T3,T52

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T3
1	-	Covered	T34,T39,T151

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T3
DetectSt	168	Covered	T1,T2,T3
IdleSt	163	Covered	T5,T1,T2
StableSt	191	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T3
DebounceSt->IdleSt	163	Not Covered
DetectSt->IdleSt	186	Covered	T149,T150
DetectSt->StableSt	191	Covered	T1,T2,T3
IdleSt->DebounceSt	148	Covered	T1,T2,T3
StableSt->IdleSt	206	Covered	T2,T3,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Excluded	T5,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T2
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T3
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T3
DetectSt	-	-	-	-	1	-	-	Covered	T149,T150
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T3
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T34,T39
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5804184	73	0	0
CntIncr_A	5804184	36920	0	0
CntNoWrap_A	5804184	5191233	0	0
DetectStDropOut_A	5804184	2	0	0
DetectedOut_A	5804184	76952	0	0
DetectedPulseOut_A	5804184	35	0	0
DisabledIdleSt_A	5804184	4991092	0	0
DisabledNoDetection_A	5804184	4993312	0	0
EnterDebounceSt_A	5804184	37	0	0
EnterDetectSt_A	5804184	37	0	0
EnterStableSt_A	5804184	34	0	0
PulseIsPulse_A	5804184	34	0	0
StayInStableSt	5804184	76899	0	0
gen_high_level_sva.HighLevelEvent_A	5804184	5193579	0	0
gen_not_sticky_sva.StableStDropOut_A	5804184	14	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	73	0	0
T1	486	2	0	0
T2	25810	2	0	0
T3	7662	2	0	0
T4	707	0	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T34	0	4	0	0
T37	0	2	0	0
T39	0	2	0	0
T63	0	4	0	0
T151	0	4	0	0
T152	0	2	0	0
T153	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	36920	0	0
T1	486	15	0	0
T2	25810	17	0	0
T3	7662	36	0	0
T4	707	0	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T34	0	144	0	0
T37	0	13	0	0
T39	0	95	0	0
T63	0	96	0	0
T151	0	86	0	0
T152	0	37	0	0
T153	0	100	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	5191233	0	0
T1	486	83	0	0
T2	25810	24160	0	0
T3	7662	7259	0	0
T5	402	1	0	0
T12	527	126	0	0
T13	404	3	0	0
T14	493	92	0	0
T15	526	125	0	0
T16	406	5	0	0
T17	718	317	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	2	0	0
T149	117057	1	0	0
T150	0	1	0	0
T154	678	0	0	0
T155	3050	0	0	0
T156	641	0	0	0
T157	13582	0	0	0
T158	32919	0	0	0
T159	836	0	0	0
T160	488	0	0	0
T161	18705	0	0	0
T162	534	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	76952	0	0
T1	486	46	0	0
T2	25810	112	0	0
T3	7662	2	0	0
T4	707	0	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T34	0	93	0	0
T37	0	41	0	0
T39	0	39	0	0
T63	0	84	0	0
T151	0	136	0	0
T152	0	43	0	0
T153	0	110	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	35	0	0
T1	486	1	0	0
T2	25810	1	0	0
T3	7662	1	0	0
T4	707	0	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T34	0	2	0	0
T37	0	1	0	0
T39	0	1	0	0
T63	0	2	0	0
T151	0	2	0	0
T152	0	1	0	0
T153	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	4991092	0	0
T1	486	3	0	0
T2	25810	23928	0	0
T3	7662	7220	0	0
T5	402	1	0	0
T12	527	126	0	0
T13	404	3	0	0
T14	493	92	0	0
T15	526	125	0	0
T16	406	5	0	0
T17	718	317	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	4993312	0	0
T1	486	3	0	0
T2	25810	23936	0	0
T3	7662	7221	0	0
T5	402	2	0	0
T12	527	127	0	0
T13	404	4	0	0
T14	493	93	0	0
T15	526	126	0	0
T16	406	6	0	0
T17	718	318	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	37	0	0
T1	486	1	0	0
T2	25810	1	0	0
T3	7662	1	0	0
T4	707	0	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T34	0	2	0	0
T37	0	1	0	0
T39	0	1	0	0
T63	0	2	0	0
T151	0	2	0	0
T152	0	1	0	0
T153	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	37	0	0
T1	486	1	0	0
T2	25810	1	0	0
T3	7662	1	0	0
T4	707	0	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T34	0	2	0	0
T37	0	1	0	0
T39	0	1	0	0
T63	0	2	0	0
T151	0	2	0	0
T152	0	1	0	0
T153	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	34	0	0
T1	486	1	0	0
T2	25810	1	0	0
T3	7662	1	0	0
T4	707	0	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T34	0	2	0	0
T37	0	1	0	0
T39	0	1	0	0
T63	0	2	0	0
T151	0	2	0	0
T152	0	1	0	0
T153	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	34	0	0
T1	486	1	0	0
T2	25810	1	0	0
T3	7662	1	0	0
T4	707	0	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T34	0	2	0	0
T37	0	1	0	0
T39	0	1	0	0
T63	0	2	0	0
T151	0	2	0	0
T152	0	1	0	0
T153	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	76899	0	0
T1	486	44	0	0
T2	25810	110	0	0
T3	7662	1	0	0
T4	707	0	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T34	0	90	0	0
T37	0	39	0	0
T39	0	38	0	0
T63	0	81	0	0
T151	0	134	0	0
T152	0	41	0	0
T153	0	107	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	5193579	0	0
T1	486	86	0	0
T2	25810	24171	0	0
T3	7662	7262	0	0
T5	402	2	0	0
T12	527	127	0	0
T13	404	4	0	0
T14	493	93	0	0
T15	526	126	0	0
T16	406	6	0	0
T17	718	318	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	14	0	0
T21	489	0	0	0
T22	501	0	0	0
T34	1011	1	0	0
T39	0	1	0	0
T41	665	0	0	0
T42	790	0	0	0
T43	15008	0	0	0
T58	497	0	0	0
T63	0	1	0	0
T70	525	0	0	0
T151	0	2	0	0
T153	0	1	0	0
T163	0	1	0	0
T164	0	1	0	0
T165	0	1	0	0
T166	0	1	0	0
T167	0	2	0	0
T168	427	0	0	0
T169	690	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T5,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T12
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T2,T3,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T2	VC_COV_UNR
1	Covered	T2,T3,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T2,T3,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T11
1	0	Covered	T1,T2,T12
1	1	Covered	T2,T3,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T11
0	1	Covered	T39,T153,T96
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T11
0	1	Covered	T2,T11,T151
1	0	Covered	T3,T52

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T3,T11
1	-	Covered	T2,T11,T151

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T3,T11
DetectSt	168	Covered	T2,T3,T11
IdleSt	163	Covered	T5,T1,T2
StableSt	191	Covered	T2,T3,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T3,T11
DebounceSt->IdleSt	163	Covered	T151,T153,T170
DetectSt->IdleSt	186	Covered	T39,T153,T96
DetectSt->StableSt	191	Covered	T2,T3,T11
IdleSt->DebounceSt	148	Covered	T2,T3,T11
StableSt->IdleSt	206	Covered	T2,T3,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T3,T11
0	1	Covered	T2,T3,T11
0	0	Excluded	T5,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T11
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T3,T11
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T2
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T3,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T151,T153,T170
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T3,T11
DetectSt	-	-	-	-	1	-	-	Covered	T39,T153,T96
DetectSt	-	-	-	-	0	1	-	Covered	T2,T3,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T3,T11
StableSt	-	-	-	-	-	-	0	Covered	T2,T3,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5804184	112	0	0
CntIncr_A	5804184	84042	0	0
CntNoWrap_A	5804184	5191194	0	0
DetectStDropOut_A	5804184	5	0	0
DetectedOut_A	5804184	57915	0	0
DetectedPulseOut_A	5804184	49	0	0
DisabledIdleSt_A	5804184	4896475	0	0
DisabledNoDetection_A	5804184	4898701	0	0
EnterDebounceSt_A	5804184	59	0	0
EnterDetectSt_A	5804184	54	0	0
EnterStableSt_A	5804184	49	0	0
PulseIsPulse_A	5804184	49	0	0
StayInStableSt	5804184	57841	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5804184	2455	0	0
gen_low_level_sva.LowLevelEvent_A	5804184	5193579	0	0
gen_not_sticky_sva.StableStDropOut_A	5804184	22	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	112	0	0
T2	25810	2	0	0
T3	7662	2	0	0
T4	707	0	0	0
T11	0	8	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T35	0	2	0	0
T39	0	4	0	0
T103	0	2	0	0
T151	0	5	0	0
T171	0	2	0	0
T172	0	4	0	0
T173	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	84042	0	0
T2	25810	17	0	0
T3	7662	36	0	0
T4	707	0	0	0
T11	0	52	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T35	0	34	0	0
T39	0	190	0	0
T103	0	54	0	0
T151	0	129	0	0
T171	0	41	0	0
T172	0	176	0	0
T173	0	60	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	5191194	0	0
T1	486	85	0	0
T2	25810	24160	0	0
T3	7662	7259	0	0
T5	402	1	0	0
T12	527	126	0	0
T13	404	3	0	0
T14	493	92	0	0
T15	526	125	0	0
T16	406	5	0	0
T17	718	317	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	5	0	0
T39	1139	1	0	0
T60	18303	0	0	0
T74	3157	0	0	0
T96	0	2	0	0
T138	723	0	0	0
T139	459	0	0	0
T140	503	0	0	0
T141	29446	0	0	0
T142	22014	0	0	0
T153	0	1	0	0
T174	0	1	0	0
T175	43600	0	0	0
T176	5285	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	57915	0	0
T2	25810	82	0	0
T3	7662	3	0	0
T4	707	0	0	0
T11	0	208	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T35	0	40	0	0
T39	0	171	0	0
T103	0	38	0	0
T151	0	74	0	0
T171	0	37	0	0
T172	0	348	0	0
T173	0	132	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	49	0	0
T2	25810	1	0	0
T3	7662	1	0	0
T4	707	0	0	0
T11	0	4	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T35	0	1	0	0
T39	0	1	0	0
T103	0	1	0	0
T151	0	2	0	0
T171	0	1	0	0
T172	0	2	0	0
T173	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	4896475	0	0
T1	486	85	0	0
T2	25810	23928	0	0
T3	7662	7219	0	0
T5	402	1	0	0
T12	527	126	0	0
T13	404	3	0	0
T14	493	92	0	0
T15	526	125	0	0
T16	406	5	0	0
T17	718	317	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	4898701	0	0
T1	486	86	0	0
T2	25810	23936	0	0
T3	7662	7220	0	0
T5	402	2	0	0
T12	527	127	0	0
T13	404	4	0	0
T14	493	93	0	0
T15	526	126	0	0
T16	406	6	0	0
T17	718	318	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	59	0	0
T2	25810	1	0	0
T3	7662	1	0	0
T4	707	0	0	0
T11	0	4	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T35	0	1	0	0
T39	0	2	0	0
T103	0	1	0	0
T151	0	3	0	0
T171	0	1	0	0
T172	0	2	0	0
T173	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	54	0	0
T2	25810	1	0	0
T3	7662	1	0	0
T4	707	0	0	0
T11	0	4	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T35	0	1	0	0
T39	0	2	0	0
T103	0	1	0	0
T151	0	2	0	0
T171	0	1	0	0
T172	0	2	0	0
T173	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	49	0	0
T2	25810	1	0	0
T3	7662	1	0	0
T4	707	0	0	0
T11	0	4	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T35	0	1	0	0
T39	0	1	0	0
T103	0	1	0	0
T151	0	2	0	0
T171	0	1	0	0
T172	0	2	0	0
T173	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	49	0	0
T2	25810	1	0	0
T3	7662	1	0	0
T4	707	0	0	0
T11	0	4	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T35	0	1	0	0
T39	0	1	0	0
T103	0	1	0	0
T151	0	2	0	0
T171	0	1	0	0
T172	0	2	0	0
T173	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	57841	0	0
T2	25810	81	0	0
T3	7662	2	0	0
T4	707	0	0	0
T11	0	202	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T35	0	38	0	0
T39	0	169	0	0
T103	0	36	0	0
T151	0	71	0	0
T171	0	35	0	0
T172	0	345	0	0
T173	0	130	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	2455	0	0
T1	486	1	0	0
T2	25810	1	0	0
T3	7662	3	0	0
T4	707	1	0	0
T12	527	6	0	0
T13	404	0	0	0
T14	493	5	0	0
T15	526	4	0	0
T16	406	0	0	0
T17	718	0	0	0
T23	0	6	0	0
T120	0	4	0	0
T121	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	5193579	0	0
T1	486	86	0	0
T2	25810	24171	0	0
T3	7662	7262	0	0
T5	402	2	0	0
T12	527	127	0	0
T13	404	4	0	0
T14	493	93	0	0
T15	526	126	0	0
T16	406	6	0	0
T17	718	318	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	22	0	0
T2	25810	1	0	0
T3	7662	0	0	0
T4	707	0	0	0
T11	0	2	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T151	0	1	0	0
T166	0	1	0	0
T172	0	1	0	0
T177	0	1	0	0
T178	0	2	0	0
T179	0	1	0	0
T180	0	1	0	0
T181	0	1	0	0