Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	91.30	90.48		83.33	90.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	91.30	90.48		83.33	90.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.00	89.13	90.48		66.67	85.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.00	89.13	90.48		66.67	85.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T5,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T1,T2,T12
1	1	Covered	T5,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T3,T4,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T2	VC_COV_UNR
1	Covered	T3,T4,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T3,T4,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T5,T1,T2
1	1	Covered	T3,T4,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T11
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T11
0	1	Covered	T11,T39,T74
1	0	Covered	T3,T52

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T4,T11
1	-	Covered	T11,T39,T74

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T4,T11
DetectSt	168	Covered	T3,T4,T11
IdleSt	163	Covered	T5,T1,T2
StableSt	191	Covered	T3,T4,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T4,T11
DebounceSt->IdleSt	163	Covered	T182
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T3,T4,T11
IdleSt->DebounceSt	148	Covered	T3,T4,T11
StableSt->IdleSt	206	Covered	T3,T11,T39

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T4,T11
0	1	Covered	T3,T4,T11
0	0	Excluded	T5,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T11
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T4,T11
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T2
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T4,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T182
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T4,T11
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T3,T4,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T11,T39
StableSt	-	-	-	-	-	-	0	Covered	T3,T4,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5804184	73	0	0
CntIncr_A	5804184	37040	0	0
CntNoWrap_A	5804184	5191233	0	0
DetectStDropOut_A	5804184	0	0	0
DetectedOut_A	5804184	42030	0	0
DetectedPulseOut_A	5804184	36	0	0
DisabledIdleSt_A	5804184	4770031	0	0
DisabledNoDetection_A	5804184	4772250	0	0
EnterDebounceSt_A	5804184	37	0	0
EnterDetectSt_A	5804184	36	0	0
EnterStableSt_A	5804184	36	0	0
PulseIsPulse_A	5804184	36	0	0
StayInStableSt	5804184	41979	0	0
gen_high_level_sva.HighLevelEvent_A	5804184	5193579	0	0
gen_not_sticky_sva.StableStDropOut_A	5804184	19	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	73	0	0
T3	7662	2	0	0
T4	707	2	0	0
T6	8924	0	0	0
T11	0	2	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T37	0	2	0	0
T38	0	2	0	0
T39	0	2	0	0
T50	402	0	0	0
T51	604	0	0	0
T63	0	2	0	0
T74	0	2	0	0
T80	0	2	0	0
T172	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	37040	0	0
T3	7662	36	0	0
T4	707	29	0	0
T6	8924	0	0	0
T11	0	14	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T37	0	13	0	0
T38	0	16	0	0
T39	0	95	0	0
T50	402	0	0	0
T51	604	0	0	0
T63	0	48	0	0
T74	0	90	0	0
T80	0	88	0	0
T172	0	88	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	5191233	0	0
T1	486	85	0	0
T2	25810	24162	0	0
T3	7662	7259	0	0
T5	402	1	0	0
T12	527	126	0	0
T13	404	3	0	0
T14	493	92	0	0
T15	526	125	0	0
T16	406	5	0	0
T17	718	317	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	42030	0	0
T3	7662	2	0	0
T4	707	95	0	0
T6	8924	0	0	0
T11	0	8	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T37	0	42	0	0
T38	0	44	0	0
T39	0	378	0	0
T50	402	0	0	0
T51	604	0	0	0
T63	0	44	0	0
T74	0	93	0	0
T80	0	44	0	0
T172	0	477	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	36	0	0
T3	7662	1	0	0
T4	707	1	0	0
T6	8924	0	0	0
T11	0	1	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T50	402	0	0	0
T51	604	0	0	0
T63	0	1	0	0
T74	0	1	0	0
T80	0	1	0	0
T172	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	4770031	0	0
T1	486	3	0	0
T2	25810	24162	0	0
T3	7662	7220	0	0
T5	402	1	0	0
T12	527	126	0	0
T13	404	3	0	0
T14	493	92	0	0
T15	526	125	0	0
T16	406	5	0	0
T17	718	317	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	4772250	0	0
T1	486	3	0	0
T2	25810	24171	0	0
T3	7662	7221	0	0
T5	402	2	0	0
T12	527	127	0	0
T13	404	4	0	0
T14	493	93	0	0
T15	526	126	0	0
T16	406	6	0	0
T17	718	318	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	37	0	0
T3	7662	1	0	0
T4	707	1	0	0
T6	8924	0	0	0
T11	0	1	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T50	402	0	0	0
T51	604	0	0	0
T63	0	1	0	0
T74	0	1	0	0
T80	0	1	0	0
T172	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	36	0	0
T3	7662	1	0	0
T4	707	1	0	0
T6	8924	0	0	0
T11	0	1	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T50	402	0	0	0
T51	604	0	0	0
T63	0	1	0	0
T74	0	1	0	0
T80	0	1	0	0
T172	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	36	0	0
T3	7662	1	0	0
T4	707	1	0	0
T6	8924	0	0	0
T11	0	1	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T50	402	0	0	0
T51	604	0	0	0
T63	0	1	0	0
T74	0	1	0	0
T80	0	1	0	0
T172	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	36	0	0
T3	7662	1	0	0
T4	707	1	0	0
T6	8924	0	0	0
T11	0	1	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T50	402	0	0	0
T51	604	0	0	0
T63	0	1	0	0
T74	0	1	0	0
T80	0	1	0	0
T172	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	41979	0	0
T3	7662	1	0	0
T4	707	93	0	0
T6	8924	0	0	0
T11	0	7	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T37	0	40	0	0
T38	0	42	0	0
T39	0	377	0	0
T50	402	0	0	0
T51	604	0	0	0
T63	0	42	0	0
T74	0	92	0	0
T80	0	42	0	0
T172	0	476	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	5193579	0	0
T1	486	86	0	0
T2	25810	24171	0	0
T3	7662	7262	0	0
T5	402	2	0	0
T12	527	127	0	0
T13	404	4	0	0
T14	493	93	0	0
T15	526	126	0	0
T16	406	6	0	0
T17	718	318	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	19	0	0
T11	15204	1	0	0
T31	950	0	0	0
T32	23276	0	0	0
T39	0	1	0	0
T55	676	0	0	0
T68	531	0	0	0
T71	60222	0	0	0
T74	0	1	0	0
T172	0	1	0	0
T178	0	1	0	0
T181	0	1	0	0
T183	0	1	0	0
T184	0	1	0	0
T185	0	1	0	0
T186	0	1	0	0
T187	4423	0	0	0
T188	456	0	0	0
T189	425	0	0	0
T190	426	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T5,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T12
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T2,T3,T4

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T2	VC_COV_UNR
1	Covered	T2,T3,T4

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T2,T3,T4

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T12,T3
1	1	Covered	T2,T3,T4

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T37,T80,T191
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T4,T11,T38
1	0	Covered	T3,T52

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T3,T4
1	-	Covered	T4,T11,T38

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T3,T4
DetectSt	168	Covered	T2,T3,T4
IdleSt	163	Covered	T5,T1,T2
StableSt	191	Covered	T2,T3,T4

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T3,T4
DebounceSt->IdleSt	163	Covered	T153,T100,T192
DetectSt->IdleSt	186	Covered	T37,T80,T191
DetectSt->StableSt	191	Covered	T2,T3,T4
IdleSt->DebounceSt	148	Covered	T2,T3,T4
StableSt->IdleSt	206	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
0	0	Excluded	T5,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T3,T4
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T2
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T3,T4
DebounceSt	-	0	1	0	-	-	-	Covered	T153,T100,T192
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T3,T4
DetectSt	-	-	-	-	1	-	-	Covered	T37,T80,T191
DetectSt	-	-	-	-	0	1	-	Covered	T2,T3,T4
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T4,T11
StableSt	-	-	-	-	-	-	0	Covered	T2,T3,T4
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5804184	136	0	0
CntIncr_A	5804184	88979	0	0
CntNoWrap_A	5804184	5191170	0	0
DetectStDropOut_A	5804184	3	0	0
DetectedOut_A	5804184	30292	0	0
DetectedPulseOut_A	5804184	63	0	0
DisabledIdleSt_A	5804184	4989694	0	0
DisabledNoDetection_A	5804184	4991906	0	0
EnterDebounceSt_A	5804184	70	0	0
EnterDetectSt_A	5804184	66	0	0
EnterStableSt_A	5804184	63	0	0
PulseIsPulse_A	5804184	63	0	0
StayInStableSt	5804184	30197	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5804184	2830	0	0
gen_low_level_sva.LowLevelEvent_A	5804184	5193579	0	0
gen_not_sticky_sva.StableStDropOut_A	5804184	29	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	136	0	0
T2	25810	2	0	0
T3	7662	2	0	0
T4	707	2	0	0
T11	0	10	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T37	0	2	0	0
T38	0	2	0	0
T40	0	2	0	0
T61	0	2	0	0
T80	0	2	0	0
T151	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	88979	0	0
T2	25810	17	0	0
T3	7662	36	0	0
T4	707	29	0	0
T11	0	151	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T37	0	13	0	0
T38	0	16	0	0
T40	0	85	0	0
T61	0	23	0	0
T80	0	88	0	0
T151	0	43	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	5191170	0	0
T1	486	85	0	0
T2	25810	24160	0	0
T3	7662	7259	0	0
T5	402	1	0	0
T12	527	126	0	0
T13	404	3	0	0
T14	493	92	0	0
T15	526	125	0	0
T16	406	5	0	0
T17	718	317	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	3	0	0
T37	478	1	0	0
T38	566	0	0	0
T73	4916	0	0	0
T80	630	1	0	0
T117	702	0	0	0
T118	676	0	0	0
T122	32845	0	0	0
T132	1355	0	0	0
T191	0	1	0	0
T193	422	0	0	0
T194	2953	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	30292	0	0
T2	25810	40	0	0
T3	7662	4	0	0
T4	707	39	0	0
T11	0	428	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T38	0	79	0	0
T40	0	301	0	0
T61	0	63	0	0
T151	0	209	0	0
T172	0	93	0	0
T195	0	57	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	63	0	0
T2	25810	1	0	0
T3	7662	1	0	0
T4	707	1	0	0
T11	0	5	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T38	0	1	0	0
T40	0	1	0	0
T61	0	1	0	0
T151	0	1	0	0
T172	0	2	0	0
T195	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	4989694	0	0
T1	486	3	0	0
T2	25810	23928	0	0
T3	7662	7218	0	0
T5	402	1	0	0
T12	527	126	0	0
T13	404	3	0	0
T14	493	92	0	0
T15	526	125	0	0
T16	406	5	0	0
T17	718	317	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	4991906	0	0
T1	486	3	0	0
T2	25810	23936	0	0
T3	7662	7219	0	0
T5	402	2	0	0
T12	527	127	0	0
T13	404	4	0	0
T14	493	93	0	0
T15	526	126	0	0
T16	406	6	0	0
T17	718	318	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	70	0	0
T2	25810	1	0	0
T3	7662	1	0	0
T4	707	1	0	0
T11	0	5	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T61	0	1	0	0
T80	0	1	0	0
T151	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	66	0	0
T2	25810	1	0	0
T3	7662	1	0	0
T4	707	1	0	0
T11	0	5	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T61	0	1	0	0
T80	0	1	0	0
T151	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	63	0	0
T2	25810	1	0	0
T3	7662	1	0	0
T4	707	1	0	0
T11	0	5	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T38	0	1	0	0
T40	0	1	0	0
T61	0	1	0	0
T151	0	1	0	0
T172	0	2	0	0
T195	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	63	0	0
T2	25810	1	0	0
T3	7662	1	0	0
T4	707	1	0	0
T11	0	5	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T38	0	1	0	0
T40	0	1	0	0
T61	0	1	0	0
T151	0	1	0	0
T172	0	2	0	0
T195	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	30197	0	0
T2	25810	38	0	0
T3	7662	3	0	0
T4	707	38	0	0
T11	0	419	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T38	0	78	0	0
T40	0	299	0	0
T61	0	61	0	0
T151	0	208	0	0
T172	0	90	0	0
T195	0	56	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	2830	0	0
T2	25810	1	0	0
T3	7662	7	0	0
T4	707	1	0	0
T12	527	6	0	0
T13	404	0	0	0
T14	493	4	0	0
T15	526	7	0	0
T16	406	0	0	0
T17	718	0	0	0
T23	0	6	0	0
T25	5118	0	0	0
T51	0	3	0	0
T120	0	2	0	0
T121	0	1	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	5193579	0	0
T1	486	86	0	0
T2	25810	24171	0	0
T3	7662	7262	0	0
T5	402	2	0	0
T12	527	127	0	0
T13	404	4	0	0
T14	493	93	0	0
T15	526	126	0	0
T16	406	6	0	0
T17	718	318	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	29	0	0
T4	707	1	0	0
T6	8924	0	0	0
T7	8003	0	0	0
T8	2340	0	0	0
T11	0	1	0	0
T23	508	0	0	0
T25	5118	0	0	0
T30	1065	0	0	0
T38	0	1	0	0
T50	402	0	0	0
T51	604	0	0	0
T96	0	1	0	0
T120	438	0	0	0
T151	0	1	0	0
T152	0	1	0	0
T172	0	1	0	0
T195	0	1	0	0
T196	0	1	0	0
T197	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T2,T12,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T2,T12,T3
1	1	Covered	T2,T12,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T2,T3,T4

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T2	VC_COV_UNR
1	Covered	T2,T3,T4

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T2,T3,T4

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T12,T3
1	1	Covered	T2,T3,T4

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T2,T198,T174
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T2,T40,T35
1	0	Covered	T3,T52

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T3,T4
1	-	Covered	T2,T40,T35

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T3,T4
DetectSt	168	Covered	T2,T3,T4
IdleSt	163	Covered	T5,T1,T2
StableSt	191	Covered	T2,T3,T4

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T3,T4
DebounceSt->IdleSt	163	Covered	T199,T164,T165
DetectSt->IdleSt	186	Covered	T2,T198,T174
DetectSt->StableSt	191	Covered	T2,T3,T4
IdleSt->DebounceSt	148	Covered	T2,T3,T4
StableSt->IdleSt	206	Covered	T2,T3,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
0	0	Excluded	T5,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T3,T4
IdleSt	0	-	-	-	-	-	-	Covered	T2,T12,T3
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T3,T4
DebounceSt	-	0	1	0	-	-	-	Covered	T199,T164,T200
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T3,T4
DetectSt	-	-	-	-	1	-	-	Covered	T2,T198,T174
DetectSt	-	-	-	-	0	1	-	Covered	T2,T3,T4
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T3,T40
StableSt	-	-	-	-	-	-	0	Covered	T2,T3,T4
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5804184	94	0	0
CntIncr_A	5804184	5004	0	0
CntNoWrap_A	5804184	5191212	0	0
DetectStDropOut_A	5804184	3	0	0
DetectedOut_A	5804184	3560	0	0
DetectedPulseOut_A	5804184	42	0	0
DisabledIdleSt_A	5804184	5176292	0	0
DisabledNoDetection_A	5804184	5178522	0	0
EnterDebounceSt_A	5804184	50	0	0
EnterDetectSt_A	5804184	45	0	0
EnterStableSt_A	5804184	42	0	0
PulseIsPulse_A	5804184	42	0	0
StayInStableSt	5804184	3494	0	0
gen_high_level_sva.HighLevelEvent_A	5804184	5193579	0	0
gen_not_sticky_sva.StableStDropOut_A	5804184	16	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	94	0	0
T2	25810	6	0	0
T3	7662	2	0	0
T4	707	2	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T35	0	2	0	0
T38	0	2	0	0
T40	0	2	0	0
T63	0	6	0	0
T93	0	2	0	0
T171	0	2	0	0
T172	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	5004	0	0
T2	25810	51	0	0
T3	7662	36	0	0
T4	707	29	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T35	0	34	0	0
T38	0	16	0	0
T40	0	85	0	0
T63	0	152	0	0
T93	0	37	0	0
T171	0	41	0	0
T172	0	88	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	5191212	0	0
T1	486	85	0	0
T2	25810	24156	0	0
T3	7662	7259	0	0
T5	402	1	0	0
T12	527	126	0	0
T13	404	3	0	0
T14	493	92	0	0
T15	526	125	0	0
T16	406	5	0	0
T17	718	317	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	3	0	0
T2	25810	1	0	0
T3	7662	0	0	0
T4	707	0	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T174	0	1	0	0
T198	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	3560	0	0
T2	25810	45	0	0
T3	7662	4	0	0
T4	707	95	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T35	0	29	0	0
T38	0	140	0	0
T40	0	155	0	0
T63	0	278	0	0
T93	0	58	0	0
T171	0	5	0	0
T172	0	213	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	42	0	0
T2	25810	2	0	0
T3	7662	1	0	0
T4	707	1	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T35	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T63	0	3	0	0
T93	0	1	0	0
T171	0	1	0	0
T172	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	5176292	0	0
T1	486	85	0	0
T2	25810	23928	0	0
T3	7662	7218	0	0
T5	402	1	0	0
T12	527	126	0	0
T13	404	3	0	0
T14	493	92	0	0
T15	526	125	0	0
T16	406	5	0	0
T17	718	317	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	5178522	0	0
T1	486	86	0	0
T2	25810	23936	0	0
T3	7662	7219	0	0
T5	402	2	0	0
T12	527	127	0	0
T13	404	4	0	0
T14	493	93	0	0
T15	526	126	0	0
T16	406	6	0	0
T17	718	318	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	50	0	0
T2	25810	3	0	0
T3	7662	1	0	0
T4	707	1	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T35	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T63	0	3	0	0
T93	0	1	0	0
T171	0	1	0	0
T172	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	45	0	0
T2	25810	3	0	0
T3	7662	1	0	0
T4	707	1	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T35	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T63	0	3	0	0
T93	0	1	0	0
T171	0	1	0	0
T172	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	42	0	0
T2	25810	2	0	0
T3	7662	1	0	0
T4	707	1	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T35	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T63	0	3	0	0
T93	0	1	0	0
T171	0	1	0	0
T172	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	42	0	0
T2	25810	2	0	0
T3	7662	1	0	0
T4	707	1	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T35	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T63	0	3	0	0
T93	0	1	0	0
T171	0	1	0	0
T172	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	3494	0	0
T2	25810	42	0	0
T3	7662	3	0	0
T4	707	93	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T35	0	28	0	0
T38	0	138	0	0
T40	0	154	0	0
T63	0	273	0	0
T93	0	56	0	0
T171	0	4	0	0
T172	0	212	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	5193579	0	0
T1	486	86	0	0
T2	25810	24171	0	0
T3	7662	7262	0	0
T5	402	2	0	0
T12	527	127	0	0
T13	404	4	0	0
T14	493	93	0	0
T15	526	126	0	0
T16	406	6	0	0
T17	718	318	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	16	0	0
T2	25810	1	0	0
T3	7662	0	0	0
T4	707	0	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T35	0	1	0	0
T40	0	1	0	0
T63	0	1	0	0
T171	0	1	0	0
T172	0	1	0	0
T177	0	1	0	0
T184	0	1	0	0
T196	0	2	0	0
T199	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T12,T3
1	Covered	T5,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T12,T3
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T2,T3,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T2	VC_COV_UNR
1	Covered	T2,T3,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T2,T3,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T12,T3
1	1	Covered	T2,T3,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T11
0	1	Covered	T85
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T11
0	1	Covered	T2,T11,T151
1	0	Covered	T3,T52

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T3,T11
1	-	Covered	T2,T11,T151

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T3,T11
DetectSt	168	Covered	T2,T3,T11
IdleSt	163	Covered	T5,T1,T2
StableSt	191	Covered	T2,T3,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T3,T11
DebounceSt->IdleSt	163	Covered	T201,T150
DetectSt->IdleSt	186	Covered	T85
DetectSt->StableSt	191	Covered	T2,T3,T11
IdleSt->DebounceSt	148	Covered	T2,T3,T11
StableSt->IdleSt	206	Covered	T2,T3,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T3,T11
0	1	Covered	T2,T3,T11
0	0	Excluded	T5,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T11
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T3,T11
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T2
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T3,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T201,T150
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T3,T11
DetectSt	-	-	-	-	1	-	-	Covered	T85
DetectSt	-	-	-	-	0	1	-	Covered	T2,T3,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T3,T11
StableSt	-	-	-	-	-	-	0	Covered	T2,T3,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5804184	62	0	0
CntIncr_A	5804184	1628	0	0
CntNoWrap_A	5804184	5191244	0	0
DetectStDropOut_A	5804184	1	0	0
DetectedOut_A	5804184	2305	0	0
DetectedPulseOut_A	5804184	29	0	0
DisabledIdleSt_A	5804184	4801172	0	0
DisabledNoDetection_A	5804184	4803392	0	0
EnterDebounceSt_A	5804184	32	0	0
EnterDetectSt_A	5804184	30	0	0
EnterStableSt_A	5804184	29	0	0
PulseIsPulse_A	5804184	29	0	0
StayInStableSt	5804184	2261	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5804184	6536	0	0
gen_low_level_sva.LowLevelEvent_A	5804184	5193579	0	0
gen_not_sticky_sva.StableStDropOut_A	5804184	12	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	62	0	0
T2	25810	4	0	0
T3	7662	2	0	0
T4	707	0	0	0
T11	0	4	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T34	0	2	0	0
T37	0	2	0	0
T40	0	2	0	0
T151	0	2	0	0
T171	0	2	0	0
T172	0	2	0	0
T202	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	1628	0	0
T2	25810	34	0	0
T3	7662	36	0	0
T4	707	0	0	0
T11	0	28	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T34	0	72	0	0
T37	0	13	0	0
T40	0	85	0	0
T151	0	43	0	0
T171	0	41	0	0
T172	0	88	0	0
T202	0	89	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	5191244	0	0
T1	486	85	0	0
T2	25810	24158	0	0
T3	7662	7259	0	0
T5	402	1	0	0
T12	527	126	0	0
T13	404	3	0	0
T14	493	92	0	0
T15	526	125	0	0
T16	406	5	0	0
T17	718	317	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	1	0	0
T85	11115	1	0	0
T128	3890	0	0	0
T203	684	0	0	0
T204	491	0	0	0
T205	506	0	0	0
T206	32348	0	0	0
T207	1971	0	0	0
T208	690	0	0	0
T209	1722	0	0	0
T210	843	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	2305	0	0
T2	25810	94	0	0
T3	7662	3	0	0
T4	707	0	0	0
T11	0	80	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T34	0	169	0	0
T37	0	42	0	0
T40	0	40	0	0
T151	0	210	0	0
T171	0	163	0	0
T172	0	42	0	0
T202	0	39	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	29	0	0
T2	25810	2	0	0
T3	7662	1	0	0
T4	707	0	0	0
T11	0	2	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T34	0	1	0	0
T37	0	1	0	0
T40	0	1	0	0
T151	0	1	0	0
T171	0	1	0	0
T172	0	1	0	0
T202	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	4801172	0	0
T1	486	85	0	0
T2	25810	23928	0	0
T3	7662	7219	0	0
T5	402	1	0	0
T12	527	126	0	0
T13	404	3	0	0
T14	493	92	0	0
T15	526	125	0	0
T16	406	5	0	0
T17	718	317	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	4803392	0	0
T1	486	86	0	0
T2	25810	23936	0	0
T3	7662	7220	0	0
T5	402	2	0	0
T12	527	127	0	0
T13	404	4	0	0
T14	493	93	0	0
T15	526	126	0	0
T16	406	6	0	0
T17	718	318	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	32	0	0
T2	25810	2	0	0
T3	7662	1	0	0
T4	707	0	0	0
T11	0	2	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T34	0	1	0	0
T37	0	1	0	0
T40	0	1	0	0
T151	0	1	0	0
T171	0	1	0	0
T172	0	1	0	0
T202	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	30	0	0
T2	25810	2	0	0
T3	7662	1	0	0
T4	707	0	0	0
T11	0	2	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T34	0	1	0	0
T37	0	1	0	0
T40	0	1	0	0
T151	0	1	0	0
T171	0	1	0	0
T172	0	1	0	0
T202	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	29	0	0
T2	25810	2	0	0
T3	7662	1	0	0
T4	707	0	0	0
T11	0	2	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T34	0	1	0	0
T37	0	1	0	0
T40	0	1	0	0
T151	0	1	0	0
T171	0	1	0	0
T172	0	1	0	0
T202	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	29	0	0
T2	25810	2	0	0
T3	7662	1	0	0
T4	707	0	0	0
T11	0	2	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T34	0	1	0	0
T37	0	1	0	0
T40	0	1	0	0
T151	0	1	0	0
T171	0	1	0	0
T172	0	1	0	0
T202	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	2261	0	0
T2	25810	92	0	0
T3	7662	2	0	0
T4	707	0	0	0
T11	0	77	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T34	0	167	0	0
T37	0	40	0	0
T40	0	38	0	0
T151	0	209	0	0
T171	0	161	0	0
T172	0	40	0	0
T202	0	37	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	6536	0	0
T2	25810	30	0	0
T3	7662	30	0	0
T4	707	0	0	0
T6	0	14	0	0
T7	0	25	0	0
T12	527	6	0	0
T13	404	0	0	0
T14	493	6	0	0
T15	526	5	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	27	0	0
T30	0	5	0	0
T120	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	5193579	0	0
T1	486	86	0	0
T2	25810	24171	0	0
T3	7662	7262	0	0
T5	402	2	0	0
T12	527	127	0	0
T13	404	4	0	0
T14	493	93	0	0
T15	526	126	0	0
T16	406	6	0	0
T17	718	318	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	12	0	0
T2	25810	2	0	0
T3	7662	0	0	0
T4	707	0	0	0
T11	0	1	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T151	0	1	0	0
T164	0	1	0	0
T174	0	1	0	0
T177	0	1	0	0
T178	0	1	0	0
T181	0	2	0	0
T186	0	1	0	0
T211	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T2,T12,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T2,T12,T3
1	1	Covered	T2,T12,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T2,T3,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T2	VC_COV_UNR
1	Covered	T2,T3,T34

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T2,T3,T34

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T71
1	0	Covered	T2,T12,T3
1	1	Covered	T2,T3,T34

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T34
0	1	Covered	T212,T184,T213
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T34
0	1	Covered	T2,T34,T40
1	0	Covered	T3,T52

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T3,T34
1	-	Covered	T2,T34,T40

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T3,T34
DetectSt	168	Covered	T2,T3,T34
IdleSt	163	Covered	T5,T1,T2
StableSt	191	Covered	T2,T3,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T3,T34
DebounceSt->IdleSt	163	Covered	T178,T214,T167
DetectSt->IdleSt	186	Covered	T212,T184,T213
DetectSt->StableSt	191	Covered	T2,T3,T34
IdleSt->DebounceSt	148	Covered	T2,T3,T34
StableSt->IdleSt	206	Covered	T2,T3,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T3,T34
0	1	Covered	T2,T3,T34
0	0	Excluded	T5,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T34
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T3,T34
IdleSt	0	-	-	-	-	-	-	Covered	T2,T12,T3
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T3,T34
DebounceSt	-	0	1	0	-	-	-	Covered	T178,T214,T167
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T3,T34
DetectSt	-	-	-	-	1	-	-	Covered	T212,T184,T213
DetectSt	-	-	-	-	0	1	-	Covered	T2,T3,T34
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T3,T34
StableSt	-	-	-	-	-	-	0	Covered	T2,T3,T34
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5804184	113	0	0
CntIncr_A	5804184	38132	0	0
CntNoWrap_A	5804184	5191193	0	0
DetectStDropOut_A	5804184	3	0	0
DetectedOut_A	5804184	50271	0	0
DetectedPulseOut_A	5804184	51	0	0
DisabledIdleSt_A	5804184	4958488	0	0
DisabledNoDetection_A	5804184	4960708	0	0
EnterDebounceSt_A	5804184	59	0	0
EnterDetectSt_A	5804184	54	0	0
EnterStableSt_A	5804184	51	0	0
PulseIsPulse_A	5804184	51	0	0
StayInStableSt	5804184	50193	0	0
gen_high_level_sva.HighLevelEvent_A	5804184	5193579	0	0
gen_not_sticky_sva.StableStDropOut_A	5804184	22	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	113	0	0
T2	25810	4	0	0
T3	7662	2	0	0
T4	707	0	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T34	0	2	0	0
T35	0	2	0	0
T36	0	2	0	0
T38	0	4	0	0
T40	0	4	0	0
T63	0	4	0	0
T152	0	2	0	0
T172	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	38132	0	0
T2	25810	34	0	0
T3	7662	36	0	0
T4	707	0	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T34	0	72	0	0
T35	0	34	0	0
T36	0	26	0	0
T38	0	32	0	0
T40	0	170	0	0
T63	0	104	0	0
T152	0	37	0	0
T172	0	176	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	5191193	0	0
T1	486	85	0	0
T2	25810	24158	0	0
T3	7662	7259	0	0
T5	402	1	0	0
T12	527	126	0	0
T13	404	3	0	0
T14	493	92	0	0
T15	526	125	0	0
T16	406	5	0	0
T17	718	317	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	3	0	0
T184	0	1	0	0
T212	1044	1	0	0
T213	0	1	0	0
T215	423	0	0	0
T216	422	0	0	0
T217	434	0	0	0
T218	523	0	0	0
T219	2285	0	0	0
T220	402	0	0	0
T221	508	0	0	0
T222	1324	0	0	0
T223	6018	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	50271	0	0
T2	25810	178	0	0
T3	7662	2	0	0
T4	707	0	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T34	0	42	0	0
T35	0	39	0	0
T36	0	39	0	0
T38	0	84	0	0
T40	0	84	0	0
T63	0	149	0	0
T152	0	31	0	0
T172	0	386	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	51	0	0
T2	25810	2	0	0
T3	7662	1	0	0
T4	707	0	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T38	0	2	0	0
T40	0	2	0	0
T63	0	2	0	0
T152	0	1	0	0
T172	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	4958488	0	0
T1	486	85	0	0
T2	25810	23928	0	0
T3	7662	7220	0	0
T5	402	1	0	0
T12	527	126	0	0
T13	404	3	0	0
T14	493	92	0	0
T15	526	125	0	0
T16	406	5	0	0
T17	718	317	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	4960708	0	0
T1	486	86	0	0
T2	25810	23936	0	0
T3	7662	7221	0	0
T5	402	2	0	0
T12	527	127	0	0
T13	404	4	0	0
T14	493	93	0	0
T15	526	126	0	0
T16	406	6	0	0
T17	718	318	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	59	0	0
T2	25810	2	0	0
T3	7662	1	0	0
T4	707	0	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T38	0	2	0	0
T40	0	2	0	0
T63	0	2	0	0
T152	0	1	0	0
T172	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	54	0	0
T2	25810	2	0	0
T3	7662	1	0	0
T4	707	0	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T38	0	2	0	0
T40	0	2	0	0
T63	0	2	0	0
T152	0	1	0	0
T172	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	51	0	0
T2	25810	2	0	0
T3	7662	1	0	0
T4	707	0	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T38	0	2	0	0
T40	0	2	0	0
T63	0	2	0	0
T152	0	1	0	0
T172	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	51	0	0
T2	25810	2	0	0
T3	7662	1	0	0
T4	707	0	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T38	0	2	0	0
T40	0	2	0	0
T63	0	2	0	0
T152	0	1	0	0
T172	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	50193	0	0
T2	25810	175	0	0
T3	7662	1	0	0
T4	707	0	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T34	0	41	0	0
T35	0	37	0	0
T36	0	37	0	0
T38	0	81	0	0
T40	0	81	0	0
T63	0	145	0	0
T152	0	30	0	0
T172	0	383	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	5193579	0	0
T1	486	86	0	0
T2	25810	24171	0	0
T3	7662	7262	0	0
T5	402	2	0	0
T12	527	127	0	0
T13	404	4	0	0
T14	493	93	0	0
T15	526	126	0	0
T16	406	6	0	0
T17	718	318	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	22	0	0
T2	25810	1	0	0
T3	7662	0	0	0
T4	707	0	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T34	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T152	0	1	0	0
T153	0	1	0	0
T172	0	1	0	0
T185	0	1	0	0
T199	0	1	0	0
T224	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	41	89.13
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	27	84.38
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T12,T3
1	Covered	T5,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T12,T3
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T3,T34,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T2	VC_COV_UNR
1	Covered	T3,T34,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T3,T34,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T11
1	0	Covered	T2,T12,T3
1	1	Covered	T3,T34,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T34,T40
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T34,T40
0	1	Covered	T40,T38,T172
1	0	Covered	T3,T52

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T34,T40
1	-	Covered	T40,T38,T172

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	4	66.67
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T34,T40
DetectSt	168	Covered	T3,T34,T40
IdleSt	163	Covered	T5,T1,T2
StableSt	191	Covered	T3,T34,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T34,T40
DebounceSt->IdleSt	163	Not Covered
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T3,T34,T40
IdleSt->DebounceSt	148	Covered	T3,T34,T40
StableSt->IdleSt	206	Covered	T3,T40,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	17	85.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	7	70.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T34,T40
0	1	Covered	T3,T34,T40
0	0	Excluded	T5,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T34,T40
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T34,T40
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T2
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T34,T40
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T34,T40
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T3,T34,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T40,T38
StableSt	-	-	-	-	-	-	0	Covered	T3,T34,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5804184	62	0	0
CntIncr_A	5804184	1635	0	0
CntNoWrap_A	5804184	5191244	0	0
DetectStDropOut_A	5804184	0	0	0
DetectedOut_A	5804184	2013	0	0
DetectedPulseOut_A	5804184	31	0	0
DisabledIdleSt_A	5804184	4866152	0	0
DisabledNoDetection_A	5804184	4868365	0	0
EnterDebounceSt_A	5804184	31	0	0
EnterDetectSt_A	5804184	31	0	0
EnterStableSt_A	5804184	31	0	0
PulseIsPulse_A	5804184	31	0	0
StayInStableSt	5804184	1966	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5804184	6076	0	0
gen_low_level_sva.LowLevelEvent_A	5804184	5193579	0	0
gen_not_sticky_sva.StableStDropOut_A	5804184	13	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	62	0	0
T3	7662	2	0	0
T4	707	0	0	0
T6	8924	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T34	0	2	0	0
T38	0	2	0	0
T40	0	2	0	0
T50	402	0	0	0
T51	604	0	0	0
T80	0	2	0	0
T170	0	2	0	0
T172	0	2	0	0
T197	0	2	0	0
T212	0	2	0	0
T225	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	1635	0	0
T3	7662	36	0	0
T4	707	0	0	0
T6	8924	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T34	0	72	0	0
T38	0	16	0	0
T40	0	85	0	0
T50	402	0	0	0
T51	604	0	0	0
T80	0	88	0	0
T170	0	47	0	0
T172	0	88	0	0
T197	0	81	0	0
T212	0	71	0	0
T225	0	25	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	5191244	0	0
T1	486	85	0	0
T2	25810	24162	0	0
T3	7662	7259	0	0
T5	402	1	0	0
T12	527	126	0	0
T13	404	3	0	0
T14	493	92	0	0
T15	526	125	0	0
T16	406	5	0	0
T17	718	317	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	2013	0	0
T3	7662	3	0	0
T4	707	0	0	0
T6	8924	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T34	0	169	0	0
T38	0	3	0	0
T40	0	25	0	0
T50	402	0	0	0
T51	604	0	0	0
T80	0	44	0	0
T170	0	39	0	0
T172	0	43	0	0
T197	0	145	0	0
T212	0	43	0	0
T225	0	38	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	31	0	0
T3	7662	1	0	0
T4	707	0	0	0
T6	8924	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T34	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T50	402	0	0	0
T51	604	0	0	0
T80	0	1	0	0
T170	0	1	0	0
T172	0	1	0	0
T197	0	1	0	0
T212	0	1	0	0
T225	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	4866152	0	0
T1	486	3	0	0
T2	25810	24162	0	0
T3	7662	7220	0	0
T5	402	1	0	0
T12	527	126	0	0
T13	404	3	0	0
T14	493	92	0	0
T15	526	125	0	0
T16	406	5	0	0
T17	718	317	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	4868365	0	0
T1	486	3	0	0
T2	25810	24171	0	0
T3	7662	7221	0	0
T5	402	2	0	0
T12	527	127	0	0
T13	404	4	0	0
T14	493	93	0	0
T15	526	126	0	0
T16	406	6	0	0
T17	718	318	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	31	0	0
T3	7662	1	0	0
T4	707	0	0	0
T6	8924	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T34	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T50	402	0	0	0
T51	604	0	0	0
T80	0	1	0	0
T170	0	1	0	0
T172	0	1	0	0
T197	0	1	0	0
T212	0	1	0	0
T225	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	31	0	0
T3	7662	1	0	0
T4	707	0	0	0
T6	8924	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T34	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T50	402	0	0	0
T51	604	0	0	0
T80	0	1	0	0
T170	0	1	0	0
T172	0	1	0	0
T197	0	1	0	0
T212	0	1	0	0
T225	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	31	0	0
T3	7662	1	0	0
T4	707	0	0	0
T6	8924	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T34	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T50	402	0	0	0
T51	604	0	0	0
T80	0	1	0	0
T170	0	1	0	0
T172	0	1	0	0
T197	0	1	0	0
T212	0	1	0	0
T225	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	31	0	0
T3	7662	1	0	0
T4	707	0	0	0
T6	8924	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T34	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T50	402	0	0	0
T51	604	0	0	0
T80	0	1	0	0
T170	0	1	0	0
T172	0	1	0	0
T197	0	1	0	0
T212	0	1	0	0
T225	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	1966	0	0
T3	7662	2	0	0
T4	707	0	0	0
T6	8924	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T34	0	167	0	0
T38	0	2	0	0
T40	0	24	0	0
T50	402	0	0	0
T51	604	0	0	0
T80	0	42	0	0
T170	0	38	0	0
T172	0	42	0	0
T197	0	143	0	0
T212	0	42	0	0
T225	0	36	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	6076	0	0
T2	25810	23	0	0
T3	7662	22	0	0
T4	707	2	0	0
T6	0	11	0	0
T7	0	23	0	0
T12	527	5	0	0
T13	404	0	0	0
T14	493	9	0	0
T15	526	3	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	24	0	0
T120	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	5193579	0	0
T1	486	86	0	0
T2	25810	24171	0	0
T3	7662	7262	0	0
T5	402	2	0	0
T12	527	127	0	0
T13	404	4	0	0
T14	493	93	0	0
T15	526	126	0	0
T16	406	6	0	0
T17	718	318	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	13	0	0
T35	547	0	0	0
T38	0	1	0	0
T40	3229	1	0	0
T48	754	0	0	0
T49	2964	0	0	0
T57	2075	0	0	0
T72	24336	0	0	0
T165	0	1	0	0
T170	0	1	0	0
T172	0	1	0	0
T174	0	1	0	0
T184	0	2	0	0
T199	0	1	0	0
T212	0	1	0	0
T226	0	1	0	0
T227	506	0	0	0
T228	524	0	0	0
T229	501	0	0	0
T230	450	0	0	0