Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T2,T12,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T2,T12,T3
1	1	Covered	T2,T12,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T3,T4,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T2	VC_COV_UNR
1	Covered	T3,T4,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T3,T4,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T11
1	0	Covered	T2,T12,T3
1	1	Covered	T3,T4,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T11
0	1	Covered	T4,T39,T231
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T11
0	1	Covered	T11,T40,T38
1	0	Covered	T3,T52

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T4,T11
1	-	Covered	T11,T40,T38

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T4,T11
DetectSt	168	Covered	T3,T4,T11
IdleSt	163	Covered	T5,T1,T2
StableSt	191	Covered	T3,T4,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T4,T11
DebounceSt->IdleSt	163	Covered	T195,T181,T200
DetectSt->IdleSt	186	Covered	T4,T39,T231
DetectSt->StableSt	191	Covered	T3,T4,T11
IdleSt->DebounceSt	148	Covered	T3,T4,T11
StableSt->IdleSt	206	Covered	T3,T11,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T4,T11
0	1	Covered	T3,T4,T11
0	0	Excluded	T5,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T11
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T4,T11
IdleSt	0	-	-	-	-	-	-	Covered	T2,T12,T3
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T4,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T195,T200,T167
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T4,T11
DetectSt	-	-	-	-	1	-	-	Covered	T4,T39,T231
DetectSt	-	-	-	-	0	1	-	Covered	T3,T4,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T11,T40
StableSt	-	-	-	-	-	-	0	Covered	T3,T4,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5804184	117	0	0
CntIncr_A	5804184	38369	0	0
CntNoWrap_A	5804184	5191189	0	0
DetectStDropOut_A	5804184	3	0	0
DetectedOut_A	5804184	3266	0	0
DetectedPulseOut_A	5804184	53	0	0
DisabledIdleSt_A	5804184	5018727	0	0
DisabledNoDetection_A	5804184	5020949	0	0
EnterDebounceSt_A	5804184	62	0	0
EnterDetectSt_A	5804184	56	0	0
EnterStableSt_A	5804184	53	0	0
PulseIsPulse_A	5804184	53	0	0
StayInStableSt	5804184	3191	0	0
gen_high_level_sva.HighLevelEvent_A	5804184	5193579	0	0
gen_not_sticky_sva.StableStDropOut_A	5804184	29	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	117	0	0
T3	7662	2	0	0
T4	707	4	0	0
T6	8924	0	0	0
T11	0	4	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T38	0	2	0	0
T39	0	6	0	0
T40	0	2	0	0
T50	402	0	0	0
T51	604	0	0	0
T63	0	2	0	0
T74	0	2	0	0
T103	0	2	0	0
T151	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	38369	0	0
T3	7662	36	0	0
T4	707	58	0	0
T6	8924	0	0	0
T11	0	28	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T38	0	16	0	0
T39	0	285	0	0
T40	0	85	0	0
T50	402	0	0	0
T51	604	0	0	0
T63	0	48	0	0
T74	0	90	0	0
T103	0	54	0	0
T151	0	86	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	5191189	0	0
T1	486	85	0	0
T2	25810	24162	0	0
T3	7662	7259	0	0
T5	402	1	0	0
T12	527	126	0	0
T13	404	3	0	0
T14	493	92	0	0
T15	526	125	0	0
T16	406	5	0	0
T17	718	317	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	3	0	0
T4	707	1	0	0
T6	8924	0	0	0
T7	8003	0	0	0
T8	2340	0	0	0
T23	508	0	0	0
T25	5118	0	0	0
T30	1065	0	0	0
T39	0	1	0	0
T50	402	0	0	0
T51	604	0	0	0
T120	438	0	0	0
T231	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	3266	0	0
T3	7662	2	0	0
T4	707	44	0	0
T6	8924	0	0	0
T11	0	124	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T38	0	60	0	0
T39	0	199	0	0
T40	0	24	0	0
T50	402	0	0	0
T51	604	0	0	0
T63	0	39	0	0
T74	0	94	0	0
T103	0	93	0	0
T151	0	182	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	53	0	0
T3	7662	1	0	0
T4	707	1	0	0
T6	8924	0	0	0
T11	0	2	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T50	402	0	0	0
T51	604	0	0	0
T63	0	1	0	0
T74	0	1	0	0
T103	0	1	0	0
T151	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	5018727	0	0
T1	486	85	0	0
T2	25810	24162	0	0
T3	7662	7220	0	0
T5	402	1	0	0
T12	527	126	0	0
T13	404	3	0	0
T14	493	92	0	0
T15	526	125	0	0
T16	406	5	0	0
T17	718	317	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	5020949	0	0
T1	486	86	0	0
T2	25810	24171	0	0
T3	7662	7221	0	0
T5	402	2	0	0
T12	527	127	0	0
T13	404	4	0	0
T14	493	93	0	0
T15	526	126	0	0
T16	406	6	0	0
T17	718	318	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	62	0	0
T3	7662	1	0	0
T4	707	2	0	0
T6	8924	0	0	0
T11	0	2	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T38	0	1	0	0
T39	0	3	0	0
T40	0	1	0	0
T50	402	0	0	0
T51	604	0	0	0
T63	0	1	0	0
T74	0	1	0	0
T103	0	1	0	0
T151	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	56	0	0
T3	7662	1	0	0
T4	707	2	0	0
T6	8924	0	0	0
T11	0	2	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T38	0	1	0	0
T39	0	3	0	0
T40	0	1	0	0
T50	402	0	0	0
T51	604	0	0	0
T63	0	1	0	0
T74	0	1	0	0
T103	0	1	0	0
T151	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	53	0	0
T3	7662	1	0	0
T4	707	1	0	0
T6	8924	0	0	0
T11	0	2	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T50	402	0	0	0
T51	604	0	0	0
T63	0	1	0	0
T74	0	1	0	0
T103	0	1	0	0
T151	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	53	0	0
T3	7662	1	0	0
T4	707	1	0	0
T6	8924	0	0	0
T11	0	2	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T50	402	0	0	0
T51	604	0	0	0
T63	0	1	0	0
T74	0	1	0	0
T103	0	1	0	0
T151	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	3191	0	0
T3	7662	1	0	0
T4	707	42	0	0
T6	8924	0	0	0
T11	0	122	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T38	0	59	0	0
T39	0	196	0	0
T40	0	23	0	0
T50	402	0	0	0
T51	604	0	0	0
T63	0	38	0	0
T74	0	93	0	0
T103	0	91	0	0
T151	0	179	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	5193579	0	0
T1	486	86	0	0
T2	25810	24171	0	0
T3	7662	7262	0	0
T5	402	2	0	0
T12	527	127	0	0
T13	404	4	0	0
T14	493	93	0	0
T15	526	126	0	0
T16	406	6	0	0
T17	718	318	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	29	0	0
T11	15204	2	0	0
T31	950	0	0	0
T32	23276	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T55	676	0	0	0
T63	0	1	0	0
T68	531	0	0	0
T71	60222	0	0	0
T74	0	1	0	0
T151	0	1	0	0
T184	0	1	0	0
T187	4423	0	0	0
T188	456	0	0	0
T189	425	0	0	0
T190	426	0	0	0
T199	0	2	0	0
T202	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T12,T3
1	Covered	T5,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T12,T3
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T3,T4,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T2	VC_COV_UNR
1	Covered	T3,T4,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T3,T4,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T2,T12,T3
1	1	Covered	T3,T4,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T38
0	1	Covered	T85
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T38
0	1	Covered	T4,T39,T151
1	0	Covered	T3,T52

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T4,T38
1	-	Covered	T4,T39,T151

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T4,T38
DetectSt	168	Covered	T3,T4,T38
IdleSt	163	Covered	T5,T1,T2
StableSt	191	Covered	T3,T4,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T4,T38
DebounceSt->IdleSt	163	Covered	T202
DetectSt->IdleSt	186	Covered	T85
DetectSt->StableSt	191	Covered	T3,T4,T38
IdleSt->DebounceSt	148	Covered	T3,T4,T38
StableSt->IdleSt	206	Covered	T3,T4,T39

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T4,T38
0	1	Covered	T3,T4,T38
0	0	Excluded	T5,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T38
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T4,T38
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T2
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T4,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T202
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T4,T38
DetectSt	-	-	-	-	1	-	-	Covered	T85
DetectSt	-	-	-	-	0	1	-	Covered	T3,T4,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T4,T39
StableSt	-	-	-	-	-	-	0	Covered	T3,T4,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5804184	81	0	0
CntIncr_A	5804184	41743	0	0
CntNoWrap_A	5804184	5191225	0	0
DetectStDropOut_A	5804184	1	0	0
DetectedOut_A	5804184	2486	0	0
DetectedPulseOut_A	5804184	39	0	0
DisabledIdleSt_A	5804184	4895777	0	0
DisabledNoDetection_A	5804184	4897991	0	0
EnterDebounceSt_A	5804184	41	0	0
EnterDetectSt_A	5804184	40	0	0
EnterStableSt_A	5804184	39	0	0
PulseIsPulse_A	5804184	39	0	0
StayInStableSt	5804184	2427	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5804184	6206	0	0
gen_low_level_sva.LowLevelEvent_A	5804184	5193579	0	0
gen_not_sticky_sva.StableStDropOut_A	5804184	17	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	81	0	0
T3	7662	2	0	0
T4	707	2	0	0
T6	8924	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T38	0	2	0	0
T39	0	4	0	0
T50	402	0	0	0
T51	604	0	0	0
T74	0	2	0	0
T93	0	2	0	0
T151	0	2	0	0
T153	0	2	0	0
T171	0	2	0	0
T202	0	3	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	41743	0	0
T3	7662	36	0	0
T4	707	29	0	0
T6	8924	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T38	0	16	0	0
T39	0	190	0	0
T50	402	0	0	0
T51	604	0	0	0
T74	0	90	0	0
T93	0	37	0	0
T151	0	43	0	0
T153	0	50	0	0
T171	0	41	0	0
T202	0	178	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	5191225	0	0
T1	486	85	0	0
T2	25810	24162	0	0
T3	7662	7259	0	0
T5	402	1	0	0
T12	527	126	0	0
T13	404	3	0	0
T14	493	92	0	0
T15	526	125	0	0
T16	406	5	0	0
T17	718	317	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	1	0	0
T85	11115	1	0	0
T128	3890	0	0	0
T203	684	0	0	0
T204	491	0	0	0
T205	506	0	0	0
T206	32348	0	0	0
T207	1971	0	0	0
T208	690	0	0	0
T209	1722	0	0	0
T210	843	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	2486	0	0
T3	7662	3	0	0
T4	707	91	0	0
T6	8924	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T38	0	44	0	0
T39	0	51	0	0
T50	402	0	0	0
T51	604	0	0	0
T74	0	40	0	0
T93	0	47	0	0
T151	0	99	0	0
T153	0	67	0	0
T171	0	82	0	0
T202	0	77	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	39	0	0
T3	7662	1	0	0
T4	707	1	0	0
T6	8924	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T38	0	1	0	0
T39	0	2	0	0
T50	402	0	0	0
T51	604	0	0	0
T74	0	1	0	0
T93	0	1	0	0
T151	0	1	0	0
T153	0	1	0	0
T171	0	1	0	0
T202	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	4895777	0	0
T1	486	3	0	0
T2	25810	24162	0	0
T3	7662	7219	0	0
T5	402	1	0	0
T12	527	126	0	0
T13	404	3	0	0
T14	493	92	0	0
T15	526	125	0	0
T16	406	5	0	0
T17	718	317	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	4897991	0	0
T1	486	3	0	0
T2	25810	24171	0	0
T3	7662	7220	0	0
T5	402	2	0	0
T12	527	127	0	0
T13	404	4	0	0
T14	493	93	0	0
T15	526	126	0	0
T16	406	6	0	0
T17	718	318	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	41	0	0
T3	7662	1	0	0
T4	707	1	0	0
T6	8924	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T38	0	1	0	0
T39	0	2	0	0
T50	402	0	0	0
T51	604	0	0	0
T74	0	1	0	0
T93	0	1	0	0
T151	0	1	0	0
T153	0	1	0	0
T171	0	1	0	0
T202	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	40	0	0
T3	7662	1	0	0
T4	707	1	0	0
T6	8924	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T38	0	1	0	0
T39	0	2	0	0
T50	402	0	0	0
T51	604	0	0	0
T74	0	1	0	0
T93	0	1	0	0
T151	0	1	0	0
T153	0	1	0	0
T171	0	1	0	0
T202	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	39	0	0
T3	7662	1	0	0
T4	707	1	0	0
T6	8924	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T38	0	1	0	0
T39	0	2	0	0
T50	402	0	0	0
T51	604	0	0	0
T74	0	1	0	0
T93	0	1	0	0
T151	0	1	0	0
T153	0	1	0	0
T171	0	1	0	0
T202	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	39	0	0
T3	7662	1	0	0
T4	707	1	0	0
T6	8924	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T38	0	1	0	0
T39	0	2	0	0
T50	402	0	0	0
T51	604	0	0	0
T74	0	1	0	0
T93	0	1	0	0
T151	0	1	0	0
T153	0	1	0	0
T171	0	1	0	0
T202	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	2427	0	0
T3	7662	2	0	0
T4	707	90	0	0
T6	8924	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T38	0	42	0	0
T39	0	49	0	0
T50	402	0	0	0
T51	604	0	0	0
T74	0	38	0	0
T93	0	45	0	0
T151	0	98	0	0
T153	0	65	0	0
T171	0	81	0	0
T202	0	76	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	6206	0	0
T2	25810	26	0	0
T3	7662	31	0	0
T4	707	1	0	0
T6	0	13	0	0
T7	0	26	0	0
T12	527	4	0	0
T13	404	0	0	0
T14	493	3	0	0
T15	526	5	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	22	0	0
T120	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	5193579	0	0
T1	486	86	0	0
T2	25810	24171	0	0
T3	7662	7262	0	0
T5	402	2	0	0
T12	527	127	0	0
T13	404	4	0	0
T14	493	93	0	0
T15	526	126	0	0
T16	406	6	0	0
T17	718	318	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	17	0	0
T4	707	1	0	0
T6	8924	0	0	0
T7	8003	0	0	0
T8	2340	0	0	0
T23	508	0	0	0
T25	5118	0	0	0
T30	1065	0	0	0
T39	0	2	0	0
T50	402	0	0	0
T51	604	0	0	0
T120	438	0	0	0
T151	0	1	0	0
T171	0	1	0	0
T177	0	1	0	0
T184	0	1	0	0
T199	0	1	0	0
T202	0	1	0	0
T212	0	1	0	0
T232	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T2,T12,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T2,T12,T3
1	1	Covered	T2,T12,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T2,T3,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T2	VC_COV_UNR
1	Covered	T2,T3,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T2,T3,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T12,T3
1	1	Covered	T2,T3,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T11
0	1	Covered	T37,T171,T177
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T11
0	1	Covered	T2,T11,T34
1	0	Covered	T3,T52

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T3,T11
1	-	Covered	T2,T11,T34

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T3,T11
DetectSt	168	Covered	T2,T3,T11
IdleSt	163	Covered	T5,T1,T2
StableSt	191	Covered	T2,T3,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T3,T11
DebounceSt->IdleSt	163	Covered	T153,T231,T181
DetectSt->IdleSt	186	Covered	T37,T171,T177
DetectSt->StableSt	191	Covered	T2,T3,T11
IdleSt->DebounceSt	148	Covered	T2,T3,T11
StableSt->IdleSt	206	Covered	T2,T3,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T3,T11
0	1	Covered	T2,T3,T11
0	0	Excluded	T5,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T11
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T3,T11
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T12
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T3,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T153,T231,T164
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T3,T11
DetectSt	-	-	-	-	1	-	-	Covered	T37,T171,T177
DetectSt	-	-	-	-	0	1	-	Covered	T2,T3,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T3,T11
StableSt	-	-	-	-	-	-	0	Covered	T2,T3,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5804184	134	0	0
CntIncr_A	5804184	117456	0	0
CntNoWrap_A	5804184	5191172	0	0
DetectStDropOut_A	5804184	5	0	0
DetectedOut_A	5804184	139072	0	0
DetectedPulseOut_A	5804184	58	0	0
DisabledIdleSt_A	5804184	4799163	0	0
DisabledNoDetection_A	5804184	4801374	0	0
EnterDebounceSt_A	5804184	72	0	0
EnterDetectSt_A	5804184	63	0	0
EnterStableSt_A	5804184	58	0	0
PulseIsPulse_A	5804184	58	0	0
StayInStableSt	5804184	138986	0	0
gen_high_level_sva.HighLevelEvent_A	5804184	5193579	0	0
gen_not_sticky_sva.StableStDropOut_A	5804184	28	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	134	0	0
T2	25810	4	0	0
T3	7662	2	0	0
T4	707	0	0	0
T11	0	6	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T34	0	4	0	0
T37	0	2	0	0
T38	0	4	0	0
T39	0	2	0	0
T40	0	2	0	0
T63	0	2	0	0
T171	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	117456	0	0
T2	25810	34	0	0
T3	7662	36	0	0
T4	707	0	0	0
T11	0	95	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T34	0	144	0	0
T37	0	13	0	0
T38	0	32	0	0
T39	0	95	0	0
T40	0	85	0	0
T63	0	48	0	0
T171	0	41	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	5191172	0	0
T1	486	85	0	0
T2	25810	24158	0	0
T3	7662	7259	0	0
T5	402	1	0	0
T12	527	126	0	0
T13	404	3	0	0
T14	493	92	0	0
T15	526	125	0	0
T16	406	5	0	0
T17	718	317	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	5	0	0
T37	478	1	0	0
T38	566	0	0	0
T73	4916	0	0	0
T80	630	0	0	0
T117	702	0	0	0
T118	676	0	0	0
T122	32845	0	0	0
T132	1355	0	0	0
T167	0	1	0	0
T171	0	1	0	0
T177	0	1	0	0
T193	422	0	0	0
T194	2953	0	0	0
T233	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	139072	0	0
T2	25810	41	0	0
T3	7662	2	0	0
T4	707	0	0	0
T11	0	189	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T34	0	210	0	0
T38	0	7	0	0
T39	0	635	0	0
T40	0	26	0	0
T63	0	47	0	0
T152	0	33	0	0
T172	0	271	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	58	0	0
T2	25810	2	0	0
T3	7662	1	0	0
T4	707	0	0	0
T11	0	3	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T34	0	2	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	0	1	0	0
T63	0	1	0	0
T152	0	1	0	0
T172	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	4799163	0	0
T1	486	3	0	0
T2	25810	23928	0	0
T3	7662	7220	0	0
T5	402	1	0	0
T12	527	126	0	0
T13	404	3	0	0
T14	493	92	0	0
T15	526	125	0	0
T16	406	5	0	0
T17	718	317	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	4801374	0	0
T1	486	3	0	0
T2	25810	23936	0	0
T3	7662	7221	0	0
T5	402	2	0	0
T12	527	127	0	0
T13	404	4	0	0
T14	493	93	0	0
T15	526	126	0	0
T16	406	6	0	0
T17	718	318	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	72	0	0
T2	25810	2	0	0
T3	7662	1	0	0
T4	707	0	0	0
T11	0	3	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T34	0	2	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	0	1	0	0
T63	0	1	0	0
T171	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	63	0	0
T2	25810	2	0	0
T3	7662	1	0	0
T4	707	0	0	0
T11	0	3	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T34	0	2	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	0	1	0	0
T63	0	1	0	0
T171	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	58	0	0
T2	25810	2	0	0
T3	7662	1	0	0
T4	707	0	0	0
T11	0	3	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T34	0	2	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	0	1	0	0
T63	0	1	0	0
T152	0	1	0	0
T172	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	58	0	0
T2	25810	2	0	0
T3	7662	1	0	0
T4	707	0	0	0
T11	0	3	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T34	0	2	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	0	1	0	0
T63	0	1	0	0
T152	0	1	0	0
T172	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	138986	0	0
T2	25810	38	0	0
T3	7662	1	0	0
T4	707	0	0	0
T11	0	184	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T34	0	208	0	0
T38	0	5	0	0
T39	0	633	0	0
T40	0	25	0	0
T63	0	46	0	0
T152	0	32	0	0
T172	0	267	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	5193579	0	0
T1	486	86	0	0
T2	25810	24171	0	0
T3	7662	7262	0	0
T5	402	2	0	0
T12	527	127	0	0
T13	404	4	0	0
T14	493	93	0	0
T15	526	126	0	0
T16	406	6	0	0
T17	718	318	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	28	0	0
T2	25810	1	0	0
T3	7662	0	0	0
T4	707	0	0	0
T11	0	1	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T34	0	2	0	0
T38	0	2	0	0
T40	0	1	0	0
T63	0	1	0	0
T93	0	1	0	0
T152	0	1	0	0
T172	0	2	0	0
T183	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T12,T3
1	Covered	T5,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T12,T3
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T3,T11,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T2	VC_COV_UNR
1	Covered	T3,T11,T36

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T3,T11,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T11
1	0	Covered	T2,T12,T3
1	1	Covered	T3,T11,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T11,T36
0	1	Covered	T211
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T11,T36
0	1	Covered	T151,T172,T153
1	0	Covered	T3,T52

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T11,T36
1	-	Covered	T151,T172,T153

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T11,T36
DetectSt	168	Covered	T3,T11,T36
IdleSt	163	Covered	T5,T1,T2
StableSt	191	Covered	T3,T11,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T11,T36
DebounceSt->IdleSt	163	Covered	T151,T201
DetectSt->IdleSt	186	Covered	T211
DetectSt->StableSt	191	Covered	T3,T11,T36
IdleSt->DebounceSt	148	Covered	T3,T11,T36
StableSt->IdleSt	206	Covered	T3,T11,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T11,T36
0	1	Covered	T3,T11,T36
0	0	Excluded	T5,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T11,T36
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T11,T36
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T2
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T11,T36
DebounceSt	-	0	1	0	-	-	-	Covered	T151,T201
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T11,T36
DetectSt	-	-	-	-	1	-	-	Covered	T211
DetectSt	-	-	-	-	0	1	-	Covered	T3,T11,T36
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T151,T172
StableSt	-	-	-	-	-	-	0	Covered	T3,T11,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5804184	74	0	0
CntIncr_A	5804184	80766	0	0
CntNoWrap_A	5804184	5191232	0	0
DetectStDropOut_A	5804184	1	0	0
DetectedOut_A	5804184	56669	0	0
DetectedPulseOut_A	5804184	35	0	0
DisabledIdleSt_A	5804184	4742236	0	0
DisabledNoDetection_A	5804184	4744460	0	0
EnterDebounceSt_A	5804184	38	0	0
EnterDetectSt_A	5804184	36	0	0
EnterStableSt_A	5804184	35	0	0
PulseIsPulse_A	5804184	35	0	0
StayInStableSt	5804184	56613	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5804184	6176	0	0
gen_low_level_sva.LowLevelEvent_A	5804184	5193579	0	0
gen_not_sticky_sva.StableStDropOut_A	5804184	12	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	74	0	0
T3	7662	2	0	0
T4	707	0	0	0
T6	8924	0	0	0
T11	0	2	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T36	0	2	0	0
T37	0	2	0	0
T50	402	0	0	0
T51	604	0	0	0
T74	0	2	0	0
T151	0	3	0	0
T152	0	2	0	0
T153	0	2	0	0
T172	0	4	0	0
T195	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	80766	0	0
T3	7662	36	0	0
T4	707	0	0	0
T6	8924	0	0	0
T11	0	46	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T36	0	26	0	0
T37	0	13	0	0
T50	402	0	0	0
T51	604	0	0	0
T74	0	90	0	0
T151	0	86	0	0
T152	0	37	0	0
T153	0	50	0	0
T172	0	176	0	0
T195	0	52	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	5191232	0	0
T1	486	85	0	0
T2	25810	24162	0	0
T3	7662	7259	0	0
T5	402	1	0	0
T12	527	126	0	0
T13	404	3	0	0
T14	493	92	0	0
T15	526	125	0	0
T16	406	5	0	0
T17	718	317	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	1	0	0
T211	742	1	0	0
T234	9990	0	0	0
T235	439	0	0	0
T236	15075	0	0	0
T237	421	0	0	0
T238	31910	0	0	0
T239	424	0	0	0
T240	402	0	0	0
T241	520	0	0	0
T242	665	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	56669	0	0
T3	7662	2	0	0
T4	707	0	0	0
T6	8924	0	0	0
T11	0	44	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T36	0	39	0	0
T37	0	42	0	0
T50	402	0	0	0
T51	604	0	0	0
T74	0	40	0	0
T151	0	10	0	0
T152	0	43	0	0
T153	0	44	0	0
T172	0	121	0	0
T195	0	42	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	35	0	0
T3	7662	1	0	0
T4	707	0	0	0
T6	8924	0	0	0
T11	0	1	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T50	402	0	0	0
T51	604	0	0	0
T74	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0
T153	0	1	0	0
T172	0	2	0	0
T195	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	4742236	0	0
T1	486	3	0	0
T2	25810	24162	0	0
T3	7662	7219	0	0
T5	402	1	0	0
T12	527	126	0	0
T13	404	3	0	0
T14	493	92	0	0
T15	526	125	0	0
T16	406	5	0	0
T17	718	317	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	4744460	0	0
T1	486	3	0	0
T2	25810	24171	0	0
T3	7662	7220	0	0
T5	402	2	0	0
T12	527	127	0	0
T13	404	4	0	0
T14	493	93	0	0
T15	526	126	0	0
T16	406	6	0	0
T17	718	318	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	38	0	0
T3	7662	1	0	0
T4	707	0	0	0
T6	8924	0	0	0
T11	0	1	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T50	402	0	0	0
T51	604	0	0	0
T74	0	1	0	0
T151	0	2	0	0
T152	0	1	0	0
T153	0	1	0	0
T172	0	2	0	0
T195	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	36	0	0
T3	7662	1	0	0
T4	707	0	0	0
T6	8924	0	0	0
T11	0	1	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T50	402	0	0	0
T51	604	0	0	0
T74	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0
T153	0	1	0	0
T172	0	2	0	0
T195	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	35	0	0
T3	7662	1	0	0
T4	707	0	0	0
T6	8924	0	0	0
T11	0	1	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T50	402	0	0	0
T51	604	0	0	0
T74	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0
T153	0	1	0	0
T172	0	2	0	0
T195	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	35	0	0
T3	7662	1	0	0
T4	707	0	0	0
T6	8924	0	0	0
T11	0	1	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T50	402	0	0	0
T51	604	0	0	0
T74	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0
T153	0	1	0	0
T172	0	2	0	0
T195	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	56613	0	0
T3	7662	1	0	0
T4	707	0	0	0
T6	8924	0	0	0
T11	0	42	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T36	0	37	0	0
T37	0	40	0	0
T50	402	0	0	0
T51	604	0	0	0
T74	0	38	0	0
T151	0	9	0	0
T152	0	41	0	0
T153	0	43	0	0
T172	0	119	0	0
T195	0	40	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	6176	0	0
T2	25810	28	0	0
T3	7662	23	0	0
T4	707	1	0	0
T6	0	16	0	0
T7	0	18	0	0
T12	527	3	0	0
T13	404	0	0	0
T14	493	11	0	0
T15	526	6	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	22	0	0
T120	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	5193579	0	0
T1	486	86	0	0
T2	25810	24171	0	0
T3	7662	7262	0	0
T5	402	2	0	0
T12	527	127	0	0
T13	404	4	0	0
T14	493	93	0	0
T15	526	126	0	0
T16	406	6	0	0
T17	718	318	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	12	0	0
T61	2645	0	0	0
T62	2756	0	0	0
T63	6596	0	0	0
T75	2428	0	0	0
T91	10792	0	0	0
T149	0	1	0	0
T151	7568	1	0	0
T153	0	1	0	0
T163	0	1	0	0
T172	0	2	0	0
T181	0	1	0	0
T183	0	1	0	0
T192	0	1	0	0
T196	0	1	0	0
T202	0	1	0	0
T243	650	0	0	0
T244	8024	0	0	0
T245	403	0	0	0
T246	36038	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T2,T12,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T2,T12,T3
1	1	Covered	T2,T12,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T2,T3,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T2	VC_COV_UNR
1	Covered	T2,T3,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T2,T3,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T11
1	0	Covered	T2,T12,T3
1	1	Covered	T2,T3,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T11
0	1	Covered	T247
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T11
0	1	Covered	T2,T35,T38
1	0	Covered	T3,T52

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T3,T11
1	-	Covered	T2,T35,T38

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T3,T11
DetectSt	168	Covered	T2,T3,T11
IdleSt	163	Covered	T5,T1,T2
StableSt	191	Covered	T2,T3,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T3,T11
DebounceSt->IdleSt	163	Covered	T71,T36,T183
DetectSt->IdleSt	186	Covered	T247
DetectSt->StableSt	191	Covered	T2,T3,T11
IdleSt->DebounceSt	148	Covered	T2,T3,T11
StableSt->IdleSt	206	Covered	T2,T3,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T3,T11
0	1	Covered	T2,T3,T11
0	0	Excluded	T5,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T11
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T3,T11
IdleSt	0	-	-	-	-	-	-	Covered	T2,T12,T3
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T3,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T71,T36,T183
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T3,T11
DetectSt	-	-	-	-	1	-	-	Covered	T247
DetectSt	-	-	-	-	0	1	-	Covered	T2,T3,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T3,T35
StableSt	-	-	-	-	-	-	0	Covered	T2,T3,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5804184	117	0	0
CntIncr_A	5804184	137117	0	0
CntNoWrap_A	5804184	5191189	0	0
DetectStDropOut_A	5804184	1	0	0
DetectedOut_A	5804184	42882	0	0
DetectedPulseOut_A	5804184	55	0	0
DisabledIdleSt_A	5804184	4710801	0	0
DisabledNoDetection_A	5804184	4713017	0	0
EnterDebounceSt_A	5804184	61	0	0
EnterDetectSt_A	5804184	56	0	0
EnterStableSt_A	5804184	55	0	0
PulseIsPulse_A	5804184	55	0	0
StayInStableSt	5804184	42797	0	0
gen_high_level_sva.HighLevelEvent_A	5804184	5193579	0	0
gen_not_sticky_sva.StableStDropOut_A	5804184	23	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	117	0	0
T2	25810	2	0	0
T3	7662	2	0	0
T4	707	0	0	0
T11	0	2	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T35	0	2	0	0
T36	0	1	0	0
T38	0	4	0	0
T39	0	2	0	0
T71	0	1	0	0
T80	0	2	0	0
T173	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	137117	0	0
T2	25810	17	0	0
T3	7662	36	0	0
T4	707	0	0	0
T11	0	14	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T35	0	34	0	0
T36	0	26	0	0
T38	0	32	0	0
T39	0	95	0	0
T71	0	44862	0	0
T80	0	88	0	0
T173	0	60	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	5191189	0	0
T1	486	85	0	0
T2	25810	24160	0	0
T3	7662	7259	0	0
T5	402	1	0	0
T12	527	126	0	0
T13	404	3	0	0
T14	493	92	0	0
T15	526	125	0	0
T16	406	5	0	0
T17	718	317	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	1	0	0
T213	663	0	0	0
T247	4166	1	0	0
T248	21196	0	0	0
T249	10416	0	0	0
T250	424	0	0	0
T251	406	0	0	0
T252	506	0	0	0
T253	219399	0	0	0
T254	504	0	0	0
T255	402	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	42882	0	0
T2	25810	77	0	0
T3	7662	4	0	0
T4	707	0	0	0
T11	0	40	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T35	0	28	0	0
T38	0	46	0	0
T39	0	170	0	0
T80	0	133	0	0
T93	0	47	0	0
T153	0	212	0	0
T173	0	30	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	55	0	0
T2	25810	1	0	0
T3	7662	1	0	0
T4	707	0	0	0
T11	0	1	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T35	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T80	0	1	0	0
T93	0	1	0	0
T153	0	1	0	0
T173	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	4710801	0	0
T1	486	85	0	0
T2	25810	23928	0	0
T3	7662	7219	0	0
T5	402	1	0	0
T12	527	126	0	0
T13	404	3	0	0
T14	493	92	0	0
T15	526	125	0	0
T16	406	5	0	0
T17	718	317	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	4713017	0	0
T1	486	86	0	0
T2	25810	23936	0	0
T3	7662	7220	0	0
T5	402	2	0	0
T12	527	127	0	0
T13	404	4	0	0
T14	493	93	0	0
T15	526	126	0	0
T16	406	6	0	0
T17	718	318	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	61	0	0
T2	25810	1	0	0
T3	7662	1	0	0
T4	707	0	0	0
T11	0	1	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T71	0	1	0	0
T80	0	1	0	0
T173	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	56	0	0
T2	25810	1	0	0
T3	7662	1	0	0
T4	707	0	0	0
T11	0	1	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T35	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T80	0	1	0	0
T93	0	1	0	0
T153	0	1	0	0
T173	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	55	0	0
T2	25810	1	0	0
T3	7662	1	0	0
T4	707	0	0	0
T11	0	1	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T35	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T80	0	1	0	0
T93	0	1	0	0
T153	0	1	0	0
T173	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	55	0	0
T2	25810	1	0	0
T3	7662	1	0	0
T4	707	0	0	0
T11	0	1	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T35	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T80	0	1	0	0
T93	0	1	0	0
T153	0	1	0	0
T173	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	42797	0	0
T2	25810	76	0	0
T3	7662	3	0	0
T4	707	0	0	0
T11	0	38	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T35	0	27	0	0
T38	0	43	0	0
T39	0	168	0	0
T80	0	131	0	0
T93	0	45	0	0
T153	0	210	0	0
T173	0	29	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	5193579	0	0
T1	486	86	0	0
T2	25810	24171	0	0
T3	7662	7262	0	0
T5	402	2	0	0
T12	527	127	0	0
T13	404	4	0	0
T14	493	93	0	0
T15	526	126	0	0
T16	406	6	0	0
T17	718	318	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	23	0	0
T2	25810	1	0	0
T3	7662	0	0	0
T4	707	0	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T35	0	1	0	0
T38	0	1	0	0
T149	0	1	0	0
T173	0	1	0	0
T177	0	2	0	0
T178	0	1	0	0
T185	0	1	0	0
T199	0	1	0	0
T201	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T12,T3
1	Covered	T5,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T12,T3
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T3,T34,T35

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T2	VC_COV_UNR
1	Covered	T3,T34,T35

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T3,T34,T35

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T2,T12,T3
1	1	Covered	T3,T34,T35

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T34,T35
0	1	Covered	T149
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T34,T35
0	1	Covered	T34,T38,T212
1	0	Covered	T3,T52

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T34,T35
1	-	Covered	T34,T38,T212

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T34,T35
DetectSt	168	Covered	T3,T34,T35
IdleSt	163	Covered	T5,T1,T2
StableSt	191	Covered	T3,T34,T35

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T34,T35
DebounceSt->IdleSt	163	Covered	T174
DetectSt->IdleSt	186	Covered	T149
DetectSt->StableSt	191	Covered	T3,T34,T35
IdleSt->DebounceSt	148	Covered	T3,T34,T35
StableSt->IdleSt	206	Covered	T3,T34,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T34,T35
0	1	Covered	T3,T34,T35
0	0	Excluded	T5,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T34,T35
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T34,T35
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T2
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T34,T35
DebounceSt	-	0	1	0	-	-	-	Covered	T174
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T34,T35
DetectSt	-	-	-	-	1	-	-	Covered	T149
DetectSt	-	-	-	-	0	1	-	Covered	T3,T34,T35
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T34,T38
StableSt	-	-	-	-	-	-	0	Covered	T3,T34,T35
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5804184	51	0	0
CntIncr_A	5804184	55721	0	0
CntNoWrap_A	5804184	5191255	0	0
DetectStDropOut_A	5804184	1	0	0
DetectedOut_A	5804184	148027	0	0
DetectedPulseOut_A	5804184	24	0	0
DisabledIdleSt_A	5804184	4928174	0	0
DisabledNoDetection_A	5804184	4930393	0	0
EnterDebounceSt_A	5804184	26	0	0
EnterDetectSt_A	5804184	25	0	0
EnterStableSt_A	5804184	24	0	0
PulseIsPulse_A	5804184	24	0	0
StayInStableSt	5804184	147988	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5804184	6832	0	0
gen_low_level_sva.LowLevelEvent_A	5804184	5193579	0	0
gen_not_sticky_sva.StableStDropOut_A	5804184	7	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	51	0	0
T3	7662	2	0	0
T4	707	0	0	0
T6	8924	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T34	0	2	0	0
T35	0	2	0	0
T36	0	2	0	0
T38	0	2	0	0
T50	402	0	0	0
T51	604	0	0	0
T63	0	2	0	0
T173	0	2	0	0
T201	0	2	0	0
T212	0	2	0	0
T256	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	55721	0	0
T3	7662	36	0	0
T4	707	0	0	0
T6	8924	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T34	0	72	0	0
T35	0	34	0	0
T36	0	26	0	0
T38	0	16	0	0
T50	402	0	0	0
T51	604	0	0	0
T63	0	48	0	0
T173	0	60	0	0
T201	0	81	0	0
T212	0	71	0	0
T256	0	15069	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	5191255	0	0
T1	486	85	0	0
T2	25810	24162	0	0
T3	7662	7259	0	0
T5	402	1	0	0
T12	527	126	0	0
T13	404	3	0	0
T14	493	92	0	0
T15	526	125	0	0
T16	406	5	0	0
T17	718	317	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	1	0	0
T149	117057	1	0	0
T154	678	0	0	0
T155	3050	0	0	0
T156	641	0	0	0
T157	13582	0	0	0
T158	32919	0	0	0
T159	836	0	0	0
T160	488	0	0	0
T161	18705	0	0	0
T162	534	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	148027	0	0
T3	7662	2	0	0
T4	707	0	0	0
T6	8924	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T34	0	176	0	0
T35	0	40	0	0
T36	0	39	0	0
T38	0	60	0	0
T50	402	0	0	0
T51	604	0	0	0
T63	0	51	0	0
T173	0	40	0	0
T201	0	167	0	0
T212	0	230	0	0
T256	0	44	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	24	0	0
T3	7662	1	0	0
T4	707	0	0	0
T6	8924	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T38	0	1	0	0
T50	402	0	0	0
T51	604	0	0	0
T63	0	1	0	0
T173	0	1	0	0
T201	0	1	0	0
T212	0	1	0	0
T256	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	4928174	0	0
T1	486	3	0	0
T2	25810	24162	0	0
T3	7662	7219	0	0
T5	402	1	0	0
T12	527	126	0	0
T13	404	3	0	0
T14	493	92	0	0
T15	526	125	0	0
T16	406	5	0	0
T17	718	317	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	4930393	0	0
T1	486	3	0	0
T2	25810	24171	0	0
T3	7662	7220	0	0
T5	402	2	0	0
T12	527	127	0	0
T13	404	4	0	0
T14	493	93	0	0
T15	526	126	0	0
T16	406	6	0	0
T17	718	318	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	26	0	0
T3	7662	1	0	0
T4	707	0	0	0
T6	8924	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T38	0	1	0	0
T50	402	0	0	0
T51	604	0	0	0
T63	0	1	0	0
T173	0	1	0	0
T201	0	1	0	0
T212	0	1	0	0
T256	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	25	0	0
T3	7662	1	0	0
T4	707	0	0	0
T6	8924	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T38	0	1	0	0
T50	402	0	0	0
T51	604	0	0	0
T63	0	1	0	0
T173	0	1	0	0
T201	0	1	0	0
T212	0	1	0	0
T256	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	24	0	0
T3	7662	1	0	0
T4	707	0	0	0
T6	8924	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T38	0	1	0	0
T50	402	0	0	0
T51	604	0	0	0
T63	0	1	0	0
T173	0	1	0	0
T201	0	1	0	0
T212	0	1	0	0
T256	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	24	0	0
T3	7662	1	0	0
T4	707	0	0	0
T6	8924	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T38	0	1	0	0
T50	402	0	0	0
T51	604	0	0	0
T63	0	1	0	0
T173	0	1	0	0
T201	0	1	0	0
T212	0	1	0	0
T256	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	147988	0	0
T3	7662	1	0	0
T4	707	0	0	0
T6	8924	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T34	0	175	0	0
T35	0	38	0	0
T36	0	37	0	0
T38	0	59	0	0
T50	402	0	0	0
T51	604	0	0	0
T63	0	49	0	0
T173	0	38	0	0
T201	0	165	0	0
T212	0	229	0	0
T256	0	42	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	6832	0	0
T2	25810	20	0	0
T3	7662	23	0	0
T4	707	0	0	0
T6	0	8	0	0
T7	0	21	0	0
T12	527	5	0	0
T13	404	0	0	0
T14	493	7	0	0
T15	526	4	0	0
T16	406	0	0	0
T17	718	3	0	0
T25	5118	25	0	0
T30	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	5193579	0	0
T1	486	86	0	0
T2	25810	24171	0	0
T3	7662	7262	0	0
T5	402	2	0	0
T12	527	127	0	0
T13	404	4	0	0
T14	493	93	0	0
T15	526	126	0	0
T16	406	6	0	0
T17	718	318	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	7	0	0
T21	489	0	0	0
T22	501	0	0	0
T34	1011	1	0	0
T38	0	1	0	0
T41	665	0	0	0
T42	790	0	0	0
T43	15008	0	0	0
T58	497	0	0	0
T70	525	0	0	0
T165	0	1	0	0
T166	0	2	0	0
T167	0	1	0	0
T168	427	0	0	0
T169	690	0	0	0
T212	0	1	0	0