Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T3,T25,T7
1	Covered	T5,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T3,T25,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T3,T25,T7

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T3,T25,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T25,T7
1	0	Covered	T3,T7,T9
1	1	Covered	T3,T25,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T25,T7
0	1	Covered	T3,T25,T10
1	0	Covered	T3,T10,T90

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T9
0	1	Covered	T3,T9,T33
1	0	Covered	T257

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T7,T9
1	-	Covered	T3,T9,T33

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T25,T7
DetectSt	168	Covered	T3,T25,T7
IdleSt	163	Covered	T5,T1,T2
StableSt	191	Covered	T3,T7,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T25,T7
DebounceSt->IdleSt	163	Covered	T3,T73,T258
DetectSt->IdleSt	186	Covered	T3,T25,T10
DetectSt->StableSt	191	Covered	T3,T7,T9
IdleSt->DebounceSt	148	Covered	T3,T25,T7
StableSt->IdleSt	206	Covered	T3,T7,T9

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T25,T7
0	1	Covered	T3,T25,T7
0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T25,T7
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T3,T25,T7
IdleSt	0	-	-	-	-	-	-	Covered	T3,T25,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T3,T52
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T25,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T3,T73,T258
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T25,T7
DetectSt	-	-	-	-	1	-	-	Covered	T3,T25,T10
DetectSt	-	-	-	-	0	1	-	Covered	T3,T7,T9
DetectSt	-	-	-	-	0	0	-	Covered	T3,T25,T7
StableSt	-	-	-	-	-	-	1	Covered	T3,T9,T33
StableSt	-	-	-	-	-	-	0	Covered	T3,T7,T9
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5804184	3123	0	0
CntIncr_A	5804184	106567	0	0
CntNoWrap_A	5804184	5188183	0	0
DetectStDropOut_A	5804184	386	0	0
DetectedOut_A	5804184	76052	0	0
DetectedPulseOut_A	5804184	919	0	0
DisabledIdleSt_A	5804184	4720785	0	0
DisabledNoDetection_A	5804184	4722857	0	0
EnterDebounceSt_A	5804184	1591	0	0
EnterDetectSt_A	5804184	1533	0	0
EnterStableSt_A	5804184	919	0	0
PulseIsPulse_A	5804184	919	0	0
StayInStableSt	5804184	75027	0	0
gen_high_event_sva.HighLevelEvent_A	5804184	5193579	0	0
gen_high_level_sva.HighLevelEvent_A	5804184	5193579	0	0
gen_not_sticky_sva.StableStDropOut_A	5804184	809	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	3123	0	0
T3	7662	16	0	0
T4	707	0	0	0
T6	8924	0	0	0
T7	0	2	0	0
T9	0	20	0	0
T10	0	44	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	16	0	0
T33	0	10	0	0
T46	0	20	0	0
T47	0	52	0	0
T50	402	0	0	0
T51	604	0	0	0
T72	0	20	0	0
T73	0	19	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	106567	0	0
T3	7662	444	0	0
T4	707	0	0	0
T6	8924	0	0	0
T7	0	57	0	0
T9	0	2290	0	0
T10	0	1171	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	394	0	0
T33	0	255	0	0
T46	0	505	0	0
T47	0	1612	0	0
T50	402	0	0	0
T51	604	0	0	0
T72	0	930	0	0
T73	0	960	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	5188183	0	0
T1	486	85	0	0
T2	25810	24162	0	0
T3	7662	7245	0	0
T5	402	1	0	0
T12	527	126	0	0
T13	404	3	0	0
T14	493	92	0	0
T15	526	125	0	0
T16	406	5	0	0
T17	718	317	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	386	0	0
T3	7662	1	0	0
T4	707	0	0	0
T6	8924	0	0	0
T10	0	16	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	8	0	0
T46	0	10	0	0
T50	402	0	0	0
T51	604	0	0	0
T79	0	19	0	0
T89	0	5	0	0
T90	0	23	0	0
T92	0	12	0	0
T94	0	12	0	0
T97	0	5	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	76052	0	0
T3	7662	457	0	0
T4	707	0	0	0
T6	8924	0	0	0
T7	0	316	0	0
T9	0	1901	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T33	0	437	0	0
T47	0	2237	0	0
T50	402	0	0	0
T51	604	0	0	0
T72	0	597	0	0
T119	0	239	0	0
T139	0	34	0	0
T141	0	885	0	0
T244	0	26	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	919	0	0
T3	7662	5	0	0
T4	707	0	0	0
T6	8924	0	0	0
T7	0	1	0	0
T9	0	10	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T33	0	5	0	0
T47	0	26	0	0
T50	402	0	0	0
T51	604	0	0	0
T72	0	10	0	0
T119	0	10	0	0
T139	0	1	0	0
T141	0	12	0	0
T244	0	8	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	4720785	0	0
T1	486	85	0	0
T2	25810	24162	0	0
T3	7662	6272	0	0
T5	402	1	0	0
T12	527	126	0	0
T13	404	3	0	0
T14	493	92	0	0
T15	526	125	0	0
T16	406	5	0	0
T17	718	317	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	4722857	0	0
T1	486	86	0	0
T2	25810	24171	0	0
T3	7662	6273	0	0
T5	402	2	0	0
T12	527	127	0	0
T13	404	4	0	0
T14	493	93	0	0
T15	526	126	0	0
T16	406	6	0	0
T17	718	318	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	1591	0	0
T3	7662	9	0	0
T4	707	0	0	0
T6	8924	0	0	0
T7	0	1	0	0
T9	0	10	0	0
T10	0	22	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	8	0	0
T33	0	5	0	0
T46	0	10	0	0
T47	0	26	0	0
T50	402	0	0	0
T51	604	0	0	0
T72	0	10	0	0
T73	0	20	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	1533	0	0
T3	7662	7	0	0
T4	707	0	0	0
T6	8924	0	0	0
T7	0	1	0	0
T9	0	10	0	0
T10	0	22	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	8	0	0
T33	0	5	0	0
T46	0	10	0	0
T47	0	26	0	0
T50	402	0	0	0
T51	604	0	0	0
T72	0	10	0	0
T119	0	10	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	919	0	0
T3	7662	5	0	0
T4	707	0	0	0
T6	8924	0	0	0
T7	0	1	0	0
T9	0	10	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T33	0	5	0	0
T47	0	26	0	0
T50	402	0	0	0
T51	604	0	0	0
T72	0	10	0	0
T119	0	10	0	0
T139	0	1	0	0
T141	0	12	0	0
T244	0	8	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	919	0	0
T3	7662	5	0	0
T4	707	0	0	0
T6	8924	0	0	0
T7	0	1	0	0
T9	0	10	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T33	0	5	0	0
T47	0	26	0	0
T50	402	0	0	0
T51	604	0	0	0
T72	0	10	0	0
T119	0	10	0	0
T139	0	1	0	0
T141	0	12	0	0
T244	0	8	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	75027	0	0
T3	7662	452	0	0
T4	707	0	0	0
T6	8924	0	0	0
T7	0	314	0	0
T9	0	1889	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T33	0	430	0	0
T47	0	2209	0	0
T50	402	0	0	0
T51	604	0	0	0
T72	0	586	0	0
T119	0	229	0	0
T139	0	32	0	0
T141	0	872	0	0
T244	0	18	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	5193579	0	0
T1	486	86	0	0
T2	25810	24171	0	0
T3	7662	7262	0	0
T5	402	2	0	0
T12	527	127	0	0
T13	404	4	0	0
T14	493	93	0	0
T15	526	126	0	0
T16	406	6	0	0
T17	718	318	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	5193579	0	0
T1	486	86	0	0
T2	25810	24171	0	0
T3	7662	7262	0	0
T5	402	2	0	0
T12	527	127	0	0
T13	404	4	0	0
T14	493	93	0	0
T15	526	126	0	0
T16	406	6	0	0
T17	718	318	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	809	0	0
T3	7662	5	0	0
T4	707	0	0	0
T6	8924	0	0	0
T9	0	8	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T33	0	3	0	0
T47	0	24	0	0
T50	402	0	0	0
T51	604	0	0	0
T72	0	9	0	0
T119	0	10	0	0
T141	0	11	0	0
T244	0	8	0	0
T259	0	9	0	0
T260	0	10	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T25
1	Covered	T5,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T25
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T2,T3,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T2	VC_COV_UNR
1	Covered	T2,T3,T7

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T2,T3,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T25
1	1	Covered	T2,T3,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T7
0	1	Covered	T88,T91,T93
1	0	Covered	T3,T52

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T7
0	1	Covered	T2,T7,T9
1	0	Covered	T52

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T3,T7
1	-	Covered	T2,T3,T7

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T3,T7
DetectSt	168	Covered	T2,T3,T7
IdleSt	163	Covered	T5,T1,T2
StableSt	191	Covered	T2,T3,T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T3,T7
DebounceSt->IdleSt	163	Covered	T2,T3,T11
DetectSt->IdleSt	186	Covered	T3,T88,T91
DetectSt->StableSt	191	Covered	T2,T3,T7
IdleSt->DebounceSt	148	Covered	T2,T3,T7
StableSt->IdleSt	206	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T3,T7
0	1	Covered	T2,T3,T7
0	0	Excluded	T5,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T3,T7
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T3,T52
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T3,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T11,T32
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T3,T7
DetectSt	-	-	-	-	1	-	-	Covered	T3,T88,T91
DetectSt	-	-	-	-	0	1	-	Covered	T2,T3,T7
DetectSt	-	-	-	-	0	0	-	Covered	T2,T3,T7
StableSt	-	-	-	-	-	-	1	Covered	T2,T3,T7
StableSt	-	-	-	-	-	-	0	Covered	T2,T3,T7
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5804184	952	0	0
CntIncr_A	5804184	51311	0	0
CntNoWrap_A	5804184	5190354	0	0
DetectStDropOut_A	5804184	59	0	0
DetectedOut_A	5804184	15662	0	0
DetectedPulseOut_A	5804184	372	0	0
DisabledIdleSt_A	5804184	4804244	0	0
DisabledNoDetection_A	5804184	4805796	0	0
EnterDebounceSt_A	5804184	518	0	0
EnterDetectSt_A	5804184	435	0	0
EnterStableSt_A	5804184	372	0	0
PulseIsPulse_A	5804184	372	0	0
StayInStableSt	5804184	15249	0	0
gen_high_level_sva.HighLevelEvent_A	5804184	5193579	0	0
gen_not_sticky_sva.StableStDropOut_A	5804184	327	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	952	0	0
T2	25810	18	0	0
T3	7662	8	0	0
T4	707	0	0	0
T7	0	2	0	0
T9	0	6	0	0
T11	0	8	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T32	0	1	0	0
T33	0	2	0	0
T43	0	8	0	0
T47	0	2	0	0
T86	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	51311	0	0
T2	25810	943	0	0
T3	7662	307	0	0
T4	707	0	0	0
T7	0	96	0	0
T9	0	669	0	0
T11	0	252	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T32	0	14	0	0
T33	0	83	0	0
T43	0	274	0	0
T47	0	97	0	0
T86	0	25	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	5190354	0	0
T1	486	85	0	0
T2	25810	24144	0	0
T3	7662	7253	0	0
T5	402	1	0	0
T12	527	126	0	0
T13	404	3	0	0
T14	493	92	0	0
T15	526	125	0	0
T16	406	5	0	0
T17	718	317	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	59	0	0
T52	0	1	0	0
T88	25236	4	0	0
T89	4616	0	0	0
T90	18156	0	0	0
T91	0	6	0	0
T93	0	3	0	0
T95	0	2	0	0
T96	0	10	0	0
T98	0	3	0	0
T99	0	1	0	0
T100	0	3	0	0
T101	0	6	0	0
T102	522	0	0	0
T103	556	0	0	0
T104	703	0	0	0
T105	652	0	0	0
T106	430	0	0	0
T107	525	0	0	0
T108	402	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	15662	0	0
T2	25810	616	0	0
T3	7662	82	0	0
T4	707	0	0	0
T7	0	53	0	0
T9	0	261	0	0
T11	0	12	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T33	0	70	0	0
T43	0	107	0	0
T47	0	51	0	0
T72	0	94	0	0
T86	0	3	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	372	0	0
T2	25810	8	0	0
T3	7662	1	0	0
T4	707	0	0	0
T7	0	1	0	0
T9	0	3	0	0
T11	0	3	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T33	0	1	0	0
T43	0	4	0	0
T47	0	1	0	0
T72	0	1	0	0
T86	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	4804244	0	0
T1	486	85	0	0
T2	25810	16352	0	0
T3	7662	6800	0	0
T5	402	1	0	0
T12	527	126	0	0
T13	404	3	0	0
T14	493	92	0	0
T15	526	125	0	0
T16	406	5	0	0
T17	718	317	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	4805796	0	0
T1	486	86	0	0
T2	25810	16353	0	0
T3	7662	6801	0	0
T5	402	2	0	0
T12	527	127	0	0
T13	404	4	0	0
T14	493	93	0	0
T15	526	126	0	0
T16	406	6	0	0
T17	718	318	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	518	0	0
T2	25810	10	0	0
T3	7662	5	0	0
T4	707	0	0	0
T7	0	1	0	0
T9	0	3	0	0
T11	0	5	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T32	0	1	0	0
T33	0	1	0	0
T43	0	4	0	0
T47	0	1	0	0
T86	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	435	0	0
T2	25810	8	0	0
T3	7662	3	0	0
T4	707	0	0	0
T7	0	1	0	0
T9	0	3	0	0
T11	0	3	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T33	0	1	0	0
T43	0	4	0	0
T47	0	1	0	0
T72	0	1	0	0
T86	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	372	0	0
T2	25810	8	0	0
T3	7662	1	0	0
T4	707	0	0	0
T7	0	1	0	0
T9	0	3	0	0
T11	0	3	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T33	0	1	0	0
T43	0	4	0	0
T47	0	1	0	0
T72	0	1	0	0
T86	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	372	0	0
T2	25810	8	0	0
T3	7662	1	0	0
T4	707	0	0	0
T7	0	1	0	0
T9	0	3	0	0
T11	0	3	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T33	0	1	0	0
T43	0	4	0	0
T47	0	1	0	0
T72	0	1	0	0
T86	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	15249	0	0
T2	25810	608	0	0
T3	7662	81	0	0
T4	707	0	0	0
T7	0	52	0	0
T9	0	257	0	0
T11	0	9	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T33	0	69	0	0
T43	0	103	0	0
T47	0	49	0	0
T72	0	93	0	0
T86	0	2	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	5193579	0	0
T1	486	86	0	0
T2	25810	24171	0	0
T3	7662	7262	0	0
T5	402	2	0	0
T12	527	127	0	0
T13	404	4	0	0
T14	493	93	0	0
T15	526	126	0	0
T16	406	6	0	0
T17	718	318	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	327	0	0
T2	25810	8	0	0
T3	7662	0	0	0
T4	707	0	0	0
T7	0	1	0	0
T9	0	2	0	0
T11	0	3	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T33	0	1	0	0
T36	0	1	0	0
T43	0	4	0	0
T72	0	1	0	0
T86	0	1	0	0
T122	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T3,T25,T7
1	Covered	T5,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T3,T25,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T3,T25,T7

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T3,T25,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T25,T7
1	0	Covered	T3,T7,T9
1	1	Covered	T3,T25,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T25,T7
0	1	Covered	T3,T25,T7
1	0	Covered	T3,T7,T119

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T9,T10
0	1	Covered	T3,T9,T10
1	0	Covered	T81,T52,T261

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T9,T10
1	-	Covered	T3,T9,T10

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T25,T7
DetectSt	168	Covered	T3,T25,T7
IdleSt	163	Covered	T5,T1,T2
StableSt	191	Covered	T3,T9,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T25,T7
DebounceSt->IdleSt	163	Covered	T3,T73,T258
DetectSt->IdleSt	186	Covered	T3,T25,T7
DetectSt->StableSt	191	Covered	T3,T9,T10
IdleSt->DebounceSt	148	Covered	T3,T25,T7
StableSt->IdleSt	206	Covered	T3,T9,T10

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T25,T7
0	1	Covered	T3,T25,T7
0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T25,T7
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T3,T25,T7
IdleSt	0	-	-	-	-	-	-	Covered	T3,T25,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T3,T52
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T25,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T3,T73,T258
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T25,T7
DetectSt	-	-	-	-	1	-	-	Covered	T3,T25,T7
DetectSt	-	-	-	-	0	1	-	Covered	T3,T9,T10
DetectSt	-	-	-	-	0	0	-	Covered	T3,T25,T7
StableSt	-	-	-	-	-	-	1	Covered	T3,T9,T10
StableSt	-	-	-	-	-	-	0	Covered	T3,T9,T10
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5804184	2946	0	0
CntIncr_A	5804184	97142	0	0
CntNoWrap_A	5804184	5188360	0	0
DetectStDropOut_A	5804184	322	0	0
DetectedOut_A	5804184	80012	0	0
DetectedPulseOut_A	5804184	991	0	0
DisabledIdleSt_A	5804184	4721595	0	0
DisabledNoDetection_A	5804184	4723638	0	0
EnterDebounceSt_A	5804184	1494	0	0
EnterDetectSt_A	5804184	1452	0	0
EnterStableSt_A	5804184	991	0	0
PulseIsPulse_A	5804184	991	0	0
StayInStableSt	5804184	78887	0	0
gen_high_event_sva.HighLevelEvent_A	5804184	5193579	0	0
gen_high_level_sva.HighLevelEvent_A	5804184	5193579	0	0
gen_not_sticky_sva.StableStDropOut_A	5804184	843	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	2946	0	0
T3	7662	16	0	0
T4	707	0	0	0
T6	8924	0	0	0
T7	0	36	0	0
T9	0	14	0	0
T10	0	30	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	16	0	0
T33	0	14	0	0
T46	0	44	0	0
T47	0	32	0	0
T50	402	0	0	0
T51	604	0	0	0
T72	0	28	0	0
T73	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	97142	0	0
T3	7662	583	0	0
T4	707	0	0	0
T6	8924	0	0	0
T7	0	1103	0	0
T9	0	1708	0	0
T10	0	615	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	394	0	0
T33	0	343	0	0
T46	0	1123	0	0
T47	0	1312	0	0
T50	402	0	0	0
T51	604	0	0	0
T72	0	1302	0	0
T73	0	192	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	5188360	0	0
T1	486	85	0	0
T2	25810	24162	0	0
T3	7662	7245	0	0
T5	402	1	0	0
T12	527	126	0	0
T13	404	3	0	0
T14	493	92	0	0
T15	526	125	0	0
T16	406	5	0	0
T17	718	317	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	322	0	0
T3	7662	1	0	0
T4	707	0	0	0
T6	8924	0	0	0
T7	0	17	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	8	0	0
T46	0	22	0	0
T50	402	0	0	0
T51	604	0	0	0
T89	0	13	0	0
T90	0	15	0	0
T92	0	5	0	0
T94	0	22	0	0
T97	0	15	0	0
T262	0	18	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	80012	0	0
T3	7662	369	0	0
T4	707	0	0	0
T6	8924	0	0	0
T9	0	977	0	0
T10	0	1853	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T33	0	497	0	0
T47	0	1131	0	0
T50	402	0	0	0
T51	604	0	0	0
T72	0	3322	0	0
T79	0	772	0	0
T141	0	2289	0	0
T244	0	1739	0	0
T260	0	501	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	991	0	0
T3	7662	5	0	0
T4	707	0	0	0
T6	8924	0	0	0
T9	0	7	0	0
T10	0	15	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T33	0	7	0	0
T47	0	16	0	0
T50	402	0	0	0
T51	604	0	0	0
T72	0	14	0	0
T79	0	6	0	0
T141	0	29	0	0
T244	0	25	0	0
T260	0	15	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	4721595	0	0
T1	486	85	0	0
T2	25810	24162	0	0
T3	7662	6219	0	0
T5	402	1	0	0
T12	527	126	0	0
T13	404	3	0	0
T14	493	92	0	0
T15	526	125	0	0
T16	406	5	0	0
T17	718	317	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	4723638	0	0
T1	486	86	0	0
T2	25810	24171	0	0
T3	7662	6220	0	0
T5	402	2	0	0
T12	527	127	0	0
T13	404	4	0	0
T14	493	93	0	0
T15	526	126	0	0
T16	406	6	0	0
T17	718	318	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	1494	0	0
T3	7662	9	0	0
T4	707	0	0	0
T6	8924	0	0	0
T7	0	18	0	0
T9	0	7	0	0
T10	0	15	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	8	0	0
T33	0	7	0	0
T46	0	22	0	0
T47	0	16	0	0
T50	402	0	0	0
T51	604	0	0	0
T72	0	14	0	0
T73	0	4	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	1452	0	0
T3	7662	7	0	0
T4	707	0	0	0
T6	8924	0	0	0
T7	0	18	0	0
T9	0	7	0	0
T10	0	15	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	8	0	0
T33	0	7	0	0
T46	0	22	0	0
T47	0	16	0	0
T50	402	0	0	0
T51	604	0	0	0
T72	0	14	0	0
T119	0	7	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	991	0	0
T3	7662	5	0	0
T4	707	0	0	0
T6	8924	0	0	0
T9	0	7	0	0
T10	0	15	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T33	0	7	0	0
T47	0	16	0	0
T50	402	0	0	0
T51	604	0	0	0
T72	0	14	0	0
T79	0	6	0	0
T141	0	29	0	0
T244	0	25	0	0
T260	0	15	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	991	0	0
T3	7662	5	0	0
T4	707	0	0	0
T6	8924	0	0	0
T9	0	7	0	0
T10	0	15	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T33	0	7	0	0
T47	0	16	0	0
T50	402	0	0	0
T51	604	0	0	0
T72	0	14	0	0
T79	0	6	0	0
T141	0	29	0	0
T244	0	25	0	0
T260	0	15	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	78887	0	0
T3	7662	364	0	0
T4	707	0	0	0
T6	8924	0	0	0
T9	0	968	0	0
T10	0	1833	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T33	0	488	0	0
T47	0	1114	0	0
T50	402	0	0	0
T51	604	0	0	0
T72	0	3303	0	0
T79	0	766	0	0
T141	0	2252	0	0
T244	0	1714	0	0
T260	0	485	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	5193579	0	0
T1	486	86	0	0
T2	25810	24171	0	0
T3	7662	7262	0	0
T5	402	2	0	0
T12	527	127	0	0
T13	404	4	0	0
T14	493	93	0	0
T15	526	126	0	0
T16	406	6	0	0
T17	718	318	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	5193579	0	0
T1	486	86	0	0
T2	25810	24171	0	0
T3	7662	7262	0	0
T5	402	2	0	0
T12	527	127	0	0
T13	404	4	0	0
T14	493	93	0	0
T15	526	126	0	0
T16	406	6	0	0
T17	718	318	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	843	0	0
T3	7662	5	0	0
T4	707	0	0	0
T6	8924	0	0	0
T9	0	5	0	0
T10	0	10	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T33	0	5	0	0
T47	0	15	0	0
T50	402	0	0	0
T51	604	0	0	0
T72	0	9	0	0
T79	0	6	0	0
T141	0	21	0	0
T244	0	25	0	0
T260	0	14	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T25
1	Covered	T5,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T25
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T2,T3,T6

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T2	VC_COV_UNR
1	Covered	T2,T3,T6

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T2,T3,T6

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T2,T3,T25
1	1	Covered	T2,T3,T6

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T6
0	1	Covered	T2,T142,T96
1	0	Covered	T3,T52

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T6
0	1	Covered	T2,T6,T9
1	0	Covered	T79,T52

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T3,T6
1	-	Covered	T2,T3,T6

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T3,T6
DetectSt	168	Covered	T2,T3,T6
IdleSt	163	Covered	T5,T1,T2
StableSt	191	Covered	T2,T3,T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T3,T6
DebounceSt->IdleSt	163	Covered	T2,T3,T88
DetectSt->IdleSt	186	Covered	T2,T3,T142
DetectSt->StableSt	191	Covered	T2,T3,T6
IdleSt->DebounceSt	148	Covered	T2,T3,T6
StableSt->IdleSt	206	Covered	T2,T3,T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T3,T6
0	1	Covered	T2,T3,T6
0	0	Excluded	T5,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T6
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T3,T6
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T3,T52
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T3,T6
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T88,T91
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T3,T6
DetectSt	-	-	-	-	1	-	-	Covered	T2,T3,T142
DetectSt	-	-	-	-	0	1	-	Covered	T2,T3,T6
DetectSt	-	-	-	-	0	0	-	Covered	T2,T3,T6
StableSt	-	-	-	-	-	-	1	Covered	T2,T3,T6
StableSt	-	-	-	-	-	-	0	Covered	T2,T3,T6
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5804184	841	0	0
CntIncr_A	5804184	45032	0	0
CntNoWrap_A	5804184	5190465	0	0
DetectStDropOut_A	5804184	43	0	0
DetectedOut_A	5804184	16090	0	0
DetectedPulseOut_A	5804184	350	0	0
DisabledIdleSt_A	5804184	4813664	0	0
DisabledNoDetection_A	5804184	4815269	0	0
EnterDebounceSt_A	5804184	444	0	0
EnterDetectSt_A	5804184	399	0	0
EnterStableSt_A	5804184	350	0	0
PulseIsPulse_A	5804184	350	0	0
StayInStableSt	5804184	15684	0	0
gen_high_level_sva.HighLevelEvent_A	5804184	5193579	0	0
gen_not_sticky_sva.StableStDropOut_A	5804184	287	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	841	0	0
T2	25810	21	0	0
T3	7662	8	0	0
T4	707	0	0	0
T6	0	2	0	0
T9	0	2	0	0
T10	0	10	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T32	0	2	0	0
T33	0	4	0	0
T43	0	6	0	0
T47	0	2	0	0
T72	0	10	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	45032	0	0
T2	25810	911	0	0
T3	7662	219	0	0
T4	707	0	0	0
T6	0	163	0	0
T9	0	227	0	0
T10	0	325	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T32	0	64	0	0
T33	0	112	0	0
T43	0	306	0	0
T47	0	84	0	0
T72	0	465	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	5190465	0	0
T1	486	85	0	0
T2	25810	24141	0	0
T3	7662	7253	0	0
T5	402	1	0	0
T12	527	126	0	0
T13	404	3	0	0
T14	493	92	0	0
T15	526	125	0	0
T16	406	5	0	0
T17	718	317	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	43	0	0
T2	25810	9	0	0
T3	7662	0	0	0
T4	707	0	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T96	0	4	0	0
T99	0	1	0	0
T100	0	1	0	0
T142	0	3	0	0
T263	0	2	0	0
T264	0	3	0	0
T265	0	4	0	0
T266	0	5	0	0
T267	0	11	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	16090	0	0
T2	25810	90	0	0
T3	7662	81	0	0
T4	707	0	0	0
T6	0	8	0	0
T9	0	83	0	0
T10	0	193	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T32	0	12	0	0
T33	0	196	0	0
T43	0	46	0	0
T47	0	63	0	0
T72	0	436	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	350	0	0
T2	25810	1	0	0
T3	7662	1	0	0
T4	707	0	0	0
T6	0	1	0	0
T9	0	1	0	0
T10	0	5	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T32	0	1	0	0
T33	0	2	0	0
T43	0	3	0	0
T47	0	1	0	0
T72	0	5	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	4813664	0	0
T1	486	85	0	0
T2	25810	16352	0	0
T3	7662	6888	0	0
T5	402	1	0	0
T12	527	126	0	0
T13	404	3	0	0
T14	493	92	0	0
T15	526	125	0	0
T16	406	5	0	0
T17	718	317	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	4815269	0	0
T1	486	86	0	0
T2	25810	16353	0	0
T3	7662	6889	0	0
T5	402	2	0	0
T12	527	127	0	0
T13	404	4	0	0
T14	493	93	0	0
T15	526	126	0	0
T16	406	6	0	0
T17	718	318	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	444	0	0
T2	25810	11	0	0
T3	7662	5	0	0
T4	707	0	0	0
T6	0	1	0	0
T9	0	1	0	0
T10	0	5	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T32	0	1	0	0
T33	0	2	0	0
T43	0	3	0	0
T47	0	1	0	0
T72	0	5	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	399	0	0
T2	25810	10	0	0
T3	7662	3	0	0
T4	707	0	0	0
T6	0	1	0	0
T9	0	1	0	0
T10	0	5	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T32	0	1	0	0
T33	0	2	0	0
T43	0	3	0	0
T47	0	1	0	0
T72	0	5	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	350	0	0
T2	25810	1	0	0
T3	7662	1	0	0
T4	707	0	0	0
T6	0	1	0	0
T9	0	1	0	0
T10	0	5	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T32	0	1	0	0
T33	0	2	0	0
T43	0	3	0	0
T47	0	1	0	0
T72	0	5	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	350	0	0
T2	25810	1	0	0
T3	7662	1	0	0
T4	707	0	0	0
T6	0	1	0	0
T9	0	1	0	0
T10	0	5	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T32	0	1	0	0
T33	0	2	0	0
T43	0	3	0	0
T47	0	1	0	0
T72	0	5	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	15684	0	0
T2	25810	89	0	0
T3	7662	80	0	0
T4	707	0	0	0
T6	0	7	0	0
T9	0	82	0	0
T10	0	188	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T32	0	11	0	0
T33	0	193	0	0
T43	0	43	0	0
T47	0	61	0	0
T72	0	426	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	5193579	0	0
T1	486	86	0	0
T2	25810	24171	0	0
T3	7662	7262	0	0
T5	402	2	0	0
T12	527	127	0	0
T13	404	4	0	0
T14	493	93	0	0
T15	526	126	0	0
T16	406	6	0	0
T17	718	318	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	287	0	0
T2	25810	1	0	0
T3	7662	0	0	0
T4	707	0	0	0
T6	0	1	0	0
T9	0	1	0	0
T10	0	5	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T32	0	1	0	0
T33	0	1	0	0
T43	0	3	0	0
T88	0	11	0	0
T122	0	3	0	0
T268	0	6	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T3,T25,T7
1	Covered	T5,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T3,T25,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T3,T25,T7

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T3,T25,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T25,T7
1	0	Covered	T3,T7,T9
1	1	Covered	T3,T25,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T25,T7
0	1	Covered	T3,T25,T7
1	0	Covered	T3,T47,T90

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T9,T10
0	1	Covered	T3,T10,T33
1	0	Covered	T9,T261

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T9,T10
1	-	Covered	T3,T10,T33

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T25,T7
DetectSt	168	Covered	T3,T25,T7
IdleSt	163	Covered	T5,T1,T2
StableSt	191	Covered	T3,T9,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T25,T7
DebounceSt->IdleSt	163	Covered	T3,T73,T258
DetectSt->IdleSt	186	Covered	T3,T25,T7
DetectSt->StableSt	191	Covered	T3,T9,T10
IdleSt->DebounceSt	148	Covered	T3,T25,T7
StableSt->IdleSt	206	Covered	T3,T9,T10

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T25,T7
0	1	Covered	T3,T25,T7
0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T25,T7
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T3,T25,T7
IdleSt	0	-	-	-	-	-	-	Covered	T3,T25,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T3,T52
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T25,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T3,T73,T258
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T25,T7
DetectSt	-	-	-	-	1	-	-	Covered	T3,T25,T7
DetectSt	-	-	-	-	0	1	-	Covered	T3,T9,T10
DetectSt	-	-	-	-	0	0	-	Covered	T3,T25,T7
StableSt	-	-	-	-	-	-	1	Covered	T3,T9,T10
StableSt	-	-	-	-	-	-	0	Covered	T3,T9,T10
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5804184	3029	0	0
CntIncr_A	5804184	99491	0	0
CntNoWrap_A	5804184	5188277	0	0
DetectStDropOut_A	5804184	286	0	0
DetectedOut_A	5804184	86662	0	0
DetectedPulseOut_A	5804184	1090	0	0
DisabledIdleSt_A	5804184	4712638	0	0
DisabledNoDetection_A	5804184	4714668	0	0
EnterDebounceSt_A	5804184	1551	0	0
EnterDetectSt_A	5804184	1478	0	0
EnterStableSt_A	5804184	1090	0	0
PulseIsPulse_A	5804184	1090	0	0
StayInStableSt	5804184	85425	0	0
gen_high_event_sva.HighLevelEvent_A	5804184	5193579	0	0
gen_high_level_sva.HighLevelEvent_A	5804184	5193579	0	0
gen_not_sticky_sva.StableStDropOut_A	5804184	926	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	3029	0	0
T3	7662	16	0	0
T4	707	0	0	0
T6	8924	0	0	0
T7	0	6	0	0
T9	0	4	0	0
T10	0	6	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	44	0	0
T33	0	32	0	0
T46	0	26	0	0
T47	0	16	0	0
T50	402	0	0	0
T51	604	0	0	0
T72	0	20	0	0
T73	0	22	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	99491	0	0
T3	7662	611	0	0
T4	707	0	0	0
T6	8924	0	0	0
T7	0	181	0	0
T9	0	436	0	0
T10	0	129	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	1097	0	0
T33	0	800	0	0
T46	0	660	0	0
T47	0	983	0	0
T50	402	0	0	0
T51	604	0	0	0
T72	0	660	0	0
T73	0	1056	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	5188277	0	0
T1	486	85	0	0
T2	25810	24162	0	0
T3	7662	7245	0	0
T5	402	1	0	0
T12	527	126	0	0
T13	404	3	0	0
T14	493	92	0	0
T15	526	125	0	0
T16	406	5	0	0
T17	718	317	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	286	0	0
T3	7662	1	0	0
T4	707	0	0	0
T6	8924	0	0	0
T7	0	3	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	22	0	0
T46	0	13	0	0
T50	402	0	0	0
T51	604	0	0	0
T79	0	17	0	0
T89	0	16	0	0
T90	0	26	0	0
T92	0	4	0	0
T94	0	8	0	0
T244	0	6	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	86662	0	0
T3	7662	450	0	0
T4	707	0	0	0
T6	8924	0	0	0
T9	0	147	0	0
T10	0	568	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T33	0	2602	0	0
T50	402	0	0	0
T51	604	0	0	0
T72	0	1417	0	0
T119	0	338	0	0
T141	0	1207	0	0
T259	0	33	0	0
T260	0	1501	0	0
T262	0	1241	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	1090	0	0
T3	7662	5	0	0
T4	707	0	0	0
T6	8924	0	0	0
T9	0	2	0	0
T10	0	3	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T33	0	16	0	0
T50	402	0	0	0
T51	604	0	0	0
T72	0	10	0	0
T119	0	12	0	0
T141	0	29	0	0
T259	0	4	0	0
T260	0	16	0	0
T262	0	9	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	4712638	0	0
T1	486	85	0	0
T2	25810	24162	0	0
T3	7662	6113	0	0
T5	402	1	0	0
T12	527	126	0	0
T13	404	3	0	0
T14	493	92	0	0
T15	526	125	0	0
T16	406	5	0	0
T17	718	317	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	4714668	0	0
T1	486	86	0	0
T2	25810	24171	0	0
T3	7662	6114	0	0
T5	402	2	0	0
T12	527	127	0	0
T13	404	4	0	0
T14	493	93	0	0
T15	526	126	0	0
T16	406	6	0	0
T17	718	318	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	1551	0	0
T3	7662	9	0	0
T4	707	0	0	0
T6	8924	0	0	0
T7	0	3	0	0
T9	0	2	0	0
T10	0	3	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	22	0	0
T33	0	16	0	0
T46	0	13	0	0
T47	0	8	0	0
T50	402	0	0	0
T51	604	0	0	0
T72	0	10	0	0
T73	0	22	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	1478	0	0
T3	7662	7	0	0
T4	707	0	0	0
T6	8924	0	0	0
T7	0	3	0	0
T9	0	2	0	0
T10	0	3	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	22	0	0
T33	0	16	0	0
T46	0	13	0	0
T47	0	8	0	0
T50	402	0	0	0
T51	604	0	0	0
T72	0	10	0	0
T119	0	12	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	1090	0	0
T3	7662	5	0	0
T4	707	0	0	0
T6	8924	0	0	0
T9	0	2	0	0
T10	0	3	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T33	0	16	0	0
T50	402	0	0	0
T51	604	0	0	0
T72	0	10	0	0
T119	0	12	0	0
T141	0	29	0	0
T259	0	4	0	0
T260	0	16	0	0
T262	0	9	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	1090	0	0
T3	7662	5	0	0
T4	707	0	0	0
T6	8924	0	0	0
T9	0	2	0	0
T10	0	3	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T33	0	16	0	0
T50	402	0	0	0
T51	604	0	0	0
T72	0	10	0	0
T119	0	12	0	0
T141	0	29	0	0
T259	0	4	0	0
T260	0	16	0	0
T262	0	9	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	85425	0	0
T3	7662	445	0	0
T4	707	0	0	0
T6	8924	0	0	0
T9	0	145	0	0
T10	0	565	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T33	0	2582	0	0
T50	402	0	0	0
T51	604	0	0	0
T72	0	1404	0	0
T119	0	325	0	0
T141	0	1175	0	0
T259	0	29	0	0
T260	0	1482	0	0
T262	0	1228	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	5193579	0	0
T1	486	86	0	0
T2	25810	24171	0	0
T3	7662	7262	0	0
T5	402	2	0	0
T12	527	127	0	0
T13	404	4	0	0
T14	493	93	0	0
T15	526	126	0	0
T16	406	6	0	0
T17	718	318	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	5193579	0	0
T1	486	86	0	0
T2	25810	24171	0	0
T3	7662	7262	0	0
T5	402	2	0	0
T12	527	127	0	0
T13	404	4	0	0
T14	493	93	0	0
T15	526	126	0	0
T16	406	6	0	0
T17	718	318	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	926	0	0
T3	7662	5	0	0
T4	707	0	0	0
T6	8924	0	0	0
T10	0	3	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T33	0	12	0	0
T50	402	0	0	0
T51	604	0	0	0
T72	0	7	0	0
T112	0	24	0	0
T119	0	11	0	0
T141	0	26	0	0
T259	0	4	0	0
T260	0	13	0	0
T262	0	5	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T25
1	Covered	T5,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T25
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T2,T3,T6

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T2	VC_COV_UNR
1	Covered	T2,T3,T6

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T2,T3,T6

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T2,T3,T25
1	1	Covered	T2,T3,T6

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T6
0	1	Covered	T6,T43,T91
1	0	Covered	T3,T52

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T10
0	1	Covered	T2,T10,T11
1	0	Covered	T52

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T3,T10
1	-	Covered	T2,T3,T10

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T3,T6
DetectSt	168	Covered	T2,T3,T6
IdleSt	163	Covered	T5,T1,T2
StableSt	191	Covered	T2,T3,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T3,T6
DebounceSt->IdleSt	163	Covered	T2,T3,T32
DetectSt->IdleSt	186	Covered	T3,T6,T43
DetectSt->StableSt	191	Covered	T2,T3,T10
IdleSt->DebounceSt	148	Covered	T2,T3,T6
StableSt->IdleSt	206	Covered	T2,T3,T10

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T3,T6
0	1	Covered	T2,T3,T6
0	0	Excluded	T5,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T6
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T3,T6
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T3,T52
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T3,T6
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T32,T268
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T3,T6
DetectSt	-	-	-	-	1	-	-	Covered	T3,T6,T43
DetectSt	-	-	-	-	0	1	-	Covered	T2,T3,T10
DetectSt	-	-	-	-	0	0	-	Covered	T2,T3,T6
StableSt	-	-	-	-	-	-	1	Covered	T2,T3,T10
StableSt	-	-	-	-	-	-	0	Covered	T2,T3,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5804184	913	0	0
CntIncr_A	5804184	46013	0	0
CntNoWrap_A	5804184	5190393	0	0
DetectStDropOut_A	5804184	60	0	0
DetectedOut_A	5804184	19295	0	0
DetectedPulseOut_A	5804184	365	0	0
DisabledIdleSt_A	5804184	4803580	0	0
DisabledNoDetection_A	5804184	4805167	0	0
EnterDebounceSt_A	5804184	484	0	0
EnterDetectSt_A	5804184	433	0	0
EnterStableSt_A	5804184	365	0	0
PulseIsPulse_A	5804184	365	0	0
StayInStableSt	5804184	18873	0	0
gen_high_level_sva.HighLevelEvent_A	5804184	5193579	0	0
gen_not_sticky_sva.StableStDropOut_A	5804184	306	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	913	0	0
T2	25810	12	0	0
T3	7662	8	0	0
T4	707	0	0	0
T6	0	8	0	0
T10	0	6	0	0
T11	0	2	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T32	0	9	0	0
T33	0	4	0	0
T43	0	14	0	0
T72	0	6	0	0
T122	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	46013	0	0
T2	25810	262	0	0
T3	7662	297	0	0
T4	707	0	0	0
T6	0	684	0	0
T10	0	144	0	0
T11	0	160	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T32	0	202	0	0
T33	0	120	0	0
T43	0	820	0	0
T72	0	381	0	0
T122	0	267	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	5190393	0	0
T1	486	85	0	0
T2	25810	24150	0	0
T3	7662	7253	0	0
T5	402	1	0	0
T12	527	126	0	0
T13	404	3	0	0
T14	493	92	0	0
T15	526	125	0	0
T16	406	5	0	0
T17	718	317	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	60	0	0
T6	8924	4	0	0
T7	8003	0	0	0
T8	2340	0	0	0
T23	508	0	0	0
T30	1065	0	0	0
T43	0	7	0	0
T51	604	0	0	0
T53	518	0	0	0
T54	1436	0	0	0
T91	0	9	0	0
T120	438	0	0	0
T121	426	0	0	0
T149	0	4	0	0
T186	0	11	0	0
T264	0	8	0	0
T266	0	1	0	0
T269	0	2	0	0
T270	0	3	0	0
T271	0	6	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	19295	0	0
T2	25810	199	0	0
T3	7662	81	0	0
T4	707	0	0	0
T10	0	380	0	0
T11	0	7	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T32	0	119	0	0
T33	0	187	0	0
T72	0	162	0	0
T122	0	221	0	0
T127	0	56	0	0
T268	0	473	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	365	0	0
T2	25810	5	0	0
T3	7662	1	0	0
T4	707	0	0	0
T10	0	3	0	0
T11	0	1	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T32	0	4	0	0
T33	0	2	0	0
T72	0	3	0	0
T122	0	3	0	0
T127	0	3	0	0
T268	0	6	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	4803580	0	0
T1	486	85	0	0
T2	25810	16352	0	0
T3	7662	6807	0	0
T5	402	1	0	0
T12	527	126	0	0
T13	404	3	0	0
T14	493	92	0	0
T15	526	125	0	0
T16	406	5	0	0
T17	718	317	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	4805167	0	0
T1	486	86	0	0
T2	25810	16353	0	0
T3	7662	6808	0	0
T5	402	2	0	0
T12	527	127	0	0
T13	404	4	0	0
T14	493	93	0	0
T15	526	126	0	0
T16	406	6	0	0
T17	718	318	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	484	0	0
T2	25810	7	0	0
T3	7662	5	0	0
T4	707	0	0	0
T6	0	4	0	0
T10	0	3	0	0
T11	0	1	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T32	0	5	0	0
T33	0	2	0	0
T43	0	7	0	0
T72	0	3	0	0
T122	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	433	0	0
T2	25810	5	0	0
T3	7662	3	0	0
T4	707	0	0	0
T6	0	4	0	0
T10	0	3	0	0
T11	0	1	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T32	0	4	0	0
T33	0	2	0	0
T43	0	7	0	0
T72	0	3	0	0
T122	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	365	0	0
T2	25810	5	0	0
T3	7662	1	0	0
T4	707	0	0	0
T10	0	3	0	0
T11	0	1	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T32	0	4	0	0
T33	0	2	0	0
T72	0	3	0	0
T122	0	3	0	0
T127	0	3	0	0
T268	0	6	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	365	0	0
T2	25810	5	0	0
T3	7662	1	0	0
T4	707	0	0	0
T10	0	3	0	0
T11	0	1	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T32	0	4	0	0
T33	0	2	0	0
T72	0	3	0	0
T122	0	3	0	0
T127	0	3	0	0
T268	0	6	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	18873	0	0
T2	25810	194	0	0
T3	7662	80	0	0
T4	707	0	0	0
T10	0	377	0	0
T11	0	6	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T32	0	115	0	0
T33	0	185	0	0
T72	0	157	0	0
T122	0	218	0	0
T127	0	53	0	0
T268	0	467	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	5193579	0	0
T1	486	86	0	0
T2	25810	24171	0	0
T3	7662	7262	0	0
T5	402	2	0	0
T12	527	127	0	0
T13	404	4	0	0
T14	493	93	0	0
T15	526	126	0	0
T16	406	6	0	0
T17	718	318	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	306	0	0
T2	25810	5	0	0
T3	7662	0	0	0
T4	707	0	0	0
T10	0	3	0	0
T11	0	1	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T32	0	4	0	0
T33	0	2	0	0
T72	0	1	0	0
T88	0	6	0	0
T122	0	3	0	0
T127	0	3	0	0
T268	0	6	0	0