Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T3,T25,T7
1	Covered	T5,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T3,T25,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T3,T25,T7

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T3,T25,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T25,T7
1	0	Covered	T3,T7,T9
1	1	Covered	T3,T25,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T25,T7
0	1	Covered	T3,T25,T7
1	0	Covered	T3,T7,T10

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T9,T33
0	1	Covered	T3,T9,T33
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T9,T33
1	-	Covered	T3,T9,T33

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T25,T7
DetectSt	168	Covered	T3,T25,T7
IdleSt	163	Covered	T5,T1,T2
StableSt	191	Covered	T3,T9,T33

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T25,T7
DebounceSt->IdleSt	163	Covered	T3,T73,T258
DetectSt->IdleSt	186	Covered	T3,T25,T7
DetectSt->StableSt	191	Covered	T3,T9,T33
IdleSt->DebounceSt	148	Covered	T3,T25,T7
StableSt->IdleSt	206	Covered	T3,T9,T33

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T25,T7
0	1	Covered	T3,T25,T7
0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T25,T7
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T3,T25,T7
IdleSt	0	-	-	-	-	-	-	Covered	T3,T25,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T3,T52
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T25,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T3,T73,T258
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T25,T7
DetectSt	-	-	-	-	1	-	-	Covered	T3,T25,T7
DetectSt	-	-	-	-	0	1	-	Covered	T3,T9,T33
DetectSt	-	-	-	-	0	0	-	Covered	T3,T25,T7
StableSt	-	-	-	-	-	-	1	Covered	T3,T9,T33
StableSt	-	-	-	-	-	-	0	Covered	T3,T9,T33
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5804184	3187	0	0
CntIncr_A	5804184	109737	0	0
CntNoWrap_A	5804184	5188119	0	0
DetectStDropOut_A	5804184	378	0	0
DetectedOut_A	5804184	83833	0	0
DetectedPulseOut_A	5804184	941	0	0
DisabledIdleSt_A	5804184	4718526	0	0
DisabledNoDetection_A	5804184	4720586	0	0
EnterDebounceSt_A	5804184	1625	0	0
EnterDetectSt_A	5804184	1563	0	0
EnterStableSt_A	5804184	941	0	0
PulseIsPulse_A	5804184	941	0	0
StayInStableSt	5804184	82774	0	0
gen_high_event_sva.HighLevelEvent_A	5804184	5193579	0	0
gen_high_level_sva.HighLevelEvent_A	5804184	5193579	0	0
gen_not_sticky_sva.StableStDropOut_A	5804184	823	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	3187	0	0
T3	7662	16	0	0
T4	707	0	0	0
T6	8924	0	0	0
T7	0	42	0	0
T9	0	30	0	0
T10	0	24	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	50	0	0
T33	0	52	0	0
T46	0	18	0	0
T47	0	36	0	0
T50	402	0	0	0
T51	604	0	0	0
T72	0	20	0	0
T73	0	18	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	109737	0	0
T3	7662	444	0	0
T4	707	0	0	0
T6	8924	0	0	0
T7	0	1280	0	0
T9	0	3780	0	0
T10	0	639	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	1245	0	0
T33	0	1326	0	0
T46	0	458	0	0
T47	0	1188	0	0
T50	402	0	0	0
T51	604	0	0	0
T72	0	1317	0	0
T73	0	864	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	5188119	0	0
T1	486	85	0	0
T2	25810	24162	0	0
T3	7662	7245	0	0
T5	402	1	0	0
T12	527	126	0	0
T13	404	3	0	0
T14	493	92	0	0
T15	526	125	0	0
T16	406	5	0	0
T17	718	317	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	378	0	0
T3	7662	1	0	0
T4	707	0	0	0
T6	8924	0	0	0
T7	0	20	0	0
T10	0	6	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	25	0	0
T46	0	9	0	0
T50	402	0	0	0
T51	604	0	0	0
T79	0	10	0	0
T89	0	2	0	0
T92	0	6	0	0
T94	0	12	0	0
T258	0	9	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	83833	0	0
T3	7662	399	0	0
T4	707	0	0	0
T6	8924	0	0	0
T9	0	5317	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T33	0	1590	0	0
T47	0	2269	0	0
T50	402	0	0	0
T51	604	0	0	0
T90	0	1930	0	0
T112	0	459	0	0
T119	0	2321	0	0
T141	0	1332	0	0
T244	0	14	0	0
T260	0	1495	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	941	0	0
T3	7662	5	0	0
T4	707	0	0	0
T6	8924	0	0	0
T9	0	15	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T33	0	26	0	0
T47	0	18	0	0
T50	402	0	0	0
T51	604	0	0	0
T90	0	9	0	0
T112	0	8	0	0
T119	0	25	0	0
T141	0	12	0	0
T244	0	2	0	0
T260	0	28	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	4718526	0	0
T1	486	85	0	0
T2	25810	24162	0	0
T3	7662	6335	0	0
T5	402	1	0	0
T12	527	126	0	0
T13	404	3	0	0
T14	493	92	0	0
T15	526	125	0	0
T16	406	5	0	0
T17	718	317	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	4720586	0	0
T1	486	86	0	0
T2	25810	24171	0	0
T3	7662	6336	0	0
T5	402	2	0	0
T12	527	127	0	0
T13	404	4	0	0
T14	493	93	0	0
T15	526	126	0	0
T16	406	6	0	0
T17	718	318	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	1625	0	0
T3	7662	9	0	0
T4	707	0	0	0
T6	8924	0	0	0
T7	0	21	0	0
T9	0	15	0	0
T10	0	12	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	25	0	0
T33	0	26	0	0
T46	0	9	0	0
T47	0	18	0	0
T50	402	0	0	0
T51	604	0	0	0
T72	0	10	0	0
T73	0	18	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	1563	0	0
T3	7662	7	0	0
T4	707	0	0	0
T6	8924	0	0	0
T7	0	21	0	0
T9	0	15	0	0
T10	0	12	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	25	0	0
T33	0	26	0	0
T46	0	9	0	0
T47	0	18	0	0
T50	402	0	0	0
T51	604	0	0	0
T72	0	10	0	0
T119	0	25	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	941	0	0
T3	7662	5	0	0
T4	707	0	0	0
T6	8924	0	0	0
T9	0	15	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T33	0	26	0	0
T47	0	18	0	0
T50	402	0	0	0
T51	604	0	0	0
T90	0	9	0	0
T112	0	8	0	0
T119	0	25	0	0
T141	0	12	0	0
T244	0	2	0	0
T260	0	28	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	941	0	0
T3	7662	5	0	0
T4	707	0	0	0
T6	8924	0	0	0
T9	0	15	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T33	0	26	0	0
T47	0	18	0	0
T50	402	0	0	0
T51	604	0	0	0
T90	0	9	0	0
T112	0	8	0	0
T119	0	25	0	0
T141	0	12	0	0
T244	0	2	0	0
T260	0	28	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	82774	0	0
T3	7662	394	0	0
T4	707	0	0	0
T6	8924	0	0	0
T9	0	5297	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T33	0	1560	0	0
T47	0	2251	0	0
T50	402	0	0	0
T51	604	0	0	0
T90	0	1916	0	0
T112	0	451	0	0
T119	0	2293	0	0
T141	0	1317	0	0
T244	0	12	0	0
T260	0	1464	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	5193579	0	0
T1	486	86	0	0
T2	25810	24171	0	0
T3	7662	7262	0	0
T5	402	2	0	0
T12	527	127	0	0
T13	404	4	0	0
T14	493	93	0	0
T15	526	126	0	0
T16	406	6	0	0
T17	718	318	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	5193579	0	0
T1	486	86	0	0
T2	25810	24171	0	0
T3	7662	7262	0	0
T5	402	2	0	0
T12	527	127	0	0
T13	404	4	0	0
T14	493	93	0	0
T15	526	126	0	0
T16	406	6	0	0
T17	718	318	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	823	0	0
T3	7662	5	0	0
T4	707	0	0	0
T6	8924	0	0	0
T9	0	10	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T33	0	22	0	0
T47	0	18	0	0
T50	402	0	0	0
T51	604	0	0	0
T90	0	4	0	0
T112	0	8	0	0
T119	0	22	0	0
T141	0	9	0	0
T244	0	2	0	0
T260	0	25	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T25
1	Covered	T5,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T25
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T2,T3,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T2	VC_COV_UNR
1	Covered	T2,T3,T9

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T2,T3,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T9
1	0	Covered	T2,T3,T25
1	1	Covered	T2,T3,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T9
0	1	Covered	T272,T96,T273
1	0	Covered	T3,T52

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T9
0	1	Covered	T2,T9,T11
1	0	Covered	T52

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T3,T9
1	-	Covered	T2,T3,T9

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T3,T9
DetectSt	168	Covered	T2,T3,T9
IdleSt	163	Covered	T5,T1,T2
StableSt	191	Covered	T2,T3,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T3,T9
DebounceSt->IdleSt	163	Covered	T3,T32,T43
DetectSt->IdleSt	186	Covered	T3,T272,T96
DetectSt->StableSt	191	Covered	T2,T3,T9
IdleSt->DebounceSt	148	Covered	T2,T3,T9
StableSt->IdleSt	206	Covered	T2,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T3,T9
0	1	Covered	T2,T3,T9
0	0	Excluded	T5,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T9
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T3,T9
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T3,T52
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T3,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T32,T43,T122
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T3,T9
DetectSt	-	-	-	-	1	-	-	Covered	T3,T272,T96
DetectSt	-	-	-	-	0	1	-	Covered	T2,T3,T9
DetectSt	-	-	-	-	0	0	-	Covered	T2,T3,T9
StableSt	-	-	-	-	-	-	1	Covered	T2,T3,T9
StableSt	-	-	-	-	-	-	0	Covered	T2,T3,T9
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5804184	863	0	0
CntIncr_A	5804184	46920	0	0
CntNoWrap_A	5804184	5190443	0	0
DetectStDropOut_A	5804184	50	0	0
DetectedOut_A	5804184	15690	0	0
DetectedPulseOut_A	5804184	354	0	0
DisabledIdleSt_A	5804184	4805047	0	0
DisabledNoDetection_A	5804184	4806642	0	0
EnterDebounceSt_A	5804184	455	0	0
EnterDetectSt_A	5804184	411	0	0
EnterStableSt_A	5804184	354	0	0
PulseIsPulse_A	5804184	354	0	0
StayInStableSt	5804184	15282	0	0
gen_high_level_sva.HighLevelEvent_A	5804184	5193579	0	0
gen_not_sticky_sva.StableStDropOut_A	5804184	297	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	863	0	0
T2	25810	12	0	0
T3	7662	8	0	0
T4	707	0	0	0
T9	0	10	0	0
T11	0	2	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T32	0	20	0	0
T33	0	8	0	0
T43	0	7	0	0
T122	0	28	0	0
T127	0	14	0	0
T268	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	46920	0	0
T2	25810	449	0	0
T3	7662	245	0	0
T4	707	0	0	0
T9	0	1275	0	0
T11	0	109	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T32	0	532	0	0
T33	0	400	0	0
T43	0	390	0	0
T122	0	1229	0	0
T127	0	1128	0	0
T268	0	336	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	5190443	0	0
T1	486	85	0	0
T2	25810	24150	0	0
T3	7662	7253	0	0
T5	402	1	0	0
T12	527	126	0	0
T13	404	3	0	0
T14	493	92	0	0
T15	526	125	0	0
T16	406	5	0	0
T17	718	317	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	50	0	0
T95	6048	0	0	0
T96	0	7	0	0
T149	0	5	0	0
T157	0	8	0	0
T186	0	1	0	0
T196	1093	0	0	0
T197	2707	0	0	0
T258	4976	0	0	0
T262	19535	0	0	0
T263	0	1	0	0
T272	7106	1	0	0
T273	0	1	0	0
T274	0	4	0	0
T275	0	8	0	0
T276	0	2	0	0
T277	493	0	0	0
T278	3027	0	0	0
T279	523	0	0	0
T280	21062	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	15690	0	0
T2	25810	189	0	0
T3	7662	83	0	0
T4	707	0	0	0
T9	0	270	0	0
T11	0	59	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T32	0	189	0	0
T33	0	213	0	0
T43	0	28	0	0
T122	0	963	0	0
T127	0	44	0	0
T268	0	278	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	354	0	0
T2	25810	6	0	0
T3	7662	1	0	0
T4	707	0	0	0
T9	0	5	0	0
T11	0	1	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T32	0	9	0	0
T33	0	4	0	0
T43	0	3	0	0
T122	0	13	0	0
T127	0	6	0	0
T268	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	4805047	0	0
T1	486	85	0	0
T2	25810	16352	0	0
T3	7662	6859	0	0
T5	402	1	0	0
T12	527	126	0	0
T13	404	3	0	0
T14	493	92	0	0
T15	526	125	0	0
T16	406	5	0	0
T17	718	317	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	4806642	0	0
T1	486	86	0	0
T2	25810	16353	0	0
T3	7662	6860	0	0
T5	402	2	0	0
T12	527	127	0	0
T13	404	4	0	0
T14	493	93	0	0
T15	526	126	0	0
T16	406	6	0	0
T17	718	318	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	455	0	0
T2	25810	6	0	0
T3	7662	5	0	0
T4	707	0	0	0
T9	0	5	0	0
T11	0	1	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T32	0	11	0	0
T33	0	4	0	0
T43	0	4	0	0
T122	0	15	0	0
T127	0	8	0	0
T268	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	411	0	0
T2	25810	6	0	0
T3	7662	3	0	0
T4	707	0	0	0
T9	0	5	0	0
T11	0	1	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T32	0	9	0	0
T33	0	4	0	0
T43	0	3	0	0
T122	0	13	0	0
T127	0	6	0	0
T268	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	354	0	0
T2	25810	6	0	0
T3	7662	1	0	0
T4	707	0	0	0
T9	0	5	0	0
T11	0	1	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T32	0	9	0	0
T33	0	4	0	0
T43	0	3	0	0
T122	0	13	0	0
T127	0	6	0	0
T268	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	354	0	0
T2	25810	6	0	0
T3	7662	1	0	0
T4	707	0	0	0
T9	0	5	0	0
T11	0	1	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T32	0	9	0	0
T33	0	4	0	0
T43	0	3	0	0
T122	0	13	0	0
T127	0	6	0	0
T268	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	15282	0	0
T2	25810	183	0	0
T3	7662	82	0	0
T4	707	0	0	0
T9	0	261	0	0
T11	0	58	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T32	0	180	0	0
T33	0	209	0	0
T43	0	25	0	0
T122	0	950	0	0
T127	0	38	0	0
T268	0	275	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	5193579	0	0
T1	486	86	0	0
T2	25810	24171	0	0
T3	7662	7262	0	0
T5	402	2	0	0
T12	527	127	0	0
T13	404	4	0	0
T14	493	93	0	0
T15	526	126	0	0
T16	406	6	0	0
T17	718	318	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5804184	297	0	0
T2	25810	6	0	0
T3	7662	0	0	0
T4	707	0	0	0
T9	0	1	0	0
T11	0	1	0	0
T12	527	0	0	0
T13	404	0	0	0
T14	493	0	0	0
T15	526	0	0	0
T16	406	0	0	0
T17	718	0	0	0
T25	5118	0	0	0
T32	0	9	0	0
T33	0	4	0	0
T43	0	3	0	0
T88	0	5	0	0
T122	0	13	0	0
T127	0	6	0	0
T268	0	3	0	0