Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1285383986	10882	0	0
auto_block_debounce_ctl_rd_A	1285383986	1320	0	0
auto_block_out_ctl_rd_A	1285383986	1571	0	0
com_det_ctl_0_rd_A	1285383986	3295	0	0
com_det_ctl_1_rd_A	1285383986	3155	0	0
com_det_ctl_2_rd_A	1285383986	3103	0	0
com_det_ctl_3_rd_A	1285383986	3378	0	0
com_out_ctl_0_rd_A	1285383986	3516	0	0
com_out_ctl_1_rd_A	1285383986	3517	0	0
com_out_ctl_2_rd_A	1285383986	3284	0	0
com_out_ctl_3_rd_A	1285383986	3616	0	0
com_pre_det_ctl_0_rd_A	1285383986	1094	0	0
com_pre_det_ctl_1_rd_A	1285383986	983	0	0
com_pre_det_ctl_2_rd_A	1285383986	909	0	0
com_pre_det_ctl_3_rd_A	1285383986	920	0	0
com_pre_sel_ctl_0_rd_A	1285383986	3565	0	0
com_pre_sel_ctl_1_rd_A	1285383986	3724	0	0
com_pre_sel_ctl_2_rd_A	1285383986	3583	0	0
com_pre_sel_ctl_3_rd_A	1285383986	3532	0	0
com_sel_ctl_0_rd_A	1285383986	3702	0	0
com_sel_ctl_1_rd_A	1285383986	3816	0	0
com_sel_ctl_2_rd_A	1285383986	3464	0	0
com_sel_ctl_3_rd_A	1285383986	3572	0	0
ec_rst_ctl_rd_A	1285383986	1953	0	0
intr_enable_rd_A	1285383986	1456	0	0
key_intr_ctl_rd_A	1285383986	2220	0	0
key_intr_debounce_ctl_rd_A	1285383986	895	0	0
key_invert_ctl_rd_A	1285383986	3509	0	0
pin_allowed_ctl_rd_A	1285383986	4376	0	0
pin_out_ctl_rd_A	1285383986	3579	0	0
pin_out_value_rd_A	1285383986	3719	0	0
regwen_rd_A	1285383986	1094	0	0
ulp_ac_debounce_ctl_rd_A	1285383986	958	0	0
ulp_ctl_rd_A	1285383986	1030	0	0
ulp_lid_debounce_ctl_rd_A	1285383986	1035	0	0
ulp_pwrb_debounce_ctl_rd_A	1285383986	1241	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1285383986	10882	0	0
T11	187507	26	0	0
T31	226917	0	0	0
T32	279313	0	0	0
T36	0	15	0	0
T40	0	5	0	0
T55	51207	0	0	0
T61	0	7	0	0
T63	0	2	0	0
T68	31935	0	0	0
T71	53383	0	0	0
T83	0	13	0	0
T151	0	7	0	0
T171	0	12	0	0
T187	398045	0	0	0
T188	57052	0	0	0
T189	51127	0	0	0
T190	51137	0	0	0
T287	0	22	0	0
T288	0	7	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1285383986	1320	0	0
T4	69113	0	0	0
T6	107086	0	0	0
T7	276100	0	0	0
T17	345106	8	0	0
T23	30534	0	0	0
T25	115154	0	0	0
T30	43806	0	0	0
T41	0	3	0	0
T42	0	6	0	0
T50	201206	0	0	0
T51	72576	0	0	0
T60	0	4	0	0
T61	0	27	0	0
T104	0	15	0	0
T120	52677	0	0	0
T127	0	21	0	0
T149	0	14	0	0
T163	0	15	0	0
T288	0	16	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1285383986	1571	0	0
T4	69113	0	0	0
T6	107086	0	0	0
T7	276100	0	0	0
T17	345106	12	0	0
T23	30534	0	0	0
T25	115154	0	0	0
T30	43806	0	0	0
T41	0	1	0	0
T42	0	2	0	0
T50	201206	0	0	0
T51	72576	0	0	0
T60	0	9	0	0
T61	0	14	0	0
T104	0	21	0	0
T120	52677	0	0	0
T127	0	11	0	0
T149	0	15	0	0
T163	0	29	0	0
T288	0	35	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1285383986	3295	0	0
T10	853198	66	0	0
T11	187507	0	0	0
T31	226917	0	0	0
T32	279313	0	0	0
T43	0	96	0	0
T47	0	42	0	0
T55	51207	0	0	0
T61	0	6	0	0
T68	31935	0	0	0
T71	53383	0	0	0
T79	0	21	0	0
T88	0	85	0	0
T90	0	69	0	0
T119	0	33	0	0
T127	0	63	0	0
T142	0	53	0	0
T187	398045	0	0	0
T188	57052	0	0	0
T304	35649	0	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1285383986	3155	0	0
T10	853198	70	0	0
T11	187507	0	0	0
T31	226917	0	0	0
T32	279313	0	0	0
T43	0	59	0	0
T47	0	37	0	0
T55	51207	0	0	0
T61	0	21	0	0
T68	31935	0	0	0
T71	53383	0	0	0
T79	0	32	0	0
T88	0	78	0	0
T90	0	89	0	0
T119	0	38	0	0
T127	0	48	0	0
T142	0	52	0	0
T187	398045	0	0	0
T188	57052	0	0	0
T304	35649	0	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1285383986	3103	0	0
T10	853198	62	0	0
T11	187507	0	0	0
T31	226917	0	0	0
T32	279313	0	0	0
T43	0	69	0	0
T47	0	37	0	0
T55	51207	0	0	0
T61	0	14	0	0
T68	31935	0	0	0
T71	53383	0	0	0
T79	0	32	0	0
T88	0	83	0	0
T90	0	41	0	0
T119	0	35	0	0
T127	0	53	0	0
T142	0	24	0	0
T187	398045	0	0	0
T188	57052	0	0	0
T304	35649	0	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1285383986	3378	0	0
T10	853198	77	0	0
T11	187507	0	0	0
T31	226917	0	0	0
T32	279313	0	0	0
T43	0	53	0	0
T47	0	61	0	0
T55	51207	0	0	0
T61	0	21	0	0
T68	31935	0	0	0
T71	53383	0	0	0
T79	0	15	0	0
T88	0	83	0	0
T90	0	56	0	0
T119	0	34	0	0
T127	0	66	0	0
T142	0	44	0	0
T187	398045	0	0	0
T188	57052	0	0	0
T304	35649	0	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1285383986	3516	0	0
T10	853198	82	0	0
T11	187507	0	0	0
T31	226917	0	0	0
T32	279313	0	0	0
T43	0	59	0	0
T47	0	54	0	0
T55	51207	0	0	0
T61	0	10	0	0
T68	31935	0	0	0
T71	53383	0	0	0
T79	0	27	0	0
T88	0	46	0	0
T90	0	48	0	0
T119	0	39	0	0
T127	0	88	0	0
T142	0	42	0	0
T187	398045	0	0	0
T188	57052	0	0	0
T304	35649	0	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1285383986	3517	0	0
T10	853198	58	0	0
T11	187507	0	0	0
T31	226917	0	0	0
T32	279313	0	0	0
T43	0	69	0	0
T47	0	48	0	0
T55	51207	0	0	0
T61	0	11	0	0
T68	31935	0	0	0
T71	53383	0	0	0
T79	0	19	0	0
T88	0	86	0	0
T90	0	47	0	0
T119	0	24	0	0
T127	0	97	0	0
T142	0	23	0	0
T187	398045	0	0	0
T188	57052	0	0	0
T304	35649	0	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1285383986	3284	0	0
T10	853198	80	0	0
T11	187507	0	0	0
T31	226917	0	0	0
T32	279313	0	0	0
T43	0	94	0	0
T47	0	41	0	0
T55	51207	0	0	0
T61	0	15	0	0
T68	31935	0	0	0
T71	53383	0	0	0
T79	0	33	0	0
T88	0	66	0	0
T90	0	52	0	0
T119	0	36	0	0
T127	0	73	0	0
T142	0	23	0	0
T187	398045	0	0	0
T188	57052	0	0	0
T304	35649	0	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1285383986	3616	0	0
T10	853198	62	0	0
T11	187507	0	0	0
T31	226917	0	0	0
T32	279313	0	0	0
T43	0	61	0	0
T47	0	48	0	0
T55	51207	0	0	0
T61	0	25	0	0
T68	31935	0	0	0
T71	53383	0	0	0
T79	0	36	0	0
T88	0	105	0	0
T90	0	75	0	0
T119	0	36	0	0
T127	0	61	0	0
T142	0	26	0	0
T187	398045	0	0	0
T188	57052	0	0	0
T304	35649	0	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1285383986	1094	0	0
T27	0	7	0	0
T28	0	2	0	0
T61	126988	20	0	0
T62	133672	0	0	0
T63	816516	0	0	0
T91	528824	0	0	0
T100	0	12	0	0
T148	0	30	0	0
T163	0	18	0	0
T165	0	14	0	0
T167	0	14	0	0
T171	568594	0	0	0
T181	0	13	0	0
T243	159341	0	0	0
T244	100312	0	0	0
T245	99009	0	0	0
T246	138750	0	0	0
T288	0	16	0	0
T305	202478	0	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1285383986	983	0	0
T27	0	4	0	0
T28	0	12	0	0
T61	126988	13	0	0
T62	133672	0	0	0
T63	816516	0	0	0
T91	528824	0	0	0
T148	0	13	0	0
T163	0	10	0	0
T165	0	11	0	0
T167	0	15	0	0
T171	568594	0	0	0
T181	0	4	0	0
T233	0	16	0	0
T243	159341	0	0	0
T244	100312	0	0	0
T245	99009	0	0	0
T246	138750	0	0	0
T288	0	11	0	0
T305	202478	0	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1285383986	909	0	0
T61	126988	17	0	0
T62	133672	0	0	0
T63	816516	0	0	0
T91	528824	0	0	0
T100	0	1	0	0
T148	0	17	0	0
T149	0	5	0	0
T163	0	22	0	0
T165	0	12	0	0
T167	0	17	0	0
T171	568594	0	0	0
T181	0	11	0	0
T233	0	26	0	0
T243	159341	0	0	0
T244	100312	0	0	0
T245	99009	0	0	0
T246	138750	0	0	0
T288	0	13	0	0
T305	202478	0	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1285383986	920	0	0
T61	126988	19	0	0
T62	133672	0	0	0
T63	816516	0	0	0
T91	528824	0	0	0
T100	0	4	0	0
T148	0	14	0	0
T149	0	8	0	0
T163	0	18	0	0
T165	0	12	0	0
T167	0	15	0	0
T171	568594	0	0	0
T181	0	4	0	0
T233	0	14	0	0
T243	159341	0	0	0
T244	100312	0	0	0
T245	99009	0	0	0
T246	138750	0	0	0
T288	0	13	0	0
T305	202478	0	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1285383986	3565	0	0
T10	853198	72	0	0
T11	187507	0	0	0
T31	226917	0	0	0
T32	279313	0	0	0
T43	0	56	0	0
T47	0	38	0	0
T55	51207	0	0	0
T61	0	12	0	0
T68	31935	0	0	0
T71	53383	0	0	0
T79	0	28	0	0
T88	0	69	0	0
T90	0	50	0	0
T119	0	46	0	0
T127	0	67	0	0
T142	0	33	0	0
T187	398045	0	0	0
T188	57052	0	0	0
T304	35649	0	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1285383986	3724	0	0
T10	853198	68	0	0
T11	187507	0	0	0
T31	226917	0	0	0
T32	279313	0	0	0
T43	0	76	0	0
T47	0	40	0	0
T55	51207	0	0	0
T61	0	13	0	0
T68	31935	0	0	0
T71	53383	0	0	0
T79	0	36	0	0
T88	0	76	0	0
T90	0	47	0	0
T119	0	67	0	0
T127	0	73	0	0
T142	0	51	0	0
T187	398045	0	0	0
T188	57052	0	0	0
T304	35649	0	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1285383986	3583	0	0
T10	853198	78	0	0
T11	187507	0	0	0
T31	226917	0	0	0
T32	279313	0	0	0
T43	0	71	0	0
T47	0	32	0	0
T55	51207	0	0	0
T61	0	13	0	0
T68	31935	0	0	0
T71	53383	0	0	0
T79	0	20	0	0
T88	0	82	0	0
T90	0	41	0	0
T119	0	46	0	0
T127	0	47	0	0
T142	0	48	0	0
T187	398045	0	0	0
T188	57052	0	0	0
T304	35649	0	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1285383986	3532	0	0
T10	853198	68	0	0
T11	187507	0	0	0
T31	226917	0	0	0
T32	279313	0	0	0
T43	0	66	0	0
T47	0	51	0	0
T55	51207	0	0	0
T61	0	26	0	0
T68	31935	0	0	0
T71	53383	0	0	0
T79	0	24	0	0
T88	0	85	0	0
T90	0	50	0	0
T119	0	44	0	0
T127	0	69	0	0
T142	0	31	0	0
T187	398045	0	0	0
T188	57052	0	0	0
T304	35649	0	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1285383986	3702	0	0
T10	853198	49	0	0
T11	187507	0	0	0
T31	226917	0	0	0
T32	279313	0	0	0
T43	0	71	0	0
T47	0	48	0	0
T55	51207	0	0	0
T61	0	21	0	0
T68	31935	0	0	0
T71	53383	0	0	0
T79	0	32	0	0
T88	0	72	0	0
T90	0	64	0	0
T119	0	50	0	0
T127	0	57	0	0
T142	0	71	0	0
T187	398045	0	0	0
T188	57052	0	0	0
T304	35649	0	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1285383986	3816	0	0
T10	853198	79	0	0
T11	187507	0	0	0
T31	226917	0	0	0
T32	279313	0	0	0
T43	0	84	0	0
T47	0	55	0	0
T55	51207	0	0	0
T61	0	26	0	0
T68	31935	0	0	0
T71	53383	0	0	0
T79	0	30	0	0
T88	0	82	0	0
T90	0	60	0	0
T119	0	43	0	0
T127	0	73	0	0
T142	0	35	0	0
T187	398045	0	0	0
T188	57052	0	0	0
T304	35649	0	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1285383986	3464	0	0
T10	853198	106	0	0
T11	187507	0	0	0
T31	226917	0	0	0
T32	279313	0	0	0
T43	0	66	0	0
T47	0	37	0	0
T55	51207	0	0	0
T61	0	12	0	0
T68	31935	0	0	0
T71	53383	0	0	0
T79	0	30	0	0
T88	0	64	0	0
T90	0	58	0	0
T119	0	49	0	0
T127	0	54	0	0
T142	0	37	0	0
T187	398045	0	0	0
T188	57052	0	0	0
T304	35649	0	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1285383986	3572	0	0
T10	853198	60	0	0
T11	187507	0	0	0
T31	226917	0	0	0
T32	279313	0	0	0
T43	0	72	0	0
T47	0	46	0	0
T55	51207	0	0	0
T61	0	17	0	0
T68	31935	0	0	0
T71	53383	0	0	0
T79	0	33	0	0
T88	0	56	0	0
T90	0	67	0	0
T119	0	46	0	0
T127	0	69	0	0
T142	0	48	0	0
T187	398045	0	0	0
T188	57052	0	0	0
T304	35649	0	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1285383986	1953	0	0
T10	853198	12	0	0
T11	187507	0	0	0
T31	226917	0	0	0
T32	279313	0	0	0
T43	0	22	0	0
T47	0	8	0	0
T55	51207	0	0	0
T68	31935	0	0	0
T71	53383	0	0	0
T88	0	37	0	0
T89	0	2	0	0
T119	0	17	0	0
T127	0	42	0	0
T169	0	1	0	0
T187	398045	0	0	0
T188	57052	0	0	0
T304	35649	0	0	0
T306	0	1	0	0
T307	0	9	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1285383986	1456	0	0
T61	126988	17	0	0
T62	133672	0	0	0
T63	816516	0	0	0
T91	528824	0	0	0
T100	0	27	0	0
T149	0	23	0	0
T163	0	11	0	0
T165	0	18	0	0
T171	568594	0	0	0
T181	0	27	0	0
T219	0	18	0	0
T222	0	22	0	0
T243	159341	0	0	0
T244	100312	0	0	0
T245	99009	0	0	0
T246	138750	0	0	0
T288	0	26	0	0
T305	202478	0	0	0
T308	0	14	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1285383986	2220	0	0
T31	226917	0	0	0
T34	85897	0	0	0
T35	0	2	0	0
T61	0	18	0	0
T68	31935	0	0	0
T69	882598	0	0	0
T71	53383	2	0	0
T80	0	4	0	0
T153	0	9	0	0
T172	0	1	0	0
T187	398045	0	0	0
T188	57052	0	0	0
T189	51127	0	0	0
T190	51137	0	0	0
T195	0	3	0	0
T199	0	3	0	0
T256	0	9	0	0
T288	0	20	0	0
T303	93163	0	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1285383986	895	0	0
T61	126988	6	0	0
T62	133672	0	0	0
T63	816516	0	0	0
T91	528824	0	0	0
T100	0	2	0	0
T148	0	25	0	0
T149	0	7	0	0
T163	0	17	0	0
T165	0	13	0	0
T167	0	6	0	0
T171	568594	0	0	0
T181	0	11	0	0
T233	0	6	0	0
T243	159341	0	0	0
T244	100312	0	0	0
T245	99009	0	0	0
T246	138750	0	0	0
T288	0	7	0	0
T305	202478	0	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1285383986	3509	0	0
T44	105221	0	0	0
T45	344305	0	0	0
T46	258337	0	0	0
T56	51310	0	0	0
T58	121800	71	0	0
T60	0	64	0	0
T61	0	235	0	0
T86	240171	0	0	0
T149	0	121	0	0
T163	0	38	0	0
T219	0	146	0	0
T277	0	36	0	0
T288	0	98	0	0
T306	303628	0	0	0
T309	0	46	0	0
T310	0	80	0	0
T311	200802	0	0	0
T312	16307	0	0	0
T313	202588	0	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1285383986	4376	0	0
T10	853198	0	0	0
T11	187507	0	0	0
T32	279313	0	0	0
T55	51207	0	0	0
T61	0	11	0	0
T67	16374	48	0	0
T68	31935	0	0	0
T71	53383	0	0	0
T75	0	77	0	0
T111	0	31	0	0
T127	0	71	0	0
T187	398045	0	0	0
T188	57052	0	0	0
T227	0	60	0	0
T229	0	49	0	0
T288	0	5	0	0
T304	35649	0	0	0
T314	0	77	0	0
T315	0	86	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1285383986	3579	0	0
T10	853198	0	0	0
T11	187507	0	0	0
T32	279313	0	0	0
T55	51207	0	0	0
T61	0	21	0	0
T67	16374	72	0	0
T68	31935	0	0	0
T71	53383	0	0	0
T75	0	69	0	0
T111	0	46	0	0
T127	0	58	0	0
T187	398045	0	0	0
T188	57052	0	0	0
T227	0	65	0	0
T229	0	44	0	0
T288	0	11	0	0
T304	35649	0	0	0
T314	0	43	0	0
T315	0	44	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1285383986	3719	0	0
T10	853198	0	0	0
T11	187507	0	0	0
T32	279313	0	0	0
T55	51207	0	0	0
T61	0	2	0	0
T67	16374	81	0	0
T68	31935	0	0	0
T71	53383	0	0	0
T75	0	77	0	0
T111	0	28	0	0
T127	0	69	0	0
T187	398045	0	0	0
T188	57052	0	0	0
T227	0	61	0	0
T229	0	28	0	0
T288	0	7	0	0
T304	35649	0	0	0
T314	0	75	0	0
T315	0	75	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1285383986	1094	0	0
T61	126988	16	0	0
T62	133672	0	0	0
T63	816516	0	0	0
T91	528824	0	0	0
T100	0	17	0	0
T148	0	11	0	0
T149	0	8	0	0
T163	0	37	0	0
T165	0	5	0	0
T167	0	6	0	0
T171	568594	0	0	0
T181	0	13	0	0
T233	0	10	0	0
T243	159341	0	0	0
T244	100312	0	0	0
T245	99009	0	0	0
T246	138750	0	0	0
T288	0	18	0	0
T305	202478	0	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1285383986	958	0	0
T8	14634	8	0	0
T9	752417	0	0	0
T31	0	10	0	0
T53	196114	0	0	0
T54	103298	0	0	0
T61	0	22	0	0
T65	16061	0	0	0
T66	238017	0	0	0
T78	0	6	0	0
T121	46971	0	0	0
T124	31598	0	0	0
T125	50727	0	0	0
T126	101092	0	0	0
T130	0	4	0	0
T149	0	10	0	0
T159	0	10	0	0
T163	0	17	0	0
T288	0	31	0	0
T316	0	6	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1285383986	1030	0	0
T8	14634	14	0	0
T9	752417	0	0	0
T31	0	1	0	0
T53	196114	0	0	0
T54	103298	0	0	0
T61	0	21	0	0
T65	16061	0	0	0
T66	238017	0	0	0
T75	0	8	0	0
T78	0	1	0	0
T121	46971	0	0	0
T124	31598	0	0	0
T125	50727	0	0	0
T126	101092	0	0	0
T149	0	23	0	0
T163	0	19	0	0
T181	0	4	0	0
T288	0	7	0	0
T316	0	3	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1285383986	1035	0	0
T8	14634	11	0	0
T9	752417	0	0	0
T23	30534	0	0	0
T30	43806	6	0	0
T31	0	8	0	0
T53	196114	0	0	0
T54	103298	0	0	0
T61	0	10	0	0
T65	16061	0	0	0
T75	0	4	0	0
T78	0	7	0	0
T120	52677	0	0	0
T121	46971	0	0	0
T124	31598	0	0	0
T130	0	4	0	0
T149	0	10	0	0
T288	0	30	0	0
T316	0	10	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1285383986	1241	0	0
T8	14634	8	0	0
T9	752417	0	0	0
T53	196114	0	0	0
T54	103298	0	0	0
T61	0	21	0	0
T65	16061	0	0	0
T66	238017	0	0	0
T75	0	3	0	0
T78	0	10	0	0
T121	46971	0	0	0
T124	31598	0	0	0
T125	50727	0	0	0
T126	101092	0	0	0
T130	0	8	0	0
T149	0	13	0	0
T159	0	8	0	0
T163	0	25	0	0
T288	0	21	0	0
T316	0	4	0	0