Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_reg_cdc
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.30 100.00 89.20 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg.u_wkup_status_cdc 96.88 100.00 87.50 100.00 100.00
tb.dut.u_reg.u_ec_rst_ctl_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.u_reg.u_key_invert_ctl_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.u_reg.u_pin_out_ctl_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.u_reg.u_pin_out_value_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.u_reg.u_key_intr_ctl_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.u_reg.u_auto_block_out_ctl_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_0_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_1_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_2_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_3_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.u_reg.u_com_det_ctl_0_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.u_reg.u_com_det_ctl_1_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.u_reg.u_com_det_ctl_2_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.u_reg.u_com_det_ctl_3_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_0_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_1_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_2_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_3_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.u_reg.u_ulp_ctl_cdc 98.08 100.00 92.31 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_status_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.88 100.00 87.50 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.79 96.99 84.93 93.22 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.60 100.00 94.40 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 92.06 95.92 81.63 90.70 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.33 100.00 93.33 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.60 100.00 94.40 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 97.73 100.00 90.91 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.33 100.00 93.33 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.60 100.00 94.40 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 97.73 100.00 90.91 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.33 100.00 93.33 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.60 100.00 94.40 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 97.73 100.00 90.91 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.33 100.00 93.33 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.60 100.00 94.40 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 97.73 100.00 90.91 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.60 100.00 94.40 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.60 100.00 94.40 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.60 100.00 94.40 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_pin_out_value_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.60 100.00 94.40 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.60 100.00 94.40 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.60 100.00 94.40 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.33 100.00 93.33 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.60 100.00 94.40 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 97.73 100.00 90.91 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.60 100.00 94.40 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.60 100.00 94.40 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.60 100.00 94.40 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.60 100.00 94.40 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.60 100.00 94.40 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.60 100.00 94.40 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.60 100.00 94.40 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.60 100.00 94.40 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.60 100.00 94.40 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.60 100.00 94.40 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.60 100.00 94.40 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.60 100.00 94.40 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.60 100.00 94.40 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.60 100.00 94.40 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.60 100.00 94.40 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.60 100.00 94.40 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.60 100.00 94.40 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.60 100.00 94.40 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.60 100.00 94.40 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.60 100.00 94.40 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.60 100.00 94.40 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_ulp_ctl_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.08 100.00 92.31 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.22 100.00 96.88 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.60 100.00 94.40 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00

Line Coverage for Module : prim_reg_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Module : prim_reg_cdc ( parameter DataWidth=16,ResetVal,BitMask=65535,DstWrReq=0,TxnWidth=3 + DataWidth=12,ResetVal=0,BitMask=4095,DstWrReq=0,TxnWidth=3 + DataWidth=8,ResetVal,BitMask=255,DstWrReq=0,TxnWidth=3 + DataWidth=14,ResetVal=0,BitMask=16383,DstWrReq=0,TxnWidth=3 + DataWidth=17,ResetVal=2000,BitMask=131071,DstWrReq=0,TxnWidth=3 + DataWidth=7,ResetVal=0,BitMask=119,DstWrReq=0,TxnWidth=3 + DataWidth=5,ResetVal=0,BitMask=31,DstWrReq=0,TxnWidth=3 + DataWidth=32,ResetVal=0,BitMask=-1,DstWrReq=0,TxnWidth=3 + DataWidth=4,ResetVal=0,BitMask=15,DstWrReq=0,TxnWidth=3 )
Cond Coverage for Module self-instances :
SCORECOND
97.73 90.91
tb.dut.u_reg.u_ec_rst_ctl_cdc

SCORECOND
97.73 90.91
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

SCORECOND
97.73 90.91
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

SCORECOND
97.73 90.91
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

SCORECOND
97.73 90.91
tb.dut.u_reg.u_pin_allowed_ctl_cdc

SCORECOND
97.73 90.91
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

SCORECOND
97.73 90.91
tb.dut.u_reg.u_key_invert_ctl_cdc

SCORECOND
97.73 90.91
tb.dut.u_reg.u_pin_out_ctl_cdc

SCORECOND
97.73 90.91
tb.dut.u_reg.u_pin_out_value_cdc

SCORECOND
97.73 90.91
tb.dut.u_reg.u_key_intr_ctl_cdc

SCORECOND
97.73 90.91
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

SCORECOND
97.73 90.91
tb.dut.u_reg.u_auto_block_out_ctl_cdc

SCORECOND
97.73 90.91
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

SCORECOND
97.73 90.91
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

SCORECOND
97.73 90.91
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

SCORECOND
97.73 90.91
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

SCORECOND
97.73 90.91
tb.dut.u_reg.u_com_sel_ctl_0_cdc

SCORECOND
97.73 90.91
tb.dut.u_reg.u_com_sel_ctl_1_cdc

SCORECOND
97.73 90.91
tb.dut.u_reg.u_com_sel_ctl_2_cdc

SCORECOND
97.73 90.91
tb.dut.u_reg.u_com_sel_ctl_3_cdc

SCORECOND
97.73 90.91
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

SCORECOND
97.73 90.91
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

SCORECOND
97.73 90.91
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

SCORECOND
97.73 90.91
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

SCORECOND
97.73 90.91
tb.dut.u_reg.u_com_det_ctl_0_cdc

SCORECOND
97.73 90.91
tb.dut.u_reg.u_com_det_ctl_1_cdc

SCORECOND
97.73 90.91
tb.dut.u_reg.u_com_det_ctl_2_cdc

SCORECOND
97.73 90.91
tb.dut.u_reg.u_com_det_ctl_3_cdc

SCORECOND
97.73 90.91
tb.dut.u_reg.u_com_out_ctl_0_cdc

SCORECOND
97.73 90.91
tb.dut.u_reg.u_com_out_ctl_1_cdc

SCORECOND
97.73 90.91
tb.dut.u_reg.u_com_out_ctl_2_cdc

SCORECOND
97.73 90.91
tb.dut.u_reg.u_com_out_ctl_3_cdc

TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT5,T1,T2
01Unreachable
10CoveredT2,T12,T3

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT5,T1,T2
10CoveredT2,T12,T3
11CoveredT2,T12,T3

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT5,T1,T2
01Unreachable
10CoveredT2,T12,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT2,T12,T3
11CoveredT2,T12,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT5,T1,T2
10Unreachable
11Unreachable

Cond Coverage for Module : prim_reg_cdc ( parameter DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=0,TxnWidth=3 + DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=1,TxnWidth=3 )
Cond Coverage for Module self-instances :
SCORECOND
98.08 92.31
tb.dut.u_reg.u_ulp_ctl_cdc

SCORECOND
96.88 87.50
tb.dut.u_reg.u_wkup_status_cdc

TotalCoveredPercent
Conditions161487.50
Logical161487.50
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT5,T1,T2
01Unreachable
10CoveredT2,T3,T6

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT5,T1,T2
10CoveredT2,T3,T6
11CoveredT2,T3,T6

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---
-1--2-StatusTests
0-CoveredT3,T8,T11
1-CoveredT2,T3,T6

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT5,T1,T2
01CoveredT1,T2,T3
10CoveredT2,T3,T6

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT2,T3,T6
11CoveredT2,T3,T6

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT5,T1,T2
10Not Covered
11CoveredT1,T2,T3

Branch Coverage for Module : prim_reg_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T1,T2
0 1 - Covered T2,T3,T25
0 0 1 Covered T2,T3,T25
0 0 0 Covered T5,T1,T2


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T1,T2
0 1 - Covered T2,T3,T25
0 0 1 Covered T2,T3,T25
0 0 0 Covered T5,T1,T2


Assert Coverage for Module : prim_reg_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 2147483647 102764894 0 0
DstReqKnown_A 206518788 179415348 0 0
SrcAckBusyChk_A 2147483647 122222 0 0
SrcBusyKnown_A 2147483647 2147483647 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 102764894 0 0
T1 111236 0 0 0
T2 2102543 102736 0 0
T3 12110274 133220 0 0
T4 2349842 0 0 0
T6 1606290 6775 0 0
T7 276100 18274 0 0
T9 0 43374 0 0
T10 0 97441 0 0
T11 0 12069 0 0
T12 1203384 0 0 0
T13 1917651 0 0 0
T14 7960284 0 0 0
T15 1967648 0 0 0
T16 1728016 0 0 0
T17 11733604 12910 0 0
T25 3684928 5897 0 0
T32 0 33408 0 0
T33 0 6563 0 0
T40 0 9560 0 0
T41 0 9719 0 0
T42 0 6932 0 0
T43 0 17196 0 0
T44 0 4027 0 0
T45 0 15300 0 0
T46 0 1991 0 0
T47 0 4447 0 0
T48 0 7860 0 0
T49 0 6984 0 0
T50 3420502 0 0 0
T51 1088640 0 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 206518788 179415348 0 0
T1 16524 2924 0 0
T2 877540 821814 0 0
T3 260508 246908 0 0
T5 13668 68 0 0
T12 17918 4318 0 0
T13 13736 136 0 0
T14 16762 3162 0 0
T15 17884 4284 0 0
T16 13804 204 0 0
T17 24412 10812 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 122222 0 0
T1 111236 0 0 0
T2 2102543 64 0 0
T3 12110274 84 0 0
T4 2349842 0 0 0
T6 1606290 16 0 0
T7 276100 18 0 0
T9 0 54 0 0
T10 0 54 0 0
T11 0 25 0 0
T12 1203384 0 0 0
T13 1917651 0 0 0
T14 7960284 0 0 0
T15 1967648 0 0 0
T16 1728016 0 0 0
T17 11733604 8 0 0
T25 3684928 9 0 0
T32 0 80 0 0
T33 0 6 0 0
T40 0 6 0 0
T41 0 7 0 0
T42 0 8 0 0
T43 0 42 0 0
T44 0 7 0 0
T45 0 9 0 0
T46 0 1 0 0
T47 0 3 0 0
T48 0 9 0 0
T49 0 8 0 0
T50 3420502 0 0 0
T51 1088640 0 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 1891012 1887646 0 0
T2 4205086 4198626 0 0
T3 12477252 12477048 0 0
T5 6842942 6840528 0 0
T12 2153424 2151724 0 0
T13 3431586 3429750 0 0
T14 7960284 7957666 0 0
T15 1967648 1965064 0 0
T16 1728016 1726112 0 0
T17 11733604 11731632 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc
TotalCoveredPercent
Conditions161487.50
Logical161487.50
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT5,T1,T2
01Unreachable
10CoveredT2,T3,T6

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT5,T1,T2
10CoveredT2,T6,T7
11CoveredT2,T3,T6

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---
-1--2-StatusTests
0-CoveredT3,T52,T26
1-CoveredT2,T6,T7

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT5,T1,T2
01CoveredT1,T2,T3
10CoveredT2,T6,T7

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT2,T3,T6
11CoveredT2,T6,T7

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT5,T1,T2
10Not Covered
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T1,T2
0 1 - Covered T2,T3,T6
0 0 1 Covered T2,T6,T7
0 0 0 Covered T5,T1,T2


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T1,T2
0 1 - Covered T2,T3,T6
0 0 1 Covered T1,T2,T3
0 0 0 Covered T5,T1,T2


Assert Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 1285383986 1037106 0 0
DstReqKnown_A 6074082 5276922 0 0
SrcAckBusyChk_A 1285383986 1115 0 0
SrcBusyKnown_A 1285383986 1283545958 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 1037106 0 0
T2 123679 25388 0 0
T3 366978 1088 0 0
T4 69113 0 0 0
T6 0 457 0 0
T7 0 1031 0 0
T8 0 93 0 0
T9 0 702 0 0
T10 0 9379 0 0
T11 0 989 0 0
T12 63336 0 0 0
T13 100929 0 0 0
T14 234126 0 0 0
T15 57872 0 0 0
T16 50824 0 0 0
T17 345106 0 0 0
T25 115154 0 0 0
T31 0 1964 0 0
T32 0 1665 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6074082 5276922 0 0
T1 486 86 0 0
T2 25810 24171 0 0
T3 7662 7262 0 0
T5 402 2 0 0
T12 527 127 0 0
T13 404 4 0 0
T14 493 93 0 0
T15 526 126 0 0
T16 406 6 0 0
T17 718 318 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 1115 0 0
T2 123679 15 0 0
T3 366978 0 0 0
T4 69113 0 0 0
T6 0 1 0 0
T7 0 1 0 0
T8 0 1 0 0
T9 0 1 0 0
T10 0 5 0 0
T11 0 2 0 0
T12 63336 0 0 0
T13 100929 0 0 0
T14 234126 0 0 0
T15 57872 0 0 0
T16 50824 0 0 0
T17 345106 0 0 0
T25 115154 0 0 0
T31 0 1 0 0
T32 0 4 0 0
T33 0 4 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 1283545958 0 0
T1 55618 55519 0 0
T2 123679 123489 0 0
T3 366978 366972 0 0
T5 201263 201192 0 0
T12 63336 63286 0 0
T13 100929 100875 0 0
T14 234126 234049 0 0
T15 57872 57796 0 0
T16 50824 50768 0 0
T17 345106 345048 0 0

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT5,T1,T2
01Unreachable
10CoveredT2,T3,T25

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT5,T1,T2
10CoveredT2,T3,T25
11CoveredT2,T3,T25

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT5,T1,T2
01Unreachable
10CoveredT2,T3,T25

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT2,T3,T25
11CoveredT2,T3,T25

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT5,T1,T2
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T1,T2
0 1 - Covered T2,T3,T25
0 0 1 Covered T2,T3,T25
0 0 0 Covered T5,T1,T2


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T1,T2
0 1 - Covered T2,T3,T25
0 0 1 Covered T2,T3,T25
0 0 0 Covered T5,T1,T2


Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 1285383986 1685665 0 0
DstReqKnown_A 6074082 5276922 0 0
SrcAckBusyChk_A 1285383986 2165 0 0
SrcBusyKnown_A 1285383986 1283545958 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 1685665 0 0
T2 123679 12770 0 0
T3 366978 1440 0 0
T4 69113 0 0 0
T6 0 787 0 0
T7 0 1990 0 0
T9 0 4698 0 0
T10 0 10173 0 0
T11 0 3180 0 0
T12 63336 0 0 0
T13 100929 0 0 0
T14 234126 0 0 0
T15 57872 0 0 0
T16 50824 0 0 0
T17 345106 0 0 0
T25 115154 635 0 0
T32 0 4086 0 0
T51 0 478 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6074082 5276922 0 0
T1 486 86 0 0
T2 25810 24171 0 0
T3 7662 7262 0 0
T5 402 2 0 0
T12 527 127 0 0
T13 404 4 0 0
T14 493 93 0 0
T15 526 126 0 0
T16 406 6 0 0
T17 718 318 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 2165 0 0
T2 123679 8 0 0
T3 366978 1 0 0
T4 69113 0 0 0
T6 0 2 0 0
T7 0 2 0 0
T9 0 6 0 0
T10 0 6 0 0
T11 0 7 0 0
T12 63336 0 0 0
T13 100929 0 0 0
T14 234126 0 0 0
T15 57872 0 0 0
T16 50824 0 0 0
T17 345106 0 0 0
T25 115154 1 0 0
T32 0 10 0 0
T51 0 1 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 1283545958 0 0
T1 55618 55519 0 0
T2 123679 123489 0 0
T3 366978 366972 0 0
T5 201263 201192 0 0
T12 63336 63286 0 0
T13 100929 100875 0 0
T14 234126 234049 0 0
T15 57872 57796 0 0
T16 50824 50768 0 0
T17 345106 345048 0 0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT5,T1,T2
01Unreachable
10CoveredT3,T30,T8

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT5,T1,T2
10CoveredT3,T30,T8
11CoveredT3,T30,T8

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT5,T1,T2
01Unreachable
10CoveredT3,T30,T8

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT3,T30,T8
11CoveredT3,T30,T8

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT5,T1,T2
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T1,T2
0 1 - Covered T3,T30,T8
0 0 1 Covered T3,T30,T8
0 0 0 Covered T5,T1,T2


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T1,T2
0 1 - Covered T3,T30,T8
0 0 1 Covered T3,T30,T8
0 0 0 Covered T5,T1,T2


Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 1285383986 833032 0 0
DstReqKnown_A 6074082 5276922 0 0
SrcAckBusyChk_A 1285383986 1178 0 0
SrcBusyKnown_A 1285383986 1283545958 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 833032 0 0
T3 366978 1440 0 0
T4 69113 0 0 0
T6 107086 0 0 0
T8 0 218 0 0
T11 0 498 0 0
T14 234126 0 0 0
T15 57872 0 0 0
T16 50824 0 0 0
T17 345106 0 0 0
T25 115154 0 0 0
T30 0 416 0 0
T31 0 1984 0 0
T50 201206 0 0 0
T51 72576 0 0 0
T53 0 1424 0 0
T54 0 2441 0 0
T55 0 371 0 0
T56 0 830 0 0
T57 0 3773 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6074082 5276922 0 0
T1 486 86 0 0
T2 25810 24171 0 0
T3 7662 7262 0 0
T5 402 2 0 0
T12 527 127 0 0
T13 404 4 0 0
T14 493 93 0 0
T15 526 126 0 0
T16 406 6 0 0
T17 718 318 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 1178 0 0
T3 366978 1 0 0
T4 69113 0 0 0
T6 107086 0 0 0
T8 0 2 0 0
T11 0 1 0 0
T14 234126 0 0 0
T15 57872 0 0 0
T16 50824 0 0 0
T17 345106 0 0 0
T25 115154 0 0 0
T30 0 1 0 0
T31 0 1 0 0
T50 201206 0 0 0
T51 72576 0 0 0
T53 0 1 0 0
T54 0 3 0 0
T55 0 1 0 0
T56 0 2 0 0
T57 0 2 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 1283545958 0 0
T1 55618 55519 0 0
T2 123679 123489 0 0
T3 366978 366972 0 0
T5 201263 201192 0 0
T12 63336 63286 0 0
T13 100929 100875 0 0
T14 234126 234049 0 0
T15 57872 57796 0 0
T16 50824 50768 0 0
T17 345106 345048 0 0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT5,T1,T2
01Unreachable
10CoveredT3,T30,T8

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT5,T1,T2
10CoveredT3,T30,T8
11CoveredT3,T30,T8

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT5,T1,T2
01Unreachable
10CoveredT3,T30,T8

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT3,T30,T8
11CoveredT3,T30,T8

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT5,T1,T2
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T1,T2
0 1 - Covered T3,T30,T8
0 0 1 Covered T3,T30,T8
0 0 0 Covered T5,T1,T2


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T1,T2
0 1 - Covered T3,T30,T8
0 0 1 Covered T3,T30,T8
0 0 0 Covered T5,T1,T2


Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 1285383986 849985 0 0
DstReqKnown_A 6074082 5276922 0 0
SrcAckBusyChk_A 1285383986 1176 0 0
SrcBusyKnown_A 1285383986 1283545958 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 849985 0 0
T3 366978 1438 0 0
T4 69113 0 0 0
T6 107086 0 0 0
T8 0 221 0 0
T11 0 496 0 0
T14 234126 0 0 0
T15 57872 0 0 0
T16 50824 0 0 0
T17 345106 0 0 0
T25 115154 0 0 0
T30 0 407 0 0
T31 0 1975 0 0
T50 201206 0 0 0
T51 72576 0 0 0
T53 0 1422 0 0
T54 0 2435 0 0
T55 0 369 0 0
T56 0 823 0 0
T57 0 3754 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6074082 5276922 0 0
T1 486 86 0 0
T2 25810 24171 0 0
T3 7662 7262 0 0
T5 402 2 0 0
T12 527 127 0 0
T13 404 4 0 0
T14 493 93 0 0
T15 526 126 0 0
T16 406 6 0 0
T17 718 318 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 1176 0 0
T3 366978 1 0 0
T4 69113 0 0 0
T6 107086 0 0 0
T8 0 2 0 0
T11 0 1 0 0
T14 234126 0 0 0
T15 57872 0 0 0
T16 50824 0 0 0
T17 345106 0 0 0
T25 115154 0 0 0
T30 0 1 0 0
T31 0 1 0 0
T50 201206 0 0 0
T51 72576 0 0 0
T53 0 1 0 0
T54 0 3 0 0
T55 0 1 0 0
T56 0 2 0 0
T57 0 2 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 1283545958 0 0
T1 55618 55519 0 0
T2 123679 123489 0 0
T3 366978 366972 0 0
T5 201263 201192 0 0
T12 63336 63286 0 0
T13 100929 100875 0 0
T14 234126 234049 0 0
T15 57872 57796 0 0
T16 50824 50768 0 0
T17 345106 345048 0 0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT5,T1,T2
01Unreachable
10CoveredT3,T30,T8

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT5,T1,T2
10CoveredT3,T30,T8
11CoveredT3,T30,T8

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT5,T1,T2
01Unreachable
10CoveredT3,T30,T8

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT3,T30,T8
11CoveredT3,T30,T8

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT5,T1,T2
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T1,T2
0 1 - Covered T3,T30,T8
0 0 1 Covered T3,T30,T8
0 0 0 Covered T5,T1,T2


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T1,T2
0 1 - Covered T3,T30,T8
0 0 1 Covered T3,T30,T8
0 0 0 Covered T5,T1,T2


Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 1285383986 873550 0 0
DstReqKnown_A 6074082 5276922 0 0
SrcAckBusyChk_A 1285383986 1218 0 0
SrcBusyKnown_A 1285383986 1283545958 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 873550 0 0
T3 366978 1436 0 0
T4 69113 0 0 0
T6 107086 0 0 0
T8 0 204 0 0
T11 0 494 0 0
T14 234126 0 0 0
T15 57872 0 0 0
T16 50824 0 0 0
T17 345106 0 0 0
T25 115154 0 0 0
T30 0 404 0 0
T31 0 1958 0 0
T50 201206 0 0 0
T51 72576 0 0 0
T53 0 1420 0 0
T54 0 2429 0 0
T55 0 367 0 0
T56 0 809 0 0
T57 0 3744 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6074082 5276922 0 0
T1 486 86 0 0
T2 25810 24171 0 0
T3 7662 7262 0 0
T5 402 2 0 0
T12 527 127 0 0
T13 404 4 0 0
T14 493 93 0 0
T15 526 126 0 0
T16 406 6 0 0
T17 718 318 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 1218 0 0
T3 366978 1 0 0
T4 69113 0 0 0
T6 107086 0 0 0
T8 0 2 0 0
T11 0 1 0 0
T14 234126 0 0 0
T15 57872 0 0 0
T16 50824 0 0 0
T17 345106 0 0 0
T25 115154 0 0 0
T30 0 1 0 0
T31 0 1 0 0
T50 201206 0 0 0
T51 72576 0 0 0
T53 0 1 0 0
T54 0 3 0 0
T55 0 1 0 0
T56 0 2 0 0
T57 0 2 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 1283545958 0 0
T1 55618 55519 0 0
T2 123679 123489 0 0
T3 366978 366972 0 0
T5 201263 201192 0 0
T12 63336 63286 0 0
T13 100929 100875 0 0
T14 234126 234049 0 0
T15 57872 57796 0 0
T16 50824 50768 0 0
T17 345106 345048 0 0

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT5,T1,T2
01Unreachable
10CoveredT14,T21,T22

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT5,T1,T2
10CoveredT14,T21,T22
11CoveredT14,T21,T22

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT5,T1,T2
01Unreachable
10CoveredT14,T21,T22

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT14,T21,T22
11CoveredT14,T21,T22

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT5,T1,T2
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T1,T2
0 1 - Covered T14,T21,T22
0 0 1 Covered T14,T21,T22
0 0 0 Covered T5,T1,T2


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T1,T2
0 1 - Covered T14,T21,T22
0 0 1 Covered T14,T21,T22
0 0 0 Covered T5,T1,T2


Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 1285383986 2504524 0 0
DstReqKnown_A 6074082 5276922 0 0
SrcAckBusyChk_A 1285383986 3156 0 0
SrcBusyKnown_A 1285383986 1283545958 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 2504524 0 0
T4 69113 0 0 0
T6 107086 0 0 0
T7 276100 0 0 0
T14 234126 33624 0 0
T15 57872 0 0 0
T16 50824 0 0 0
T17 345106 0 0 0
T21 0 30817 0 0
T22 0 9252 0 0
T25 115154 0 0 0
T50 201206 0 0 0
T51 72576 0 0 0
T58 0 17780 0 0
T59 0 3908 0 0
T60 0 7944 0 0
T61 0 100904 0 0
T62 0 34442 0 0
T63 0 8360 0 0
T64 0 8405 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6074082 5276922 0 0
T1 486 86 0 0
T2 25810 24171 0 0
T3 7662 7262 0 0
T5 402 2 0 0
T12 527 127 0 0
T13 404 4 0 0
T14 493 93 0 0
T15 526 126 0 0
T16 406 6 0 0
T17 718 318 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 3156 0 0
T4 69113 0 0 0
T6 107086 0 0 0
T7 276100 0 0 0
T14 234126 20 0 0
T15 57872 0 0 0
T16 50824 0 0 0
T17 345106 0 0 0
T21 0 20 0 0
T22 0 20 0 0
T25 115154 0 0 0
T50 201206 0 0 0
T51 72576 0 0 0
T58 0 20 0 0
T59 0 20 0 0
T60 0 20 0 0
T61 0 60 0 0
T62 0 20 0 0
T63 0 20 0 0
T64 0 20 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 1283545958 0 0
T1 55618 55519 0 0
T2 123679 123489 0 0
T3 366978 366972 0 0
T5 201263 201192 0 0
T12 63336 63286 0 0
T13 100929 100875 0 0
T14 234126 234049 0 0
T15 57872 57796 0 0
T16 50824 50768 0 0
T17 345106 345048 0 0

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT5,T1,T2
01Unreachable
10CoveredT12,T14,T15

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT5,T1,T2
10CoveredT12,T14,T15
11CoveredT12,T14,T15

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT5,T1,T2
01Unreachable
10CoveredT12,T14,T15

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT12,T14,T15
11CoveredT12,T14,T15

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT5,T1,T2
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T1,T2
0 1 - Covered T12,T14,T15
0 0 1 Covered T12,T14,T15
0 0 0 Covered T5,T1,T2


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T1,T2
0 1 - Covered T12,T14,T15
0 0 1 Covered T12,T14,T15
0 0 0 Covered T5,T1,T2


Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 1285383986 4912628 0 0
DstReqKnown_A 6074082 5276922 0 0
SrcAckBusyChk_A 1285383986 6027 0 0
SrcBusyKnown_A 1285383986 1283545958 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 4912628 0 0
T3 366978 0 0 0
T4 69113 0 0 0
T11 0 25908 0 0
T12 63336 8208 0 0
T13 100929 0 0 0
T14 234126 1883 0 0
T15 57872 7292 0 0
T16 50824 0 0 0
T17 345106 0 0 0
T23 0 3903 0 0
T25 115154 0 0 0
T50 201206 0 0 0
T65 0 1967 0 0
T66 0 30432 0 0
T67 0 1708 0 0
T68 0 3554 0 0
T69 0 35155 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6074082 5276922 0 0
T1 486 86 0 0
T2 25810 24171 0 0
T3 7662 7262 0 0
T5 402 2 0 0
T12 527 127 0 0
T13 404 4 0 0
T14 493 93 0 0
T15 526 126 0 0
T16 406 6 0 0
T17 718 318 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 6027 0 0
T3 366978 0 0 0
T4 69113 0 0 0
T11 0 60 0 0
T12 63336 20 0 0
T13 100929 0 0 0
T14 234126 1 0 0
T15 57872 20 0 0
T16 50824 0 0 0
T17 345106 0 0 0
T23 0 20 0 0
T25 115154 0 0 0
T50 201206 0 0 0
T65 0 20 0 0
T66 0 20 0 0
T67 0 20 0 0
T68 0 20 0 0
T69 0 20 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 1283545958 0 0
T1 55618 55519 0 0
T2 123679 123489 0 0
T3 366978 366972 0 0
T5 201263 201192 0 0
T12 63336 63286 0 0
T13 100929 100875 0 0
T14 234126 234049 0 0
T15 57872 57796 0 0
T16 50824 50768 0 0
T17 345106 345048 0 0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT5,T1,T2
01Unreachable
10CoveredT2,T12,T3

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT5,T1,T2
10CoveredT2,T12,T3
11CoveredT2,T12,T3

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT5,T1,T2
01Unreachable
10CoveredT2,T12,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT2,T12,T3
11CoveredT2,T12,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT5,T1,T2
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T1,T2
0 1 - Covered T2,T12,T3
0 0 1 Covered T2,T12,T3
0 0 0 Covered T5,T1,T2


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T1,T2
0 1 - Covered T2,T12,T3
0 0 1 Covered T2,T12,T3
0 0 0 Covered T5,T1,T2


Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 1285383986 6047648 0 0
DstReqKnown_A 6074082 5276922 0 0
SrcAckBusyChk_A 1285383986 7171 0 0
SrcBusyKnown_A 1285383986 1283545958 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 6047648 0 0
T2 123679 12945 0 0
T3 366978 1439 0 0
T4 69113 0 0 0
T6 0 949 0 0
T7 0 2064 0 0
T12 63336 8288 0 0
T13 100929 0 0 0
T14 234126 1888 0 0
T15 57872 7578 0 0
T16 50824 0 0 0
T17 345106 0 0 0
T23 0 4163 0 0
T25 115154 671 0 0
T51 0 480 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6074082 5276922 0 0
T1 486 86 0 0
T2 25810 24171 0 0
T3 7662 7262 0 0
T5 402 2 0 0
T12 527 127 0 0
T13 404 4 0 0
T14 493 93 0 0
T15 526 126 0 0
T16 406 6 0 0
T17 718 318 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 7171 0 0
T2 123679 8 0 0
T3 366978 1 0 0
T4 69113 0 0 0
T6 0 2 0 0
T7 0 2 0 0
T12 63336 20 0 0
T13 100929 0 0 0
T14 234126 1 0 0
T15 57872 20 0 0
T16 50824 0 0 0
T17 345106 0 0 0
T23 0 20 0 0
T25 115154 1 0 0
T51 0 1 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 1283545958 0 0
T1 55618 55519 0 0
T2 123679 123489 0 0
T3 366978 366972 0 0
T5 201263 201192 0 0
T12 63336 63286 0 0
T13 100929 100875 0 0
T14 234126 234049 0 0
T15 57872 57796 0 0
T16 50824 50768 0 0
T17 345106 345048 0 0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT5,T1,T2
01Unreachable
10CoveredT12,T15,T23

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT5,T1,T2
10CoveredT12,T15,T23
11CoveredT12,T15,T23

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT5,T1,T2
01Unreachable
10CoveredT12,T15,T23

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT12,T15,T23
11CoveredT12,T15,T23

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT5,T1,T2
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T1,T2
0 1 - Covered T12,T15,T23
0 0 1 Covered T12,T15,T23
0 0 0 Covered T5,T1,T2


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T1,T2
0 1 - Covered T12,T15,T23
0 0 1 Covered T12,T15,T23
0 0 0 Covered T5,T1,T2


Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 1285383986 4883805 0 0
DstReqKnown_A 6074082 5276922 0 0
SrcAckBusyChk_A 1285383986 5913 0 0
SrcBusyKnown_A 1285383986 1283545958 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 4883805 0 0
T3 366978 0 0 0
T4 69113 0 0 0
T11 0 26028 0 0
T12 63336 8248 0 0
T13 100929 0 0 0
T14 234126 0 0 0
T15 57872 7441 0 0
T16 50824 0 0 0
T17 345106 0 0 0
T23 0 4040 0 0
T25 115154 0 0 0
T50 201206 0 0 0
T65 0 2007 0 0
T66 0 30642 0 0
T67 0 1750 0 0
T68 0 3697 0 0
T69 0 35368 0 0
T70 0 12014 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6074082 5276922 0 0
T1 486 86 0 0
T2 25810 24171 0 0
T3 7662 7262 0 0
T5 402 2 0 0
T12 527 127 0 0
T13 404 4 0 0
T14 493 93 0 0
T15 526 126 0 0
T16 406 6 0 0
T17 718 318 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 5913 0 0
T3 366978 0 0 0
T4 69113 0 0 0
T11 0 60 0 0
T12 63336 20 0 0
T13 100929 0 0 0
T14 234126 0 0 0
T15 57872 20 0 0
T16 50824 0 0 0
T17 345106 0 0 0
T23 0 20 0 0
T25 115154 0 0 0
T50 201206 0 0 0
T65 0 20 0 0
T66 0 20 0 0
T67 0 20 0 0
T68 0 20 0 0
T69 0 20 0 0
T70 0 20 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 1283545958 0 0
T1 55618 55519 0 0
T2 123679 123489 0 0
T3 366978 366972 0 0
T5 201263 201192 0 0
T12 63336 63286 0 0
T13 100929 100875 0 0
T14 234126 234049 0 0
T15 57872 57796 0 0
T16 50824 50768 0 0
T17 345106 345048 0 0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT5,T1,T2
01Unreachable
10CoveredT1,T2,T3

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT5,T1,T2
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT5,T1,T2
01Unreachable
10CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT5,T1,T2
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T1,T2
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T5,T1,T2


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T1,T2
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T5,T1,T2


Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 1285383986 887152 0 0
DstReqKnown_A 6074082 5276922 0 0
SrcAckBusyChk_A 1285383986 1213 0 0
SrcBusyKnown_A 1285383986 1283545958 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 887152 0 0
T1 55618 357 0 0
T2 123679 1436 0 0
T3 366978 46035 0 0
T4 69113 466 0 0
T11 0 1991 0 0
T12 63336 0 0 0
T13 100929 0 0 0
T14 234126 0 0 0
T15 57872 0 0 0
T16 50824 0 0 0
T17 345106 0 0 0
T34 0 359 0 0
T35 0 711 0 0
T36 0 734 0 0
T40 0 1436 0 0
T71 0 471 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6074082 5276922 0 0
T1 486 86 0 0
T2 25810 24171 0 0
T3 7662 7262 0 0
T5 402 2 0 0
T12 527 127 0 0
T13 404 4 0 0
T14 493 93 0 0
T15 526 126 0 0
T16 406 6 0 0
T17 718 318 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 1213 0 0
T1 55618 1 0 0
T2 123679 1 0 0
T3 366978 28 0 0
T4 69113 1 0 0
T11 0 4 0 0
T12 63336 0 0 0
T13 100929 0 0 0
T14 234126 0 0 0
T15 57872 0 0 0
T16 50824 0 0 0
T17 345106 0 0 0
T34 0 1 0 0
T35 0 1 0 0
T36 0 1 0 0
T40 0 1 0 0
T71 0 1 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 1283545958 0 0
T1 55618 55519 0 0
T2 123679 123489 0 0
T3 366978 366972 0 0
T5 201263 201192 0 0
T12 63336 63286 0 0
T13 100929 100875 0 0
T14 234126 234049 0 0
T15 57872 57796 0 0
T16 50824 50768 0 0
T17 345106 345048 0 0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT5,T1,T2
01Unreachable
10CoveredT1,T2,T3

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT5,T1,T2
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT5,T1,T2
01Unreachable
10CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT5,T1,T2
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T1,T2
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T5,T1,T2


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T1,T2
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T5,T1,T2


Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 1285383986 1693563 0 0
DstReqKnown_A 6074082 5276922 0 0
SrcAckBusyChk_A 1285383986 2195 0 0
SrcBusyKnown_A 1285383986 1283545958 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 1693563 0 0
T1 55618 351 0 0
T2 123679 14669 0 0
T3 366978 2868 0 0
T4 69113 455 0 0
T6 0 775 0 0
T7 0 1986 0 0
T9 0 4686 0 0
T10 0 10101 0 0
T11 0 4160 0 0
T12 63336 0 0 0
T13 100929 0 0 0
T14 234126 0 0 0
T15 57872 0 0 0
T16 50824 0 0 0
T17 345106 0 0 0
T25 0 633 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6074082 5276922 0 0
T1 486 86 0 0
T2 25810 24171 0 0
T3 7662 7262 0 0
T5 402 2 0 0
T12 527 127 0 0
T13 404 4 0 0
T14 493 93 0 0
T15 526 126 0 0
T16 406 6 0 0
T17 718 318 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 2195 0 0
T1 55618 1 0 0
T2 123679 9 0 0
T3 366978 2 0 0
T4 69113 1 0 0
T6 0 2 0 0
T7 0 2 0 0
T9 0 6 0 0
T10 0 6 0 0
T11 0 9 0 0
T12 63336 0 0 0
T13 100929 0 0 0
T14 234126 0 0 0
T15 57872 0 0 0
T16 50824 0 0 0
T17 345106 0 0 0
T25 0 1 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 1283545958 0 0
T1 55618 55519 0 0
T2 123679 123489 0 0
T3 366978 366972 0 0
T5 201263 201192 0 0
T12 63336 63286 0 0
T13 100929 100875 0 0
T14 234126 234049 0 0
T15 57872 57796 0 0
T16 50824 50768 0 0
T17 345106 345048 0 0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT5,T1,T2
01Unreachable
10CoveredT3,T17,T11

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT5,T1,T2
10CoveredT3,T17,T11
11CoveredT3,T17,T11

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT5,T1,T2
01Unreachable
10CoveredT3,T17,T11

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT3,T17,T11
11CoveredT3,T17,T11

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT5,T1,T2
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T1,T2
0 1 - Covered T3,T17,T11
0 0 1 Covered T3,T17,T11
0 0 0 Covered T5,T1,T2


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T1,T2
0 1 - Covered T3,T17,T11
0 0 1 Covered T3,T17,T11
0 0 0 Covered T5,T1,T2


Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 1285383986 1201219 0 0
DstReqKnown_A 6074082 5276922 0 0
SrcAckBusyChk_A 1285383986 1551 0 0
SrcBusyKnown_A 1285383986 1283545958 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 1201219 0 0
T3 366978 2880 0 0
T4 69113 0 0 0
T6 107086 0 0 0
T11 0 2371 0 0
T14 234126 0 0 0
T15 57872 0 0 0
T16 50824 0 0 0
T17 345106 8147 0 0
T25 115154 0 0 0
T40 0 6702 0 0
T41 0 7081 0 0
T42 0 4234 0 0
T44 0 2310 0 0
T45 0 10055 0 0
T48 0 5251 0 0
T49 0 4243 0 0
T50 201206 0 0 0
T51 72576 0 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6074082 5276922 0 0
T1 486 86 0 0
T2 25810 24171 0 0
T3 7662 7262 0 0
T5 402 2 0 0
T12 527 127 0 0
T13 404 4 0 0
T14 493 93 0 0
T15 526 126 0 0
T16 406 6 0 0
T17 718 318 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 1551 0 0
T3 366978 2 0 0
T4 69113 0 0 0
T6 107086 0 0 0
T11 0 5 0 0
T14 234126 0 0 0
T15 57872 0 0 0
T16 50824 0 0 0
T17 345106 5 0 0
T25 115154 0 0 0
T40 0 4 0 0
T41 0 5 0 0
T42 0 5 0 0
T44 0 4 0 0
T45 0 6 0 0
T48 0 6 0 0
T49 0 5 0 0
T50 201206 0 0 0
T51 72576 0 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 1283545958 0 0
T1 55618 55519 0 0
T2 123679 123489 0 0
T3 366978 366972 0 0
T5 201263 201192 0 0
T12 63336 63286 0 0
T13 100929 100875 0 0
T14 234126 234049 0 0
T15 57872 57796 0 0
T16 50824 50768 0 0
T17 345106 345048 0 0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT5,T1,T2
01Unreachable
10CoveredT3,T17,T11

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT5,T1,T2
10CoveredT3,T17,T11
11CoveredT3,T17,T11

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT5,T1,T2
01Unreachable
10CoveredT3,T17,T11

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT3,T17,T11
11CoveredT3,T17,T11

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT5,T1,T2
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T1,T2
0 1 - Covered T3,T17,T11
0 0 1 Covered T3,T17,T11
0 0 0 Covered T5,T1,T2


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T1,T2
0 1 - Covered T3,T17,T11
0 0 1 Covered T3,T17,T11
0 0 0 Covered T5,T1,T2


Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 1285383986 1016322 0 0
DstReqKnown_A 6074082 5276922 0 0
SrcAckBusyChk_A 1285383986 1351 0 0
SrcBusyKnown_A 1285383986 1283545958 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 1016322 0 0
T3 366978 1440 0 0
T4 69113 0 0 0
T6 107086 0 0 0
T11 0 1862 0 0
T14 234126 0 0 0
T15 57872 0 0 0
T16 50824 0 0 0
T17 345106 4763 0 0
T25 115154 0 0 0
T40 0 2858 0 0
T41 0 2638 0 0
T42 0 2698 0 0
T44 0 1717 0 0
T45 0 5245 0 0
T48 0 2609 0 0
T49 0 2741 0 0
T50 201206 0 0 0
T51 72576 0 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6074082 5276922 0 0
T1 486 86 0 0
T2 25810 24171 0 0
T3 7662 7262 0 0
T5 402 2 0 0
T12 527 127 0 0
T13 404 4 0 0
T14 493 93 0 0
T15 526 126 0 0
T16 406 6 0 0
T17 718 318 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 1351 0 0
T3 366978 1 0 0
T4 69113 0 0 0
T6 107086 0 0 0
T11 0 4 0 0
T14 234126 0 0 0
T15 57872 0 0 0
T16 50824 0 0 0
T17 345106 3 0 0
T25 115154 0 0 0
T40 0 2 0 0
T41 0 2 0 0
T42 0 3 0 0
T44 0 3 0 0
T45 0 3 0 0
T48 0 3 0 0
T49 0 3 0 0
T50 201206 0 0 0
T51 72576 0 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 1283545958 0 0
T1 55618 55519 0 0
T2 123679 123489 0 0
T3 366978 366972 0 0
T5 201263 201192 0 0
T12 63336 63286 0 0
T13 100929 100875 0 0
T14 234126 234049 0 0
T15 57872 57796 0 0
T16 50824 50768 0 0
T17 345106 345048 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT5,T1,T2
01Unreachable
10CoveredT3,T25,T7

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT5,T1,T2
10CoveredT3,T25,T7
11CoveredT3,T25,T7

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT5,T1,T2
01Unreachable
10CoveredT3,T25,T7

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT3,T25,T7
11CoveredT3,T25,T7

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT5,T1,T2
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T1,T2
0 1 - Covered T3,T25,T7
0 0 1 Covered T3,T25,T7
0 0 0 Covered T5,T1,T2


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T1,T2
0 1 - Covered T3,T25,T7
0 0 1 Covered T3,T25,T7
0 0 0 Covered T5,T1,T2


Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 1285383986 6990105 0 0
DstReqKnown_A 6074082 5276922 0 0
SrcAckBusyChk_A 1285383986 7738 0 0
SrcBusyKnown_A 1285383986 1283545958 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 6990105 0 0
T3 366978 17745 0 0
T4 69113 0 0 0
T6 107086 0 0 0
T7 0 63404 0 0
T9 0 51000 0 0
T10 0 122472 0 0
T14 234126 0 0 0
T15 57872 0 0 0
T16 50824 0 0 0
T17 345106 0 0 0
T25 115154 38845 0 0
T33 0 93820 0 0
T46 0 87358 0 0
T47 0 109042 0 0
T50 201206 0 0 0
T51 72576 0 0 0
T72 0 39679 0 0
T73 0 85817 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6074082 5276922 0 0
T1 486 86 0 0
T2 25810 24171 0 0
T3 7662 7262 0 0
T5 402 2 0 0
T12 527 127 0 0
T13 404 4 0 0
T14 493 93 0 0
T15 526 126 0 0
T16 406 6 0 0
T17 718 318 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 7738 0 0
T3 366978 11 0 0
T4 69113 0 0 0
T6 107086 0 0 0
T7 0 52 0 0
T9 0 61 0 0
T10 0 71 0 0
T14 234126 0 0 0
T15 57872 0 0 0
T16 50824 0 0 0
T17 345106 0 0 0
T25 115154 51 0 0
T33 0 84 0 0
T46 0 51 0 0
T47 0 64 0 0
T50 201206 0 0 0
T51 72576 0 0 0
T72 0 70 0 0
T73 0 51 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 1283545958 0 0
T1 55618 55519 0 0
T2 123679 123489 0 0
T3 366978 366972 0 0
T5 201263 201192 0 0
T12 63336 63286 0 0
T13 100929 100875 0 0
T14 234126 234049 0 0
T15 57872 57796 0 0
T16 50824 50768 0 0
T17 345106 345048 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT5,T1,T2
01Unreachable
10CoveredT3,T25,T7

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT5,T1,T2
10CoveredT3,T25,T7
11CoveredT3,T25,T7

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT5,T1,T2
01Unreachable
10CoveredT3,T25,T7

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT3,T25,T7
11CoveredT3,T25,T7

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT5,T1,T2
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T1,T2
0 1 - Covered T3,T25,T7
0 0 1 Covered T3,T25,T7
0 0 0 Covered T5,T1,T2


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T1,T2
0 1 - Covered T3,T25,T7
0 0 1 Covered T3,T25,T7
0 0 0 Covered T5,T1,T2


Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 1285383986 6797996 0 0
DstReqKnown_A 6074082 5276922 0 0
SrcAckBusyChk_A 1285383986 7632 0 0
SrcBusyKnown_A 1285383986 1283545958 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 6797996 0 0
T3 366978 17739 0 0
T4 69113 0 0 0
T6 107086 0 0 0
T7 0 64217 0 0
T9 0 52830 0 0
T10 0 93758 0 0
T14 234126 0 0 0
T15 57872 0 0 0
T16 50824 0 0 0
T17 345106 0 0 0
T25 115154 38635 0 0
T33 0 90390 0 0
T46 0 86685 0 0
T47 0 125097 0 0
T50 201206 0 0 0
T51 72576 0 0 0
T72 0 36344 0 0
T73 0 85064 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6074082 5276922 0 0
T1 486 86 0 0
T2 25810 24171 0 0
T3 7662 7262 0 0
T5 402 2 0 0
T12 527 127 0 0
T13 404 4 0 0
T14 493 93 0 0
T15 526 126 0 0
T16 406 6 0 0
T17 718 318 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 7632 0 0
T3 366978 11 0 0
T4 69113 0 0 0
T6 107086 0 0 0
T7 0 53 0 0
T9 0 64 0 0
T10 0 56 0 0
T14 234126 0 0 0
T15 57872 0 0 0
T16 50824 0 0 0
T17 345106 0 0 0
T25 115154 51 0 0
T33 0 82 0 0
T46 0 51 0 0
T47 0 74 0 0
T50 201206 0 0 0
T51 72576 0 0 0
T72 0 66 0 0
T73 0 51 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 1283545958 0 0
T1 55618 55519 0 0
T2 123679 123489 0 0
T3 366978 366972 0 0
T5 201263 201192 0 0
T12 63336 63286 0 0
T13 100929 100875 0 0
T14 234126 234049 0 0
T15 57872 57796 0 0
T16 50824 50768 0 0
T17 345106 345048 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT5,T1,T2
01Unreachable
10CoveredT3,T25,T7

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT5,T1,T2
10CoveredT3,T25,T7
11CoveredT3,T25,T7

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT5,T1,T2
01Unreachable
10CoveredT3,T25,T7

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT3,T25,T7
11CoveredT3,T25,T7

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT5,T1,T2
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T1,T2
0 1 - Covered T3,T25,T7
0 0 1 Covered T3,T25,T7
0 0 0 Covered T5,T1,T2


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T1,T2
0 1 - Covered T3,T25,T7
0 0 1 Covered T3,T25,T7
0 0 0 Covered T5,T1,T2


Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 1285383986 6643127 0 0
DstReqKnown_A 6074082 5276922 0 0
SrcAckBusyChk_A 1285383986 7565 0 0
SrcBusyKnown_A 1285383986 1283545958 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 6643127 0 0
T3 366978 17738 0 0
T4 69113 0 0 0
T6 107086 0 0 0
T7 0 63993 0 0
T9 0 58421 0 0
T10 0 114534 0 0
T14 234126 0 0 0
T15 57872 0 0 0
T16 50824 0 0 0
T17 345106 0 0 0
T25 115154 38425 0 0
T33 0 79092 0 0
T46 0 85918 0 0
T47 0 152086 0 0
T50 201206 0 0 0
T51 72576 0 0 0
T72 0 37694 0 0
T73 0 84297 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6074082 5276922 0 0
T1 486 86 0 0
T2 25810 24171 0 0
T3 7662 7262 0 0
T5 402 2 0 0
T12 527 127 0 0
T13 404 4 0 0
T14 493 93 0 0
T15 526 126 0 0
T16 406 6 0 0
T17 718 318 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 7565 0 0
T3 366978 11 0 0
T4 69113 0 0 0
T6 107086 0 0 0
T7 0 53 0 0
T9 0 71 0 0
T10 0 68 0 0
T14 234126 0 0 0
T15 57872 0 0 0
T16 50824 0 0 0
T17 345106 0 0 0
T25 115154 51 0 0
T33 0 73 0 0
T46 0 51 0 0
T47 0 90 0 0
T50 201206 0 0 0
T51 72576 0 0 0
T72 0 70 0 0
T73 0 51 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 1283545958 0 0
T1 55618 55519 0 0
T2 123679 123489 0 0
T3 366978 366972 0 0
T5 201263 201192 0 0
T12 63336 63286 0 0
T13 100929 100875 0 0
T14 234126 234049 0 0
T15 57872 57796 0 0
T16 50824 50768 0 0
T17 345106 345048 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT5,T1,T2
01Unreachable
10CoveredT3,T25,T7

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT5,T1,T2
10CoveredT3,T25,T7
11CoveredT3,T25,T7

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT5,T1,T2
01Unreachable
10CoveredT3,T25,T7

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT3,T25,T7
11CoveredT3,T25,T7

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT5,T1,T2
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T1,T2
0 1 - Covered T3,T25,T7
0 0 1 Covered T3,T25,T7
0 0 0 Covered T5,T1,T2


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T1,T2
0 1 - Covered T3,T25,T7
0 0 1 Covered T3,T25,T7
0 0 0 Covered T5,T1,T2


Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 1285383986 6692530 0 0
DstReqKnown_A 6074082 5276922 0 0
SrcAckBusyChk_A 1285383986 7659 0 0
SrcBusyKnown_A 1285383986 1283545958 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 6692530 0 0
T3 366978 17739 0 0
T4 69113 0 0 0
T6 107086 0 0 0
T7 0 63769 0 0
T9 0 45779 0 0
T10 0 117868 0 0
T14 234126 0 0 0
T15 57872 0 0 0
T16 50824 0 0 0
T17 345106 0 0 0
T25 115154 38215 0 0
T33 0 67363 0 0
T46 0 85237 0 0
T47 0 119612 0 0
T50 201206 0 0 0
T51 72576 0 0 0
T72 0 42946 0 0
T73 0 83553 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6074082 5276922 0 0
T1 486 86 0 0
T2 25810 24171 0 0
T3 7662 7262 0 0
T5 402 2 0 0
T12 527 127 0 0
T13 404 4 0 0
T14 493 93 0 0
T15 526 126 0 0
T16 406 6 0 0
T17 718 318 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 7659 0 0
T3 366978 11 0 0
T4 69113 0 0 0
T6 107086 0 0 0
T7 0 53 0 0
T9 0 56 0 0
T10 0 71 0 0
T14 234126 0 0 0
T15 57872 0 0 0
T16 50824 0 0 0
T17 345106 0 0 0
T25 115154 51 0 0
T33 0 63 0 0
T46 0 51 0 0
T47 0 72 0 0
T50 201206 0 0 0
T51 72576 0 0 0
T72 0 80 0 0
T73 0 51 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 1283545958 0 0
T1 55618 55519 0 0
T2 123679 123489 0 0
T3 366978 366972 0 0
T5 201263 201192 0 0
T12 63336 63286 0 0
T13 100929 100875 0 0
T14 234126 234049 0 0
T15 57872 57796 0 0
T16 50824 50768 0 0
T17 345106 345048 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT5,T1,T2
01Unreachable
10CoveredT3,T25,T7

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT5,T1,T2
10CoveredT3,T25,T7
11CoveredT3,T25,T7

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT5,T1,T2
01Unreachable
10CoveredT3,T25,T7

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT3,T25,T7
11CoveredT3,T25,T7

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT5,T1,T2
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T1,T2
0 1 - Covered T3,T25,T7
0 0 1 Covered T3,T25,T7
0 0 0 Covered T5,T1,T2


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T1,T2
0 1 - Covered T3,T25,T7
0 0 1 Covered T3,T25,T7
0 0 0 Covered T5,T1,T2


Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 1285383986 1068246 0 0
DstReqKnown_A 6074082 5276922 0 0
SrcAckBusyChk_A 1285383986 1451 0 0
SrcBusyKnown_A 1285383986 1283545958 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 1068246 0 0
T3 366978 14366 0 0
T4 69113 0 0 0
T6 107086 0 0 0
T7 0 2066 0 0
T9 0 4926 0 0
T10 0 11414 0 0
T14 234126 0 0 0
T15 57872 0 0 0
T16 50824 0 0 0
T17 345106 0 0 0
T25 115154 673 0 0
T33 0 6563 0 0
T46 0 1991 0 0
T47 0 4447 0 0
T50 201206 0 0 0
T51 72576 0 0 0
T72 0 3993 0 0
T73 0 1428 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6074082 5276922 0 0
T1 486 86 0 0
T2 25810 24171 0 0
T3 7662 7262 0 0
T5 402 2 0 0
T12 527 127 0 0
T13 404 4 0 0
T14 493 93 0 0
T15 526 126 0 0
T16 406 6 0 0
T17 718 318 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 1451 0 0
T3 366978 9 0 0
T4 69113 0 0 0
T6 107086 0 0 0
T7 0 2 0 0
T9 0 6 0 0
T10 0 6 0 0
T14 234126 0 0 0
T15 57872 0 0 0
T16 50824 0 0 0
T17 345106 0 0 0
T25 115154 1 0 0
T33 0 6 0 0
T46 0 1 0 0
T47 0 3 0 0
T50 201206 0 0 0
T51 72576 0 0 0
T72 0 7 0 0
T73 0 1 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 1283545958 0 0
T1 55618 55519 0 0
T2 123679 123489 0 0
T3 366978 366972 0 0
T5 201263 201192 0 0
T12 63336 63286 0 0
T13 100929 100875 0 0
T14 234126 234049 0 0
T15 57872 57796 0 0
T16 50824 50768 0 0
T17 345106 345048 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT5,T1,T2
01Unreachable
10CoveredT3,T25,T7

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT5,T1,T2
10CoveredT3,T25,T7
11CoveredT3,T25,T7

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT5,T1,T2
01Unreachable
10CoveredT3,T25,T7

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT3,T25,T7
11CoveredT3,T25,T7

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT5,T1,T2
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T1,T2
0 1 - Covered T3,T25,T7
0 0 1 Covered T3,T25,T7
0 0 0 Covered T5,T1,T2


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T1,T2
0 1 - Covered T3,T25,T7
0 0 1 Covered T3,T25,T7
0 0 0 Covered T5,T1,T2


Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 1285383986 1074034 0 0
DstReqKnown_A 6074082 5276922 0 0
SrcAckBusyChk_A 1285383986 1460 0 0
SrcBusyKnown_A 1285383986 1283545958 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 1074034 0 0
T3 366978 14360 0 0
T4 69113 0 0 0
T6 107086 0 0 0
T7 0 2046 0 0
T9 0 4866 0 0
T10 0 11053 0 0
T14 234126 0 0 0
T15 57872 0 0 0
T16 50824 0 0 0
T17 345106 0 0 0
T25 115154 663 0 0
T33 0 6324 0 0
T46 0 1953 0 0
T47 0 4310 0 0
T50 201206 0 0 0
T51 72576 0 0 0
T72 0 3740 0 0
T73 0 1389 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6074082 5276922 0 0
T1 486 86 0 0
T2 25810 24171 0 0
T3 7662 7262 0 0
T5 402 2 0 0
T12 527 127 0 0
T13 404 4 0 0
T14 493 93 0 0
T15 526 126 0 0
T16 406 6 0 0
T17 718 318 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 1460 0 0
T3 366978 9 0 0
T4 69113 0 0 0
T6 107086 0 0 0
T7 0 2 0 0
T9 0 6 0 0
T10 0 6 0 0
T14 234126 0 0 0
T15 57872 0 0 0
T16 50824 0 0 0
T17 345106 0 0 0
T25 115154 1 0 0
T33 0 6 0 0
T46 0 1 0 0
T47 0 3 0 0
T50 201206 0 0 0
T51 72576 0 0 0
T72 0 7 0 0
T73 0 1 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 1283545958 0 0
T1 55618 55519 0 0
T2 123679 123489 0 0
T3 366978 366972 0 0
T5 201263 201192 0 0
T12 63336 63286 0 0
T13 100929 100875 0 0
T14 234126 234049 0 0
T15 57872 57796 0 0
T16 50824 50768 0 0
T17 345106 345048 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT5,T1,T2
01Unreachable
10CoveredT3,T25,T7

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT5,T1,T2
10CoveredT3,T25,T7
11CoveredT3,T25,T7

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT5,T1,T2
01Unreachable
10CoveredT3,T25,T7

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT3,T25,T7
11CoveredT3,T25,T7

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT5,T1,T2
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T1,T2
0 1 - Covered T3,T25,T7
0 0 1 Covered T3,T25,T7
0 0 0 Covered T5,T1,T2


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T1,T2
0 1 - Covered T3,T25,T7
0 0 1 Covered T3,T25,T7
0 0 0 Covered T5,T1,T2


Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 1285383986 1035562 0 0
DstReqKnown_A 6074082 5276922 0 0
SrcAckBusyChk_A 1285383986 1433 0 0
SrcBusyKnown_A 1285383986 1283545958 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 1035562 0 0
T3 366978 14360 0 0
T4 69113 0 0 0
T6 107086 0 0 0
T7 0 2026 0 0
T9 0 4806 0 0
T10 0 10760 0 0
T14 234126 0 0 0
T15 57872 0 0 0
T16 50824 0 0 0
T17 345106 0 0 0
T25 115154 653 0 0
T33 0 6103 0 0
T46 0 1914 0 0
T47 0 4149 0 0
T50 201206 0 0 0
T51 72576 0 0 0
T72 0 3493 0 0
T73 0 1352 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6074082 5276922 0 0
T1 486 86 0 0
T2 25810 24171 0 0
T3 7662 7262 0 0
T5 402 2 0 0
T12 527 127 0 0
T13 404 4 0 0
T14 493 93 0 0
T15 526 126 0 0
T16 406 6 0 0
T17 718 318 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 1433 0 0
T3 366978 9 0 0
T4 69113 0 0 0
T6 107086 0 0 0
T7 0 2 0 0
T9 0 6 0 0
T10 0 6 0 0
T14 234126 0 0 0
T15 57872 0 0 0
T16 50824 0 0 0
T17 345106 0 0 0
T25 115154 1 0 0
T33 0 6 0 0
T46 0 1 0 0
T47 0 3 0 0
T50 201206 0 0 0
T51 72576 0 0 0
T72 0 7 0 0
T73 0 1 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 1283545958 0 0
T1 55618 55519 0 0
T2 123679 123489 0 0
T3 366978 366972 0 0
T5 201263 201192 0 0
T12 63336 63286 0 0
T13 100929 100875 0 0
T14 234126 234049 0 0
T15 57872 57796 0 0
T16 50824 50768 0 0
T17 345106 345048 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT5,T1,T2
01Unreachable
10CoveredT3,T25,T7

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT5,T1,T2
10CoveredT3,T25,T7
11CoveredT3,T25,T7

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT5,T1,T2
01Unreachable
10CoveredT3,T25,T7

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT3,T25,T7
11CoveredT3,T25,T7

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT5,T1,T2
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T1,T2
0 1 - Covered T3,T25,T7
0 0 1 Covered T3,T25,T7
0 0 0 Covered T5,T1,T2


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T1,T2
0 1 - Covered T3,T25,T7
0 0 1 Covered T3,T25,T7
0 0 0 Covered T5,T1,T2


Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 1285383986 1044996 0 0
DstReqKnown_A 6074082 5276922 0 0
SrcAckBusyChk_A 1285383986 1434 0 0
SrcBusyKnown_A 1285383986 1283545958 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 1044996 0 0
T3 366978 14361 0 0
T4 69113 0 0 0
T6 107086 0 0 0
T7 0 2006 0 0
T9 0 4746 0 0
T10 0 10460 0 0
T14 234126 0 0 0
T15 57872 0 0 0
T16 50824 0 0 0
T17 345106 0 0 0
T25 115154 643 0 0
T33 0 5898 0 0
T46 0 1882 0 0
T47 0 3975 0 0
T50 201206 0 0 0
T51 72576 0 0 0
T72 0 3298 0 0
T73 0 1314 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6074082 5276922 0 0
T1 486 86 0 0
T2 25810 24171 0 0
T3 7662 7262 0 0
T5 402 2 0 0
T12 527 127 0 0
T13 404 4 0 0
T14 493 93 0 0
T15 526 126 0 0
T16 406 6 0 0
T17 718 318 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 1434 0 0
T3 366978 9 0 0
T4 69113 0 0 0
T6 107086 0 0 0
T7 0 2 0 0
T9 0 6 0 0
T10 0 6 0 0
T14 234126 0 0 0
T15 57872 0 0 0
T16 50824 0 0 0
T17 345106 0 0 0
T25 115154 1 0 0
T33 0 6 0 0
T46 0 1 0 0
T47 0 3 0 0
T50 201206 0 0 0
T51 72576 0 0 0
T72 0 7 0 0
T73 0 1 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 1283545958 0 0
T1 55618 55519 0 0
T2 123679 123489 0 0
T3 366978 366972 0 0
T5 201263 201192 0 0
T12 63336 63286 0 0
T13 100929 100875 0 0
T14 234126 234049 0 0
T15 57872 57796 0 0
T16 50824 50768 0 0
T17 345106 345048 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT5,T1,T2
01Unreachable
10CoveredT2,T3,T25

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT5,T1,T2
10CoveredT2,T3,T25
11CoveredT2,T3,T25

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT5,T1,T2
01Unreachable
10CoveredT2,T3,T25

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT2,T3,T25
11CoveredT2,T3,T25

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT5,T1,T2
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T1,T2
0 1 - Covered T2,T3,T25
0 0 1 Covered T2,T3,T25
0 0 0 Covered T5,T1,T2


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T1,T2
0 1 - Covered T2,T3,T25
0 0 1 Covered T2,T3,T25
0 0 0 Covered T5,T1,T2


Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 1285383986 7546015 0 0
DstReqKnown_A 6074082 5276922 0 0
SrcAckBusyChk_A 1285383986 8336 0 0
SrcBusyKnown_A 1285383986 1283545958 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 7546015 0 0
T2 123679 12962 0 0
T3 366978 17709 0 0
T4 69113 0 0 0
T6 0 949 0 0
T7 0 63496 0 0
T9 0 51086 0 0
T10 0 123005 0 0
T11 0 2487 0 0
T12 63336 0 0 0
T13 100929 0 0 0
T14 234126 0 0 0
T15 57872 0 0 0
T16 50824 0 0 0
T17 345106 0 0 0
T25 115154 38941 0 0
T32 0 4326 0 0
T43 0 2810 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6074082 5276922 0 0
T1 486 86 0 0
T2 25810 24171 0 0
T3 7662 7262 0 0
T5 402 2 0 0
T12 527 127 0 0
T13 404 4 0 0
T14 493 93 0 0
T15 526 126 0 0
T16 406 6 0 0
T17 718 318 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 8336 0 0
T2 123679 8 0 0
T3 366978 11 0 0
T4 69113 0 0 0
T6 0 2 0 0
T7 0 52 0 0
T9 0 61 0 0
T10 0 71 0 0
T11 0 5 0 0
T12 63336 0 0 0
T13 100929 0 0 0
T14 234126 0 0 0
T15 57872 0 0 0
T16 50824 0 0 0
T17 345106 0 0 0
T25 115154 51 0 0
T32 0 10 0 0
T43 0 6 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 1283545958 0 0
T1 55618 55519 0 0
T2 123679 123489 0 0
T3 366978 366972 0 0
T5 201263 201192 0 0
T12 63336 63286 0 0
T13 100929 100875 0 0
T14 234126 234049 0 0
T15 57872 57796 0 0
T16 50824 50768 0 0
T17 345106 345048 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT5,T1,T2
01Unreachable
10CoveredT2,T3,T25

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT5,T1,T2
10CoveredT2,T3,T25
11CoveredT2,T3,T25

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT5,T1,T2
01Unreachable
10CoveredT2,T3,T25

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT2,T3,T25
11CoveredT2,T3,T25

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT5,T1,T2
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T1,T2
0 1 - Covered T2,T3,T25
0 0 1 Covered T2,T3,T25
0 0 0 Covered T5,T1,T2


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T1,T2
0 1 - Covered T2,T3,T25
0 0 1 Covered T2,T3,T25
0 0 0 Covered T5,T1,T2


Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 1285383986 7375712 0 0
DstReqKnown_A 6074082 5276922 0 0
SrcAckBusyChk_A 1285383986 8209 0 0
SrcBusyKnown_A 1285383986 1283545958 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 7375712 0 0
T2 123679 12946 0 0
T3 366978 17703 0 0
T4 69113 0 0 0
T6 0 928 0 0
T7 0 64311 0 0
T9 0 52922 0 0
T10 0 94225 0 0
T11 0 499 0 0
T12 63336 0 0 0
T13 100929 0 0 0
T14 234126 0 0 0
T15 57872 0 0 0
T16 50824 0 0 0
T17 345106 0 0 0
T25 115154 38731 0 0
T32 0 4306 0 0
T43 0 2393 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6074082 5276922 0 0
T1 486 86 0 0
T2 25810 24171 0 0
T3 7662 7262 0 0
T5 402 2 0 0
T12 527 127 0 0
T13 404 4 0 0
T14 493 93 0 0
T15 526 126 0 0
T16 406 6 0 0
T17 718 318 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 8209 0 0
T2 123679 8 0 0
T3 366978 11 0 0
T4 69113 0 0 0
T6 0 2 0 0
T7 0 53 0 0
T9 0 64 0 0
T10 0 56 0 0
T11 0 1 0 0
T12 63336 0 0 0
T13 100929 0 0 0
T14 234126 0 0 0
T15 57872 0 0 0
T16 50824 0 0 0
T17 345106 0 0 0
T25 115154 51 0 0
T32 0 10 0 0
T43 0 5 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 1283545958 0 0
T1 55618 55519 0 0
T2 123679 123489 0 0
T3 366978 366972 0 0
T5 201263 201192 0 0
T12 63336 63286 0 0
T13 100929 100875 0 0
T14 234126 234049 0 0
T15 57872 57796 0 0
T16 50824 50768 0 0
T17 345106 345048 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT5,T1,T2
01Unreachable
10CoveredT2,T3,T25

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT5,T1,T2
10CoveredT2,T3,T25
11CoveredT2,T3,T25

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT5,T1,T2
01Unreachable
10CoveredT2,T3,T25

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT2,T3,T25
11CoveredT2,T3,T25

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT5,T1,T2
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T1,T2
0 1 - Covered T2,T3,T25
0 0 1 Covered T2,T3,T25
0 0 0 Covered T5,T1,T2


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T1,T2
0 1 - Covered T2,T3,T25
0 0 1 Covered T2,T3,T25
0 0 0 Covered T5,T1,T2


Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 1285383986 7198920 0 0
DstReqKnown_A 6074082 5276922 0 0
SrcAckBusyChk_A 1285383986 8122 0 0
SrcBusyKnown_A 1285383986 1283545958 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 7198920 0 0
T2 123679 12930 0 0
T3 366978 17703 0 0
T4 69113 0 0 0
T6 0 915 0 0
T7 0 64087 0 0
T9 0 58527 0 0
T10 0 115031 0 0
T11 0 497 0 0
T12 63336 0 0 0
T13 100929 0 0 0
T14 234126 0 0 0
T15 57872 0 0 0
T16 50824 0 0 0
T17 345106 0 0 0
T25 115154 38521 0 0
T32 0 4286 0 0
T43 0 2338 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6074082 5276922 0 0
T1 486 86 0 0
T2 25810 24171 0 0
T3 7662 7262 0 0
T5 402 2 0 0
T12 527 127 0 0
T13 404 4 0 0
T14 493 93 0 0
T15 526 126 0 0
T16 406 6 0 0
T17 718 318 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 8122 0 0
T2 123679 8 0 0
T3 366978 11 0 0
T4 69113 0 0 0
T6 0 2 0 0
T7 0 53 0 0
T9 0 71 0 0
T10 0 68 0 0
T11 0 1 0 0
T12 63336 0 0 0
T13 100929 0 0 0
T14 234126 0 0 0
T15 57872 0 0 0
T16 50824 0 0 0
T17 345106 0 0 0
T25 115154 51 0 0
T32 0 10 0 0
T43 0 5 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 1283545958 0 0
T1 55618 55519 0 0
T2 123679 123489 0 0
T3 366978 366972 0 0
T5 201263 201192 0 0
T12 63336 63286 0 0
T13 100929 100875 0 0
T14 234126 234049 0 0
T15 57872 57796 0 0
T16 50824 50768 0 0
T17 345106 345048 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT5,T1,T2
01Unreachable
10CoveredT2,T3,T25

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT5,T1,T2
10CoveredT2,T3,T25
11CoveredT2,T3,T25

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT5,T1,T2
01Unreachable
10CoveredT2,T3,T25

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT2,T3,T25
11CoveredT2,T3,T25

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT5,T1,T2
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T1,T2
0 1 - Covered T2,T3,T25
0 0 1 Covered T2,T3,T25
0 0 0 Covered T5,T1,T2


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T1,T2
0 1 - Covered T2,T3,T25
0 0 1 Covered T2,T3,T25
0 0 0 Covered T5,T1,T2


Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 1285383986 7268024 0 0
DstReqKnown_A 6074082 5276922 0 0
SrcAckBusyChk_A 1285383986 8239 0 0
SrcBusyKnown_A 1285383986 1283545958 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 7268024 0 0
T2 123679 12914 0 0
T3 366978 17703 0 0
T4 69113 0 0 0
T6 0 904 0 0
T7 0 63863 0 0
T9 0 45855 0 0
T10 0 118373 0 0
T11 0 495 0 0
T12 63336 0 0 0
T13 100929 0 0 0
T14 234126 0 0 0
T15 57872 0 0 0
T16 50824 0 0 0
T17 345106 0 0 0
T25 115154 38311 0 0
T32 0 4266 0 0
T43 0 2298 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6074082 5276922 0 0
T1 486 86 0 0
T2 25810 24171 0 0
T3 7662 7262 0 0
T5 402 2 0 0
T12 527 127 0 0
T13 404 4 0 0
T14 493 93 0 0
T15 526 126 0 0
T16 406 6 0 0
T17 718 318 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 8239 0 0
T2 123679 8 0 0
T3 366978 11 0 0
T4 69113 0 0 0
T6 0 2 0 0
T7 0 53 0 0
T9 0 56 0 0
T10 0 71 0 0
T11 0 1 0 0
T12 63336 0 0 0
T13 100929 0 0 0
T14 234126 0 0 0
T15 57872 0 0 0
T16 50824 0 0 0
T17 345106 0 0 0
T25 115154 51 0 0
T32 0 10 0 0
T43 0 5 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 1283545958 0 0
T1 55618 55519 0 0
T2 123679 123489 0 0
T3 366978 366972 0 0
T5 201263 201192 0 0
T12 63336 63286 0 0
T13 100929 100875 0 0
T14 234126 234049 0 0
T15 57872 57796 0 0
T16 50824 50768 0 0
T17 345106 345048 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT5,T1,T2
01Unreachable
10CoveredT2,T3,T25

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT5,T1,T2
10CoveredT2,T3,T25
11CoveredT2,T3,T25

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT5,T1,T2
01Unreachable
10CoveredT2,T3,T25

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT2,T3,T25
11CoveredT2,T3,T25

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT5,T1,T2
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T1,T2
0 1 - Covered T2,T3,T25
0 0 1 Covered T2,T3,T25
0 0 0 Covered T5,T1,T2


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T1,T2
0 1 - Covered T2,T3,T25
0 0 1 Covered T2,T3,T25
0 0 0 Covered T5,T1,T2


Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 1285383986 1657585 0 0
DstReqKnown_A 6074082 5276922 0 0
SrcAckBusyChk_A 1285383986 2074 0 0
SrcBusyKnown_A 1285383986 1283545958 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 1657585 0 0
T2 123679 12898 0 0
T3 366978 14330 0 0
T4 69113 0 0 0
T6 0 889 0 0
T7 0 2058 0 0
T9 0 4902 0 0
T10 0 11267 0 0
T11 0 2471 0 0
T12 63336 0 0 0
T13 100929 0 0 0
T14 234126 0 0 0
T15 57872 0 0 0
T16 50824 0 0 0
T17 345106 0 0 0
T25 115154 669 0 0
T32 0 4246 0 0
T43 0 2595 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6074082 5276922 0 0
T1 486 86 0 0
T2 25810 24171 0 0
T3 7662 7262 0 0
T5 402 2 0 0
T12 527 127 0 0
T13 404 4 0 0
T14 493 93 0 0
T15 526 126 0 0
T16 406 6 0 0
T17 718 318 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 2074 0 0
T2 123679 8 0 0
T3 366978 9 0 0
T4 69113 0 0 0
T6 0 2 0 0
T7 0 2 0 0
T9 0 6 0 0
T10 0 6 0 0
T11 0 5 0 0
T12 63336 0 0 0
T13 100929 0 0 0
T14 234126 0 0 0
T15 57872 0 0 0
T16 50824 0 0 0
T17 345106 0 0 0
T25 115154 1 0 0
T32 0 10 0 0
T43 0 6 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 1283545958 0 0
T1 55618 55519 0 0
T2 123679 123489 0 0
T3 366978 366972 0 0
T5 201263 201192 0 0
T12 63336 63286 0 0
T13 100929 100875 0 0
T14 234126 234049 0 0
T15 57872 57796 0 0
T16 50824 50768 0 0
T17 345106 345048 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT5,T1,T2
01Unreachable
10CoveredT2,T3,T25

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT5,T1,T2
10CoveredT2,T3,T25
11CoveredT2,T3,T25

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT5,T1,T2
01Unreachable
10CoveredT2,T3,T25

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT2,T3,T25
11CoveredT2,T3,T25

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT5,T1,T2
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T1,T2
0 1 - Covered T2,T3,T25
0 0 1 Covered T2,T3,T25
0 0 0 Covered T5,T1,T2


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T1,T2
0 1 - Covered T2,T3,T25
0 0 1 Covered T2,T3,T25
0 0 0 Covered T5,T1,T2


Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 1285383986 1635796 0 0
DstReqKnown_A 6074082 5276922 0 0
SrcAckBusyChk_A 1285383986 2047 0 0
SrcBusyKnown_A 1285383986 1283545958 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 1635796 0 0
T2 123679 12882 0 0
T3 366978 14324 0 0
T4 69113 0 0 0
T6 0 882 0 0
T7 0 2038 0 0
T9 0 4842 0 0
T10 0 10927 0 0
T11 0 491 0 0
T12 63336 0 0 0
T13 100929 0 0 0
T14 234126 0 0 0
T15 57872 0 0 0
T16 50824 0 0 0
T17 345106 0 0 0
T25 115154 659 0 0
T32 0 4226 0 0
T43 0 2181 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6074082 5276922 0 0
T1 486 86 0 0
T2 25810 24171 0 0
T3 7662 7262 0 0
T5 402 2 0 0
T12 527 127 0 0
T13 404 4 0 0
T14 493 93 0 0
T15 526 126 0 0
T16 406 6 0 0
T17 718 318 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 2047 0 0
T2 123679 8 0 0
T3 366978 9 0 0
T4 69113 0 0 0
T6 0 2 0 0
T7 0 2 0 0
T9 0 6 0 0
T10 0 6 0 0
T11 0 1 0 0
T12 63336 0 0 0
T13 100929 0 0 0
T14 234126 0 0 0
T15 57872 0 0 0
T16 50824 0 0 0
T17 345106 0 0 0
T25 115154 1 0 0
T32 0 10 0 0
T43 0 5 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 1283545958 0 0
T1 55618 55519 0 0
T2 123679 123489 0 0
T3 366978 366972 0 0
T5 201263 201192 0 0
T12 63336 63286 0 0
T13 100929 100875 0 0
T14 234126 234049 0 0
T15 57872 57796 0 0
T16 50824 50768 0 0
T17 345106 345048 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT5,T1,T2
01Unreachable
10CoveredT2,T3,T25

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT5,T1,T2
10CoveredT2,T3,T25
11CoveredT2,T3,T25

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT5,T1,T2
01Unreachable
10CoveredT2,T3,T25

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT2,T3,T25
11CoveredT2,T3,T25

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT5,T1,T2
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T1,T2
0 1 - Covered T2,T3,T25
0 0 1 Covered T2,T3,T25
0 0 0 Covered T5,T1,T2


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T1,T2
0 1 - Covered T2,T3,T25
0 0 1 Covered T2,T3,T25
0 0 0 Covered T5,T1,T2


Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 1285383986 1567690 0 0
DstReqKnown_A 6074082 5276922 0 0
SrcAckBusyChk_A 1285383986 2019 0 0
SrcBusyKnown_A 1285383986 1283545958 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 1567690 0 0
T2 123679 12866 0 0
T3 366978 14324 0 0
T4 69113 0 0 0
T6 0 866 0 0
T7 0 2018 0 0
T9 0 4782 0 0
T10 0 10628 0 0
T11 0 489 0 0
T12 63336 0 0 0
T13 100929 0 0 0
T14 234126 0 0 0
T15 57872 0 0 0
T16 50824 0 0 0
T17 345106 0 0 0
T25 115154 649 0 0
T32 0 4206 0 0
T43 0 2139 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6074082 5276922 0 0
T1 486 86 0 0
T2 25810 24171 0 0
T3 7662 7262 0 0
T5 402 2 0 0
T12 527 127 0 0
T13 404 4 0 0
T14 493 93 0 0
T15 526 126 0 0
T16 406 6 0 0
T17 718 318 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 2019 0 0
T2 123679 8 0 0
T3 366978 9 0 0
T4 69113 0 0 0
T6 0 2 0 0
T7 0 2 0 0
T9 0 6 0 0
T10 0 6 0 0
T11 0 1 0 0
T12 63336 0 0 0
T13 100929 0 0 0
T14 234126 0 0 0
T15 57872 0 0 0
T16 50824 0 0 0
T17 345106 0 0 0
T25 115154 1 0 0
T32 0 10 0 0
T43 0 5 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 1283545958 0 0
T1 55618 55519 0 0
T2 123679 123489 0 0
T3 366978 366972 0 0
T5 201263 201192 0 0
T12 63336 63286 0 0
T13 100929 100875 0 0
T14 234126 234049 0 0
T15 57872 57796 0 0
T16 50824 50768 0 0
T17 345106 345048 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT5,T1,T2
01Unreachable
10CoveredT2,T3,T25

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT5,T1,T2
10CoveredT2,T3,T25
11CoveredT2,T3,T25

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT5,T1,T2
01Unreachable
10CoveredT2,T3,T25

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT2,T3,T25
11CoveredT2,T3,T25

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT5,T1,T2
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T1,T2
0 1 - Covered T2,T3,T25
0 0 1 Covered T2,T3,T25
0 0 0 Covered T5,T1,T2


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T1,T2
0 1 - Covered T2,T3,T25
0 0 1 Covered T2,T3,T25
0 0 0 Covered T5,T1,T2


Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 1285383986 1565048 0 0
DstReqKnown_A 6074082 5276922 0 0
SrcAckBusyChk_A 1285383986 2016 0 0
SrcBusyKnown_A 1285383986 1283545958 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 1565048 0 0
T2 123679 12850 0 0
T3 366978 14325 0 0
T4 69113 0 0 0
T6 0 861 0 0
T7 0 1998 0 0
T9 0 4722 0 0
T10 0 10306 0 0
T11 0 487 0 0
T12 63336 0 0 0
T13 100929 0 0 0
T14 234126 0 0 0
T15 57872 0 0 0
T16 50824 0 0 0
T17 345106 0 0 0
T25 115154 639 0 0
T32 0 4186 0 0
T43 0 2086 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6074082 5276922 0 0
T1 486 86 0 0
T2 25810 24171 0 0
T3 7662 7262 0 0
T5 402 2 0 0
T12 527 127 0 0
T13 404 4 0 0
T14 493 93 0 0
T15 526 126 0 0
T16 406 6 0 0
T17 718 318 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 2016 0 0
T2 123679 8 0 0
T3 366978 9 0 0
T4 69113 0 0 0
T6 0 2 0 0
T7 0 2 0 0
T9 0 6 0 0
T10 0 6 0 0
T11 0 1 0 0
T12 63336 0 0 0
T13 100929 0 0 0
T14 234126 0 0 0
T15 57872 0 0 0
T16 50824 0 0 0
T17 345106 0 0 0
T25 115154 1 0 0
T32 0 10 0 0
T43 0 5 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 1283545958 0 0
T1 55618 55519 0 0
T2 123679 123489 0 0
T3 366978 366972 0 0
T5 201263 201192 0 0
T12 63336 63286 0 0
T13 100929 100875 0 0
T14 234126 234049 0 0
T15 57872 57796 0 0
T16 50824 50768 0 0
T17 345106 345048 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT5,T1,T2
01Unreachable
10CoveredT2,T3,T25

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT5,T1,T2
10CoveredT2,T3,T25
11CoveredT2,T3,T25

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT5,T1,T2
01Unreachable
10CoveredT2,T3,T25

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT2,T3,T25
11CoveredT2,T3,T25

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT5,T1,T2
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T1,T2
0 1 - Covered T2,T3,T25
0 0 1 Covered T2,T3,T25
0 0 0 Covered T5,T1,T2


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T1,T2
0 1 - Covered T2,T3,T25
0 0 1 Covered T2,T3,T25
0 0 0 Covered T5,T1,T2


Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 1285383986 1640140 0 0
DstReqKnown_A 6074082 5276922 0 0
SrcAckBusyChk_A 1285383986 2095 0 0
SrcBusyKnown_A 1285383986 1283545958 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 1640140 0 0
T2 123679 12834 0 0
T3 366978 14312 0 0
T4 69113 0 0 0
T6 0 842 0 0
T7 0 2054 0 0
T9 0 4890 0 0
T10 0 11210 0 0
T11 0 2455 0 0
T12 63336 0 0 0
T13 100929 0 0 0
T14 234126 0 0 0
T15 57872 0 0 0
T16 50824 0 0 0
T17 345106 0 0 0
T25 115154 667 0 0
T32 0 4166 0 0
T43 0 2375 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6074082 5276922 0 0
T1 486 86 0 0
T2 25810 24171 0 0
T3 7662 7262 0 0
T5 402 2 0 0
T12 527 127 0 0
T13 404 4 0 0
T14 493 93 0 0
T15 526 126 0 0
T16 406 6 0 0
T17 718 318 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 2095 0 0
T2 123679 8 0 0
T3 366978 9 0 0
T4 69113 0 0 0
T6 0 2 0 0
T7 0 2 0 0
T9 0 6 0 0
T10 0 6 0 0
T11 0 5 0 0
T12 63336 0 0 0
T13 100929 0 0 0
T14 234126 0 0 0
T15 57872 0 0 0
T16 50824 0 0 0
T17 345106 0 0 0
T25 115154 1 0 0
T32 0 10 0 0
T43 0 6 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 1283545958 0 0
T1 55618 55519 0 0
T2 123679 123489 0 0
T3 366978 366972 0 0
T5 201263 201192 0 0
T12 63336 63286 0 0
T13 100929 100875 0 0
T14 234126 234049 0 0
T15 57872 57796 0 0
T16 50824 50768 0 0
T17 345106 345048 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT5,T1,T2
01Unreachable
10CoveredT2,T3,T25

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT5,T1,T2
10CoveredT2,T3,T25
11CoveredT2,T3,T25

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT5,T1,T2
01Unreachable
10CoveredT2,T3,T25

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT2,T3,T25
11CoveredT2,T3,T25

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT5,T1,T2
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T1,T2
0 1 - Covered T2,T3,T25
0 0 1 Covered T2,T3,T25
0 0 0 Covered T5,T1,T2


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T1,T2
0 1 - Covered T2,T3,T25
0 0 1 Covered T2,T3,T25
0 0 0 Covered T5,T1,T2


Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 1285383986 1592404 0 0
DstReqKnown_A 6074082 5276922 0 0
SrcAckBusyChk_A 1285383986 2038 0 0
SrcBusyKnown_A 1285383986 1283545958 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 1592404 0 0
T2 123679 12818 0 0
T3 366978 14306 0 0
T4 69113 0 0 0
T6 0 827 0 0
T7 0 2034 0 0
T9 0 4830 0 0
T10 0 10880 0 0
T11 0 483 0 0
T12 63336 0 0 0
T13 100929 0 0 0
T14 234126 0 0 0
T15 57872 0 0 0
T16 50824 0 0 0
T17 345106 0 0 0
T25 115154 657 0 0
T32 0 4146 0 0
T43 0 1982 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6074082 5276922 0 0
T1 486 86 0 0
T2 25810 24171 0 0
T3 7662 7262 0 0
T5 402 2 0 0
T12 527 127 0 0
T13 404 4 0 0
T14 493 93 0 0
T15 526 126 0 0
T16 406 6 0 0
T17 718 318 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 2038 0 0
T2 123679 8 0 0
T3 366978 9 0 0
T4 69113 0 0 0
T6 0 2 0 0
T7 0 2 0 0
T9 0 6 0 0
T10 0 6 0 0
T11 0 1 0 0
T12 63336 0 0 0
T13 100929 0 0 0
T14 234126 0 0 0
T15 57872 0 0 0
T16 50824 0 0 0
T17 345106 0 0 0
T25 115154 1 0 0
T32 0 10 0 0
T43 0 5 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 1283545958 0 0
T1 55618 55519 0 0
T2 123679 123489 0 0
T3 366978 366972 0 0
T5 201263 201192 0 0
T12 63336 63286 0 0
T13 100929 100875 0 0
T14 234126 234049 0 0
T15 57872 57796 0 0
T16 50824 50768 0 0
T17 345106 345048 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT5,T1,T2
01Unreachable
10CoveredT2,T3,T25

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT5,T1,T2
10CoveredT2,T3,T25
11CoveredT2,T3,T25

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT5,T1,T2
01Unreachable
10CoveredT2,T3,T25

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT2,T3,T25
11CoveredT2,T3,T25

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT5,T1,T2
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T1,T2
0 1 - Covered T2,T3,T25
0 0 1 Covered T2,T3,T25
0 0 0 Covered T5,T1,T2


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T1,T2
0 1 - Covered T2,T3,T25
0 0 1 Covered T2,T3,T25
0 0 0 Covered T5,T1,T2


Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 1285383986 1579265 0 0
DstReqKnown_A 6074082 5276922 0 0
SrcAckBusyChk_A 1285383986 2031 0 0
SrcBusyKnown_A 1285383986 1283545958 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 1579265 0 0
T2 123679 12802 0 0
T3 366978 14306 0 0
T4 69113 0 0 0
T6 0 812 0 0
T7 0 2014 0 0
T9 0 4770 0 0
T10 0 10572 0 0
T11 0 481 0 0
T12 63336 0 0 0
T13 100929 0 0 0
T14 234126 0 0 0
T15 57872 0 0 0
T16 50824 0 0 0
T17 345106 0 0 0
T25 115154 647 0 0
T32 0 4126 0 0
T43 0 1944 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6074082 5276922 0 0
T1 486 86 0 0
T2 25810 24171 0 0
T3 7662 7262 0 0
T5 402 2 0 0
T12 527 127 0 0
T13 404 4 0 0
T14 493 93 0 0
T15 526 126 0 0
T16 406 6 0 0
T17 718 318 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 2031 0 0
T2 123679 8 0 0
T3 366978 9 0 0
T4 69113 0 0 0
T6 0 2 0 0
T7 0 2 0 0
T9 0 6 0 0
T10 0 6 0 0
T11 0 1 0 0
T12 63336 0 0 0
T13 100929 0 0 0
T14 234126 0 0 0
T15 57872 0 0 0
T16 50824 0 0 0
T17 345106 0 0 0
T25 115154 1 0 0
T32 0 10 0 0
T43 0 5 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 1283545958 0 0
T1 55618 55519 0 0
T2 123679 123489 0 0
T3 366978 366972 0 0
T5 201263 201192 0 0
T12 63336 63286 0 0
T13 100929 100875 0 0
T14 234126 234049 0 0
T15 57872 57796 0 0
T16 50824 50768 0 0
T17 345106 345048 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT5,T1,T2
01Unreachable
10CoveredT2,T3,T25

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT5,T1,T2
10CoveredT2,T3,T25
11CoveredT2,T3,T25

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT5,T1,T2
01Unreachable
10CoveredT2,T3,T25

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT2,T3,T25
11CoveredT2,T3,T25

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT5,T1,T2
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T1,T2
0 1 - Covered T2,T3,T25
0 0 1 Covered T2,T3,T25
0 0 0 Covered T5,T1,T2


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T1,T2
0 1 - Covered T2,T3,T25
0 0 1 Covered T2,T3,T25
0 0 0 Covered T5,T1,T2


Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 1285383986 1541728 0 0
DstReqKnown_A 6074082 5276922 0 0
SrcAckBusyChk_A 1285383986 2009 0 0
SrcBusyKnown_A 1285383986 1283545958 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 1541728 0 0
T2 123679 12786 0 0
T3 366978 14307 0 0
T4 69113 0 0 0
T6 0 796 0 0
T7 0 1994 0 0
T9 0 4710 0 0
T10 0 10237 0 0
T11 0 479 0 0
T12 63336 0 0 0
T13 100929 0 0 0
T14 234126 0 0 0
T15 57872 0 0 0
T16 50824 0 0 0
T17 345106 0 0 0
T25 115154 637 0 0
T32 0 4106 0 0
T43 0 1894 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6074082 5276922 0 0
T1 486 86 0 0
T2 25810 24171 0 0
T3 7662 7262 0 0
T5 402 2 0 0
T12 527 127 0 0
T13 404 4 0 0
T14 493 93 0 0
T15 526 126 0 0
T16 406 6 0 0
T17 718 318 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 2009 0 0
T2 123679 8 0 0
T3 366978 9 0 0
T4 69113 0 0 0
T6 0 2 0 0
T7 0 2 0 0
T9 0 6 0 0
T10 0 6 0 0
T11 0 1 0 0
T12 63336 0 0 0
T13 100929 0 0 0
T14 234126 0 0 0
T15 57872 0 0 0
T16 50824 0 0 0
T17 345106 0 0 0
T25 115154 1 0 0
T32 0 10 0 0
T43 0 5 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 1283545958 0 0
T1 55618 55519 0 0
T2 123679 123489 0 0
T3 366978 366972 0 0
T5 201263 201192 0 0
T12 63336 63286 0 0
T13 100929 100875 0 0
T14 234126 234049 0 0
T15 57872 57796 0 0
T16 50824 50768 0 0
T17 345106 345048 0 0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc
TotalCoveredPercent
Conditions131292.31
Logical131292.31
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT5,T1,T2
01Unreachable
10CoveredT3,T8,T11

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT5,T1,T2
10CoveredT3,T8,T11
11CoveredT3,T8,T11

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---
-1--2-StatusTests
0-CoveredT3,T8,T11
1-CoveredT3,T8,T11

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT5,T1,T2
01Unreachable
10CoveredT3,T8,T11

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT3,T8,T11
11CoveredT3,T8,T11

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT5,T1,T2
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T1,T2
0 1 - Covered T3,T8,T11
0 0 1 Covered T3,T8,T11
0 0 0 Covered T5,T1,T2


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T1,T2
0 1 - Covered T3,T8,T11
0 0 1 Covered T3,T8,T11
0 0 0 Covered T5,T1,T2


Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 1285383986 823772 0 0
DstReqKnown_A 6074082 5276922 0 0
SrcAckBusyChk_A 1285383986 1186 0 0
SrcBusyKnown_A 1285383986 1283545958 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 823772 0 0
T3 366978 5751 0 0
T4 69113 0 0 0
T6 107086 0 0 0
T8 0 224 0 0
T11 0 995 0 0
T14 234126 0 0 0
T15 57872 0 0 0
T16 50824 0 0 0
T17 345106 0 0 0
T25 115154 0 0 0
T31 0 3963 0 0
T50 201206 0 0 0
T51 72576 0 0 0
T57 0 3757 0 0
T74 0 3801 0 0
T75 0 694 0 0
T76 0 3969 0 0
T77 0 626 0 0
T78 0 953 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6074082 5276922 0 0
T1 486 86 0 0
T2 25810 24171 0 0
T3 7662 7262 0 0
T5 402 2 0 0
T12 527 127 0 0
T13 404 4 0 0
T14 493 93 0 0
T15 526 126 0 0
T16 406 6 0 0
T17 718 318 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 1186 0 0
T3 366978 4 0 0
T4 69113 0 0 0
T6 107086 0 0 0
T8 0 2 0 0
T11 0 2 0 0
T14 234126 0 0 0
T15 57872 0 0 0
T16 50824 0 0 0
T17 345106 0 0 0
T25 115154 0 0 0
T31 0 2 0 0
T50 201206 0 0 0
T51 72576 0 0 0
T57 0 2 0 0
T74 0 2 0 0
T75 0 2 0 0
T76 0 2 0 0
T77 0 2 0 0
T78 0 2 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285383986 1283545958 0 0
T1 55618 55519 0 0
T2 123679 123489 0 0
T3 366978 366972 0 0
T5 201263 201192 0 0
T12 63336 63286 0 0
T13 100929 100875 0 0
T14 234126 234049 0 0
T15 57872 57796 0 0
T16 50824 50768 0 0
T17 345106 345048 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%