Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.12	95.12	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	95.12	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.12	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	4	58	93.55

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	4	27	87.10	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2138

1

T3

14

T5

23

T7

13

auto[1]

642

1

T3

6

T5

5

T47

1

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2136

1

T3

14

T5

28

T7

8

auto[1]

644

1

T3

6

T7

5

T47

1

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2172

1

T3

19

T5

28

T7

8

auto[1]

608

1

T3

1

T7

5

T47

1

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2191

1

T3

11

T5

16

T7

13

auto[1]

589

1

T3

9

T5

12

T47

1

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2590

1

T3

20

T5

28

T7

13

auto[1]

190

1

T9

5

T34

4

T77

2

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2565

1

T3

20

T5

23

T7

13

auto[1]

215

1

T5

5

T9

2

T34

5

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2508

1

T3

20

T5

28

T7

13

auto[1]

272

1

T9

2

T34

31

T76

4

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2523

1

T3

20

T5

28

T7

13

auto[1]

257

1

T9

4

T76

3

T277

3

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2491

1

T3

20

T5

21

T7

13

auto[1]

289

1

T5

7

T9

2

T34

4

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2162

1

T3

9

T5

23

T7

5

auto[1]

618

1

T3

11

T5

5

T7

8

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	4	27	87.10	4
Automatically Generated Cross Bins	31	4	27	87.10	4
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	*	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1

Covered bins

cp_precondition_key0_in_sel

cp_precondition_key1_in_sel

cp_precondition_key2_in_sel

cp_precondition_pwrb_in_sel

cp_precondition_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

858

1

T3

20

T7

13

T33

14

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

38

1

T9

5

T279

11

T382

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

99

1

T5

7

T78

1

T277

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

29

1

T34

4

T278

3

T97

8

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

75

1

T76

3

T279

11

T280

7

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

26

1

T277

2

T123

8

T383

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

30

1

T9

1

T276

5

T384

9

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

17

1

T367

1

T372

5

T123

4

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

114

1

T34

26

T76

4

T58

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

23

1

T77

2

T385

5

T275

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

21

1

T58

1

T386

3

T372

11

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

3

1

T386

2

T276

1

-

-

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

13

1

T89

2

T272

4

T387

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

8

1

T388

7

T370

1

-

-

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

6

1

T367

1

T385

3

T252

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

51

1

T5

5

T332

3

T386

20

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

8

1

T278

2

T332

3

T367

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

26

1

T58

1

T389

2

T384

9

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

7

1

T97

3

T290

3

T175

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

33

1

T123

7

T272

7

T388

4

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

3

1

T278

2

T300

1

-

-

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

19

1

T34

5

T277

3

T300

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

9

1

T277

2

T276

1

T390

6

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

3

1

T97

3

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

3

1

T9

1

T391

2

-

-

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

1

1

T387

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

3

1

T384

3

-

-

-

-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

112

1

T9

1

T34

18

T89

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

130

1

T3

6

T7

8

T240

8

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

51

1

T277

3

T299

1

T386

10

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

126

1

T3

3

T5

7

T34

4

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

41

1

T35

7

T97

3

T288

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

52

1

T3

5

T77

3

T89

6

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

38

1

T5

5

T386

10

T295

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

95

1

T33

13

T279

11

T392

6

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

82

1

T223

2

T129

6

T393

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

41

1

T278

2

T280

7

T332

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

42

1

T48

4

T76

3

T301

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

76

1

T58

1

T278

3

T97

8

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

10

1

T394

1

T395

2

T376

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

22

1

T33

1

T278

2

T332

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

8

1

T129

1

T393

1

T395

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

129

1

T58

1

T54

1

T102

11

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

93

1

T3

5

T34

13

T392

7

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

56

1

T48

5

T77

2

T54

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

24

1

T211

1

T129

2

T396

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

67

1

T9

5

T35

3

T280

6

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

20

1

T277

1

T365

3

T294

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

35

1

T48

2

T76

4

T211

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

9

1

T35

1

T369

3

T397

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

85

1

T7

5

T279

11

T293

7

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

29

1

T9

1

T289

2

T121

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

17

1

T277

2

T288

2

T102

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

10

1

T129

2

T373

4

T398

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

13

1

T78

1

T240

1

T396

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

4

1

T3

1

T285

1

T378

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

8

1

T365

2

T394

2

T200

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

1

1

T294

1

-

-

-

-

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded