Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1034

1

T14

10

T3

11

T72

11

auto[1]

1033

1

T14

10

T3

9

T72

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

502

1

T14

5

T3

7

T72

4

from_0to1

504

1

T14

4

T3

6

T72

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1029

1

T14

12

T3

8

T72

8

auto[1]

1038

1

T14

8

T3

12

T72

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1069

1

T14

15

T3

12

T72

11

auto[1]

998

1

T14

5

T3

8

T72

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

60

1

T3

1

T36

1

T283

2

auto[0]

from_1to0

auto[0]

auto[1]

56

1

T14

1

T214

1

T229

3

auto[0]

from_1to0

auto[1]

auto[0]

67

1

T3

3

T72

2

T283

1

auto[0]

from_1to0

auto[1]

auto[1]

51

1

T3

1

T229

2

T337

1

auto[0]

from_0to1

auto[0]

auto[0]

68

1

T14

3

T3

1

T72

2

auto[0]

from_0to1

auto[0]

auto[1]

71

1

T36

1

T118

1

T207

3

auto[0]

from_0to1

auto[1]

auto[0]

63

1

T3

2

T283

1

T118

1

auto[0]

from_0to1

auto[1]

auto[1]

66

1

T72

1

T283

1

T118

1

auto[1]

from_1to0

auto[0]

auto[0]

67

1

T14

2

T3

1

T72

1

auto[1]

from_1to0

auto[0]

auto[1]

68

1

T3

1

T36

1

T116

1

auto[1]

from_1to0

auto[1]

auto[0]

70

1

T14

1

T36

1

T283

2

auto[1]

from_1to0

auto[1]

auto[1]

63

1

T14

1

T72

1

T36

1

auto[1]

from_0to1

auto[0]

auto[0]

49

1

T14

1

T3

1

T36

1

auto[1]

from_0to1

auto[0]

auto[1]

55

1

T116

2

T207

1

T337

1

auto[1]

from_0to1

auto[1]

auto[0]

72

1

T3

1

T36

2

T283

1

auto[1]

from_0to1

auto[1]

auto[1]

60

1

T3

1

T72

1

T36

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1026

1

T14

8

T3

8

T72

10

auto[1]

1041

1

T14

12

T3

12

T72

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

500

1

T14

4

T3

5

T72

4

from_0to1

497

1

T14

4

T3

6

T72

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1053

1

T14

8

T3

7

T72

13

auto[1]

1014

1

T14

12

T3

13

T72

7

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1033

1

T14

12

T3

11

T72

8

auto[1]

1034

1

T14

8

T3

9

T72

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

44

1

T72

2

T118

1

T207

1

auto[0]

from_1to0

auto[0]

auto[1]

64

1

T116

2

T118

1

T229

1

auto[0]

from_1to0

auto[1]

auto[0]

61

1

T14

1

T207

1

T214

2

auto[0]

from_1to0

auto[1]

auto[1]

70

1

T3

1

T72

1

T36

2

auto[0]

from_0to1

auto[0]

auto[0]

71

1

T3

1

T214

1

T337

2

auto[0]

from_0to1

auto[0]

auto[1]

66

1

T116

1

T337

1

T242

1

auto[0]

from_0to1

auto[1]

auto[0]

54

1

T14

1

T3

1

T36

1

auto[0]

from_0to1

auto[1]

auto[1]

56

1

T3

1

T36

1

T283

2

auto[1]

from_1to0

auto[0]

auto[0]

73

1

T207

1

T214

1

T229

1

auto[1]

from_1to0

auto[0]

auto[1]

68

1

T14

2

T3

2

T283

1

auto[1]

from_1to0

auto[1]

auto[0]

62

1

T14

1

T3

2

T36

1

auto[1]

from_1to0

auto[1]

auto[1]

58

1

T72

1

T36

1

T283

1

auto[1]

from_0to1

auto[0]

auto[0]

58

1

T72

1

T283

1

T229

2

auto[1]

from_0to1

auto[0]

auto[1]

62

1

T14

1

T3

1

T72

2

auto[1]

from_0to1

auto[1]

auto[0]

66

1

T14

2

T3

1

T36

2

auto[1]

from_0to1

auto[1]

auto[1]

64

1

T3

1

T72

1

T207

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1033

1

T14

11

T3

13

T72

12

auto[1]

1034

1

T14

9

T3

7

T72

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

484

1

T14

5

T3

5

T72

4

from_0to1

494

1

T14

6

T3

5

T72

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1037

1

T14

11

T3

10

T72

9

auto[1]

1030

1

T14

9

T3

10

T72

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1043

1

T14

9

T3

10

T72

8

auto[1]

1024

1

T14

11

T3

10

T72

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

60

1

T14

1

T72

1

T283

2

auto[0]

from_1to0

auto[0]

auto[1]

60

1

T3

1

T36

1

T116

1

auto[0]

from_1to0

auto[1]

auto[0]

54

1

T3

1

T207

1

T214

1

auto[0]

from_1to0

auto[1]

auto[1]

73

1

T14

2

T3

1

T72

1

auto[0]

from_0to1

auto[0]

auto[0]

55

1

T14

3

T3

1

T116

1

auto[0]

from_0to1

auto[0]

auto[1]

70

1

T3

2

T36

2

T283

1

auto[0]

from_0to1

auto[1]

auto[0]

68

1

T3

1

T72

1

T283

1

auto[0]

from_0to1

auto[1]

auto[1]

50

1

T14

1

T72

2

T116

1

auto[1]

from_1to0

auto[0]

auto[0]

52

1

T3

1

T36

1

T116

1

auto[1]

from_1to0

auto[0]

auto[1]

50

1

T14

1

T72

1

T283

1

auto[1]

from_1to0

auto[1]

auto[0]

62

1

T3

1

T283

1

T116

1

auto[1]

from_1to0

auto[1]

auto[1]

73

1

T14

1

T72

1

T36

1

auto[1]

from_0to1

auto[0]

auto[0]

81

1

T14

1

T3

1

T72

1

auto[1]

from_0to1

auto[0]

auto[1]

52

1

T14

1

T72

1

T36

1

auto[1]

from_0to1

auto[1]

auto[0]

71

1

T283

1

T207

1

T229

2

auto[1]

from_0to1

auto[1]

auto[1]

47

1

T283

1

T214

2

T242

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1045

1

T14

8

T3

9

T72

10

auto[1]

1022

1

T14

12

T3

11

T72

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

530

1

T14

5

T3

7

T72

4

from_0to1

525

1

T14

5

T3

7

T72

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1047

1

T14

10

T3

9

T72

14

auto[1]

1020

1

T14

10

T3

11

T72

6

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1064

1

T14

7

T3

10

T72

8

auto[1]

1003

1

T14

13

T3

10

T72

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

86

1

T36

1

T118

2

T214

1

auto[0]

from_1to0

auto[0]

auto[1]

63

1

T14

2

T72

2

T283

1

auto[0]

from_1to0

auto[1]

auto[0]

59

1

T3

1

T116

1

T118

1

auto[0]

from_1to0

auto[1]

auto[1]

60

1

T14

1

T72

1

T36

1

auto[0]

from_0to1

auto[0]

auto[0]

69

1

T3

1

T36

1

T118

1

auto[0]

from_0to1

auto[0]

auto[1]

65

1

T14

1

T3

2

T72

2

auto[0]

from_0to1

auto[1]

auto[0]

72

1

T14

2

T3

1

T72

1

auto[0]

from_0to1

auto[1]

auto[1]

78

1

T3

1

T36

1

T116

1

auto[1]

from_1to0

auto[0]

auto[0]

62

1

T3

2

T116

2

T118

1

auto[1]

from_1to0

auto[0]

auto[1]

71

1

T3

1

T36

2

T116

1

auto[1]

from_1to0

auto[1]

auto[0]

66

1

T3

1

T72

1

T283

1

auto[1]

from_1to0

auto[1]

auto[1]

63

1

T14

2

T3

2

T283

2

auto[1]

from_0to1

auto[0]

auto[0]

67

1

T36

2

T116

2

T207

1

auto[1]

from_0to1

auto[0]

auto[1]

60

1

T14

1

T283

1

T207

1

auto[1]

from_0to1

auto[1]

auto[0]

61

1

T72

1

T36

1

T283

2

auto[1]

from_0to1

auto[1]

auto[1]

53

1

T14

1

T3

2

T116

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1002

1

T14

6

T3

11

T72

6

auto[1]

1065

1

T14

14

T3

9

T72

14

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

513

1

T14

4

T3

7

T72

5

from_0to1

499

1

T14

5

T3

7

T72

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1081

1

T14

12

T3

11

T72

15

auto[1]

986

1

T14

8

T3

9

T72

5

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1036

1

T14

9

T3

11

T72

9

auto[1]

1031

1

T14

11

T3

9

T72

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

65

1

T116

1

T207

1

T214

1

auto[0]

from_1to0

auto[0]

auto[1]

49

1

T14

1

T3

1

T72

1

auto[0]

from_1to0

auto[1]

auto[0]

67

1

T14

1

T283

1

T116

2

auto[0]

from_1to0

auto[1]

auto[1]

66

1

T3

2

T54

2

T339

1

auto[0]

from_0to1

auto[0]

auto[0]

62

1

T14

1

T72

1

T36

1

auto[0]

from_0to1

auto[0]

auto[1]

55

1

T3

2

T36

1

T116

1

auto[0]

from_0to1

auto[1]

auto[0]

59

1

T3

1

T72

1

T36

1

auto[0]

from_0to1

auto[1]

auto[1]

62

1

T118

1

T308

2

T338

3

auto[1]

from_1to0

auto[0]

auto[0]

65

1

T72

1

T36

2

T116

2

auto[1]

from_1to0

auto[0]

auto[1]

65

1

T14

1

T3

1

T72

1

auto[1]

from_1to0

auto[1]

auto[0]

66

1

T3

3

T36

1

T118

1

auto[1]

from_1to0

auto[1]

auto[1]

70

1

T14

1

T72

2

T283

1

auto[1]

from_0to1

auto[0]

auto[0]

73

1

T14

1

T3

3

T72

1

auto[1]

from_0to1

auto[0]

auto[1]

68

1

T14

2

T214

1

T229

1

auto[1]

from_0to1

auto[1]

auto[0]

56

1

T14

1

T3

1

T72

1

auto[1]

from_0to1

auto[1]

auto[1]

64

1

T283

1

T116

1

T118

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1058

1

T14

11

T3

11

T72

7

auto[1]

1009

1

T14

9

T3

9

T72

13

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

488

1

T14

3

T3

7

T72

5

from_0to1

483

1

T14

2

T3

7

T72

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1042

1

T14

10

T3

12

T72

7

auto[1]

1025

1

T14

10

T3

8

T72

13

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1044

1

T14

10

T3

10

T72

14

auto[1]

1023

1

T14

10

T3

10

T72

6

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

62

1

T3

2

T72

1

T283

2

auto[0]

from_1to0

auto[0]

auto[1]

62

1

T3

1

T36

1

T116

2

auto[0]

from_1to0

auto[1]

auto[0]

63

1

T14

1

T3

2

T72

2

auto[0]

from_1to0

auto[1]

auto[1]

66

1

T118

1

T214

1

T229

3

auto[0]

from_0to1

auto[0]

auto[0]

77

1

T116

2

T118

1

T207

1

auto[0]

from_0to1

auto[0]

auto[1]

72

1

T14

1

T3

2

T116

1

auto[0]

from_0to1

auto[1]

auto[0]

61

1

T3

1

T283

1

T116

1

auto[0]

from_0to1

auto[1]

auto[1]

49

1

T3

1

T36

1

T116

1

auto[1]

from_1to0

auto[0]

auto[0]

58

1

T14

2

T3

1

T36

1

auto[1]

from_1to0

auto[0]

auto[1]

64

1

T283

1

T116

1

T118

1

auto[1]

from_1to0

auto[1]

auto[0]

60

1

T72

1

T36

1

T283

1

auto[1]

from_1to0

auto[1]

auto[1]

53

1

T3

1

T72

1

T36

1

auto[1]

from_0to1

auto[0]

auto[0]

66

1

T3

1

T72

1

T36

2

auto[1]

from_0to1

auto[0]

auto[1]

48

1

T3

1

T72

1

T36

1

auto[1]

from_0to1

auto[1]

auto[0]

43

1

T72

1

T36

2

T207

1

auto[1]

from_0to1

auto[1]

auto[1]

67

1

T14

1

T3

1

T72

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1041

1

T14

11

T3

6

T72

12

auto[1]

1026

1

T14

9

T3

14

T72

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

495

1

T14

4

T3

6

T72

4

from_0to1

497

1

T14

5

T3

6

T72

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1066

1

T14

9

T3

14

T72

12

auto[1]

1001

1

T14

11

T3

6

T72

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1057

1

T14

10

T3

10

T72

8

auto[1]

1010

1

T14

10

T3

10

T72

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

73

1

T283

1

T116

1

T118

1

auto[0]

from_1to0

auto[0]

auto[1]

59

1

T14

1

T72

1

T283

2

auto[0]

from_1to0

auto[1]

auto[0]

58

1

T116

1

T118

1

T207

1

auto[0]

from_1to0

auto[1]

auto[1]

63

1

T3

2

T283

1

T118

1

auto[0]

from_0to1

auto[0]

auto[0]

64

1

T3

1

T36

1

T118

1

auto[0]

from_0to1

auto[0]

auto[1]

64

1

T14

1

T36

1

T283

1

auto[0]

from_0to1

auto[1]

auto[0]

64

1

T14

1

T72

1

T283

1

auto[0]

from_0to1

auto[1]

auto[1]

55

1

T14

1

T3

1

T283

1

auto[1]

from_1to0

auto[0]

auto[0]

75

1

T14

1

T3

1

T72

1

auto[1]

from_1to0

auto[0]

auto[1]

43

1

T3

2

T72

1

T36

1

auto[1]

from_1to0

auto[1]

auto[0]

67

1

T14

1

T3

1

T72

1

auto[1]

from_1to0

auto[1]

auto[1]

57

1

T14

1

T116

1

T118

1

auto[1]

from_0to1

auto[0]

auto[0]

60

1

T3

1

T72

1

T36

1

auto[1]

from_0to1

auto[0]

auto[1]

74

1

T3

2

T72

1

T283

1

auto[1]

from_0to1

auto[1]

auto[0]

58

1

T14

1

T3

1

T116

3

auto[1]

from_0to1

auto[1]

auto[1]

58

1

T14

1

T72

1

T36

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1040

1

T14

8

T3

12

T72

12

auto[1]

1027

1

T14

12

T3

8

T72

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

502

1

T14

4

T3

4

T72

5

from_0to1

492

1

T14

4

T3

4

T72

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1002

1

T14

11

T3

7

T72

8

auto[1]

1065

1

T14

9

T3

13

T72

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1065

1

T14

7

T3

12

T72

10

auto[1]

1002

1

T14

13

T3

8

T72

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

50

1

T14

1

T3

1

T118

1

auto[0]

from_1to0

auto[0]

auto[1]

57

1

T14

1

T72

1

T36

1

auto[0]

from_1to0

auto[1]

auto[0]

78

1

T3

2

T72

1

T36

1

auto[0]

from_1to0

auto[1]

auto[1]

61

1

T3

1

T72

1

T283

1

auto[0]

from_0to1

auto[0]

auto[0]

69

1

T283

1

T207

1

T229

1

auto[0]

from_0to1

auto[0]

auto[1]

57

1

T14

2

T3

1

T36

1

auto[0]

from_0to1

auto[1]

auto[0]

69

1

T3

1

T36

1

T283

1

auto[0]

from_0to1

auto[1]

auto[1]

60

1

T14

1

T3

1

T72

2

auto[1]

from_1to0

auto[0]

auto[0]

67

1

T72

1

T36

1

T118

3

auto[1]

from_1to0

auto[0]

auto[1]

53

1

T283

1

T207

1

T242

1

auto[1]

from_1to0

auto[1]

auto[0]

62

1

T14

1

T36

1

T283

1

auto[1]

from_1to0

auto[1]

auto[1]

74

1

T14

1

T72

1

T36

1

auto[1]

from_0to1

auto[0]

auto[0]

67

1

T3

1

T207

1

T242

1

auto[1]

from_0to1

auto[0]

auto[1]

48

1

T283

1

T214

1

T308

1

auto[1]

from_0to1

auto[1]

auto[0]

66

1

T14

1

T72

2

T36

2

auto[1]

from_0to1

auto[1]

auto[1]

56

1

T283

1

T116

1

T229

1