Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	157727	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

120488

1

T4

1

T1

11

T2

194

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	144813	1			T4	3		T1	14		T2	199
values[0x0]	66226	1			T4	1		T1	6		T2	121
values[0x1]	67176	1			T4	1		T1	2		T2	91

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	127644	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

150571

1

T4

3

T1

12

T2

231

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1132	1			T14	1		T7	2		T9	2
valid_sources[0x01]	768	1			T9	4		T27	1		T75	1
valid_sources[0x02]	909	1			T2	3		T14	2		T3	6
valid_sources[0x03]	2044	1			T14	2		T15	2		T7	1
valid_sources[0x04]	1110	1			T7	2		T9	4		T11	1
valid_sources[0x05]	797	1			T14	1		T17	1		T6	1
valid_sources[0x06]	835	1			T2	3		T14	3		T15	2
valid_sources[0x07]	1152	1			T12	1		T15	1		T7	2
valid_sources[0x08]	1128	1			T2	42		T14	1		T7	3
valid_sources[0x09]	1065	1			T2	2		T14	1		T7	4
valid_sources[0x0a]	1127	1			T14	1		T7	4		T9	6
valid_sources[0x0b]	1539	1			T12	1		T7	3		T73	1
valid_sources[0x0c]	1023	1			T14	2		T7	2		T9	1
valid_sources[0x0d]	1267	1			T14	1		T17	1		T7	4
valid_sources[0x0e]	1138	1			T12	1		T14	2		T7	3
valid_sources[0x0f]	1447	1			T4	1		T6	2		T7	3
valid_sources[0x10]	1719	1			T7	3		T72	1		T11	1
valid_sources[0x11]	1075	1			T14	1		T7	2		T73	1
valid_sources[0x12]	978	1			T27	3		T33	7		T48	6
valid_sources[0x13]	1352	1			T14	1		T7	5		T27	3
valid_sources[0x14]	1901	1			T7	3		T74	1		T284	1
valid_sources[0x15]	948	1			T7	1		T9	7		T27	3
valid_sources[0x16]	961	1			T7	6		T11	1		T27	3
valid_sources[0x17]	1050	1			T15	2		T7	1		T9	10
valid_sources[0x18]	821	1			T14	1		T7	1		T73	1
valid_sources[0x19]	1068	1			T7	1		T9	5		T27	13
valid_sources[0x1a]	1446	1			T6	2		T7	4		T9	7
valid_sources[0x1b]	886	1			T14	1		T7	6		T27	6
valid_sources[0x1c]	1816	1			T7	1		T9	3		T27	4
valid_sources[0x1d]	833	1			T14	3		T7	3		T9	11
valid_sources[0x1e]	1723	1			T14	1		T7	1		T36	4
valid_sources[0x1f]	878	1			T7	4		T26	1		T9	5
valid_sources[0x20]	814	1			T9	8		T27	7		T33	3
valid_sources[0x21]	985	1			T7	1		T56	1		T9	6
valid_sources[0x22]	998	1			T7	5		T9	5		T27	3
valid_sources[0x23]	1007	1			T6	2		T7	6		T27	9
valid_sources[0x24]	803	1			T15	2		T72	4		T27	5
valid_sources[0x25]	904	1			T6	1		T7	3		T73	1
valid_sources[0x26]	924	1			T7	1		T27	2		T75	1
valid_sources[0x27]	959	1			T14	1		T17	1		T7	1
valid_sources[0x28]	936	1			T13	2		T7	5		T73	1
valid_sources[0x29]	996	1			T15	1		T7	1		T72	17
valid_sources[0x2a]	1198	1			T17	1		T7	2		T73	1
valid_sources[0x2b]	783	1			T2	3		T7	3		T9	18
valid_sources[0x2c]	870	1			T3	20		T7	7		T9	4
valid_sources[0x2d]	1004	1			T15	1		T7	4		T9	3
valid_sources[0x2e]	862	1			T7	1		T9	5		T27	4
valid_sources[0x2f]	840	1			T6	1		T7	4		T27	4
valid_sources[0x30]	779	1			T14	1		T7	1		T116	1
valid_sources[0x31]	1692	1			T7	6		T73	1		T9	5
valid_sources[0x32]	1175	1			T3	1		T6	1		T7	4
valid_sources[0x33]	1171	1			T14	1		T15	4		T6	1
valid_sources[0x34]	805	1			T14	2		T7	5		T72	5
valid_sources[0x35]	858	1			T27	3		T33	3		T207	1
valid_sources[0x36]	978	1			T7	2		T9	20		T132	3
valid_sources[0x37]	1423	1			T3	555		T7	4		T9	3
valid_sources[0x38]	1701	1			T15	1		T7	3		T27	3
valid_sources[0x39]	835	1			T7	3		T9	10		T11	1
valid_sources[0x3a]	820	1			T7	2		T56	1		T9	2
valid_sources[0x3b]	932	1			T9	1		T27	4		T75	1
valid_sources[0x3c]	744	1			T4	1		T15	1		T7	4
valid_sources[0x3d]	913	1			T7	1		T9	3		T33	2
valid_sources[0x3e]	1048	1			T17	1		T7	2		T9	2
valid_sources[0x3f]	1209	1			T1	22		T12	1		T14	1
valid_sources[0x40]	840	1			T14	3		T7	1		T9	3
valid_sources[0x41]	944	1			T7	3		T27	16		T144	1
valid_sources[0x42]	836	1			T7	3		T144	3		T177	2
valid_sources[0x43]	1004	1			T14	1		T7	3		T26	2
valid_sources[0x44]	713	1			T14	1		T15	1		T27	6
valid_sources[0x45]	1068	1			T14	2		T15	1		T7	2
valid_sources[0x46]	913	1			T6	1		T7	1		T9	6
valid_sources[0x47]	942	1			T15	2		T73	1		T9	8
valid_sources[0x48]	1101	1			T17	1		T7	2		T9	12
valid_sources[0x49]	916	1			T2	64		T14	2		T7	1
valid_sources[0x4a]	1041	1			T12	1		T14	1		T25	1
valid_sources[0x4b]	1307	1			T7	1		T27	1		T75	1
valid_sources[0x4c]	1191	1			T14	1		T7	2		T9	4
valid_sources[0x4d]	883	1			T7	2		T73	1		T27	10
valid_sources[0x4e]	1176	1			T2	7		T7	1		T9	14
valid_sources[0x4f]	1126	1			T13	7		T7	6		T9	22
valid_sources[0x50]	1267	1			T2	3		T13	21		T3	393
valid_sources[0x51]	959	1			T14	1		T7	1		T9	6
valid_sources[0x52]	904	1			T15	1		T7	1		T27	1
valid_sources[0x53]	1211	1			T7	4		T27	10		T144	1
valid_sources[0x54]	898	1			T14	1		T7	1		T9	6
valid_sources[0x55]	1489	1			T14	1		T17	1		T6	1
valid_sources[0x56]	1035	1			T2	26		T7	4		T9	9
valid_sources[0x57]	801	1			T7	4		T9	4		T36	1
valid_sources[0x58]	1031	1			T13	18		T15	1		T7	5
valid_sources[0x59]	792	1			T7	7		T27	2		T33	1
valid_sources[0x5a]	901	1			T7	3		T73	1		T11	2
valid_sources[0x5b]	1238	1			T14	2		T7	3		T9	6
valid_sources[0x5c]	788	1			T15	1		T7	3		T9	2
valid_sources[0x5d]	894	1			T14	1		T7	1		T36	177
valid_sources[0x5e]	828	1			T13	6		T15	1		T7	1
valid_sources[0x5f]	924	1			T4	1		T7	1		T73	4
valid_sources[0x60]	998	1			T14	2		T25	5		T6	1
valid_sources[0x61]	744	1			T12	1		T14	1		T6	1
valid_sources[0x62]	919	1			T7	2		T73	1		T9	9
valid_sources[0x63]	892	1			T15	1		T7	3		T27	5
valid_sources[0x64]	956	1			T7	2		T36	4		T27	3
valid_sources[0x65]	1107	1			T7	2		T73	1		T9	14
valid_sources[0x66]	888	1			T2	4		T15	1		T3	29
valid_sources[0x67]	631	1			T14	1		T7	2		T144	4
valid_sources[0x68]	1136	1			T7	2		T9	3		T27	1
valid_sources[0x69]	3329	1			T7	4		T73	3		T131	12
valid_sources[0x6a]	1203	1			T7	1		T9	5		T178	8
valid_sources[0x6b]	1006	1			T7	3		T27	2		T33	1
valid_sources[0x6c]	2528	1			T15	3		T7	1		T9	12
valid_sources[0x6d]	1014	1			T25	1		T73	1		T9	6
valid_sources[0x6e]	945	1			T14	2		T7	4		T9	3
valid_sources[0x6f]	1280	1			T15	3		T55	1		T7	5
valid_sources[0x70]	888	1			T14	1		T7	2		T27	1
valid_sources[0x71]	2092	1			T7	1		T9	2		T27	3
valid_sources[0x72]	886	1			T15	1		T144	2		T33	1
valid_sources[0x73]	1184	1			T9	15		T27	5		T75	1
valid_sources[0x74]	784	1			T15	2		T7	3		T26	1
valid_sources[0x75]	1004	1			T9	1		T27	3		T33	7
valid_sources[0x76]	764	1			T15	5		T7	3		T11	2
valid_sources[0x77]	902	1			T7	3		T27	2		T144	3
valid_sources[0x78]	816	1			T9	9		T27	12		T144	1
valid_sources[0x79]	867	1			T12	1		T14	1		T7	2
valid_sources[0x7a]	1118	1			T6	1		T7	2		T26	1
valid_sources[0x7b]	881	1			T27	1		T178	1		T33	5
valid_sources[0x7c]	879	1			T7	1		T9	4		T74	1
valid_sources[0x7d]	1736	1			T14	1		T7	6		T27	3
valid_sources[0x7e]	667	1			T15	1		T7	2		T27	2
valid_sources[0x7f]	924	1			T27	11		T33	2		T35	2
valid_sources[0x80]	989	1			T14	1		T7	5		T9	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

65317

1

T1

9

T2

104

T12

4

values[0x0]

all_enables

biggest_size

32335

1

T4

1

T1

2

T2

58

values[0x1]

all_enables

biggest_size

22836

1

T2

32

T13

5

T14

4