Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1457701023	9392	0	0
auto_block_debounce_ctl_rd_A	1457701023	1919	0	0
auto_block_out_ctl_rd_A	1457701023	3020	0	0
com_det_ctl_0_rd_A	1457701023	3720	0	0
com_det_ctl_1_rd_A	1457701023	3825	0	0
com_det_ctl_2_rd_A	1457701023	3792	0	0
com_det_ctl_3_rd_A	1457701023	4008	0	0
com_out_ctl_0_rd_A	1457701023	4553	0	0
com_out_ctl_1_rd_A	1457701023	4665	0	0
com_out_ctl_2_rd_A	1457701023	4703	0	0
com_out_ctl_3_rd_A	1457701023	4315	0	0
com_pre_det_ctl_0_rd_A	1457701023	1213	0	0
com_pre_det_ctl_1_rd_A	1457701023	1358	0	0
com_pre_det_ctl_2_rd_A	1457701023	1351	0	0
com_pre_det_ctl_3_rd_A	1457701023	1326	0	0
com_pre_sel_ctl_0_rd_A	1457701023	4813	0	0
com_pre_sel_ctl_1_rd_A	1457701023	4968	0	0
com_pre_sel_ctl_2_rd_A	1457701023	4735	0	0
com_pre_sel_ctl_3_rd_A	1457701023	4662	0	0
com_sel_ctl_0_rd_A	1457701023	4719	0	0
com_sel_ctl_1_rd_A	1457701023	4932	0	0
com_sel_ctl_2_rd_A	1457701023	4614	0	0
com_sel_ctl_3_rd_A	1457701023	5045	0	0
ec_rst_ctl_rd_A	1457701023	2312	0	0
intr_enable_rd_A	1457701023	2011	0	0
key_intr_ctl_rd_A	1457701023	4432	0	0
key_intr_debounce_ctl_rd_A	1457701023	1338	0	0
key_invert_ctl_rd_A	1457701023	5068	0	0
pin_allowed_ctl_rd_A	1457701023	6521	0	0
pin_out_ctl_rd_A	1457701023	5055	0	0
pin_out_value_rd_A	1457701023	5156	0	0
regwen_rd_A	1457701023	1618	0	0
ulp_ac_debounce_ctl_rd_A	1457701023	1621	0	0
ulp_ctl_rd_A	1457701023	1619	0	0
ulp_lid_debounce_ctl_rd_A	1457701023	1596	0	0
ulp_pwrb_debounce_ctl_rd_A	1457701023	1490	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1457701023	9392	0	0
T2	279424	10	0	0
T3	185416	5	0	0
T5	852089	0	0	0
T12	90098	0	0	0
T13	260881	0	0	0
T14	959355	0	0	0
T15	681137	0	0	0
T16	415759	0	0	0
T17	48642	0	0	0
T25	335926	0	0	0
T36	0	12	0	0
T38	0	9	0	0
T54	0	15	0	0
T80	0	2	0	0
T83	0	8	0	0
T94	0	5	0	0
T104	0	2	0	0
T130	0	19	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1457701023	1919	0	0
T3	185416	7	0	0
T5	852089	0	0	0
T6	53570	0	0	0
T7	141270	0	0	0
T16	415759	0	0	0
T17	48642	0	0	0
T25	335926	14	0	0
T26	111460	0	0	0
T36	0	35	0	0
T52	0	12	0	0
T54	0	27	0	0
T55	192966	0	0	0
T56	271150	0	0	0
T80	0	18	0	0
T83	0	54	0	0
T95	0	8	0	0
T134	0	32	0	0
T331	0	6	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1457701023	3020	0	0
T3	185416	8	0	0
T5	852089	0	0	0
T6	53570	0	0	0
T7	141270	0	0	0
T16	415759	0	0	0
T17	48642	0	0	0
T25	335926	13	0	0
T26	111460	0	0	0
T36	0	40	0	0
T52	0	7	0	0
T54	0	28	0	0
T55	192966	0	0	0
T56	271150	0	0	0
T80	0	16	0	0
T83	0	28	0	0
T95	0	17	0	0
T134	0	24	0	0
T331	0	6	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1457701023	3720	0	0
T3	185416	97	0	0
T5	852089	0	0	0
T6	53570	0	0	0
T7	141270	0	0	0
T16	415759	0	0	0
T17	48642	0	0	0
T25	335926	0	0	0
T26	111460	0	0	0
T36	0	19	0	0
T48	0	55	0	0
T54	0	19	0	0
T55	192966	0	0	0
T56	271150	0	0	0
T68	0	29	0	0
T77	0	48	0	0
T80	0	14	0	0
T277	0	23	0	0
T280	0	47	0	0
T330	0	76	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1457701023	3825	0	0
T3	185416	122	0	0
T5	852089	0	0	0
T6	53570	0	0	0
T7	141270	0	0	0
T16	415759	0	0	0
T17	48642	0	0	0
T25	335926	0	0	0
T26	111460	0	0	0
T36	0	34	0	0
T48	0	66	0	0
T54	0	33	0	0
T55	192966	0	0	0
T56	271150	0	0	0
T68	0	28	0	0
T77	0	39	0	0
T80	0	10	0	0
T277	0	26	0	0
T280	0	84	0	0
T330	0	60	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1457701023	3792	0	0
T3	185416	99	0	0
T5	852089	0	0	0
T6	53570	0	0	0
T7	141270	0	0	0
T16	415759	0	0	0
T17	48642	0	0	0
T25	335926	0	0	0
T26	111460	0	0	0
T36	0	34	0	0
T48	0	67	0	0
T54	0	39	0	0
T55	192966	0	0	0
T56	271150	0	0	0
T68	0	29	0	0
T77	0	45	0	0
T277	0	32	0	0
T280	0	61	0	0
T330	0	73	0	0
T332	0	25	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1457701023	4008	0	0
T3	185416	117	0	0
T5	852089	0	0	0
T6	53570	0	0	0
T7	141270	0	0	0
T16	415759	0	0	0
T17	48642	0	0	0
T25	335926	0	0	0
T26	111460	0	0	0
T36	0	52	0	0
T48	0	82	0	0
T54	0	47	0	0
T55	192966	0	0	0
T56	271150	0	0	0
T68	0	42	0	0
T77	0	48	0	0
T80	0	6	0	0
T277	0	31	0	0
T280	0	66	0	0
T330	0	63	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1457701023	4553	0	0
T3	185416	150	0	0
T5	852089	0	0	0
T6	53570	0	0	0
T7	141270	0	0	0
T16	415759	0	0	0
T17	48642	0	0	0
T25	335926	0	0	0
T26	111460	0	0	0
T36	0	30	0	0
T48	0	49	0	0
T54	0	31	0	0
T55	192966	0	0	0
T56	271150	0	0	0
T68	0	37	0	0
T77	0	29	0	0
T277	0	26	0	0
T280	0	75	0	0
T330	0	60	0	0
T332	0	48	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1457701023	4665	0	0
T3	185416	109	0	0
T5	852089	0	0	0
T6	53570	0	0	0
T7	141270	0	0	0
T16	415759	0	0	0
T17	48642	0	0	0
T25	335926	0	0	0
T26	111460	0	0	0
T36	0	35	0	0
T48	0	70	0	0
T54	0	25	0	0
T55	192966	0	0	0
T56	271150	0	0	0
T68	0	33	0	0
T77	0	45	0	0
T80	0	19	0	0
T277	0	17	0	0
T280	0	89	0	0
T330	0	63	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1457701023	4703	0	0
T3	185416	91	0	0
T5	852089	0	0	0
T6	53570	0	0	0
T7	141270	0	0	0
T16	415759	0	0	0
T17	48642	0	0	0
T25	335926	0	0	0
T26	111460	0	0	0
T36	0	40	0	0
T48	0	74	0	0
T54	0	45	0	0
T55	192966	0	0	0
T56	271150	0	0	0
T68	0	37	0	0
T77	0	50	0	0
T80	0	12	0	0
T277	0	26	0	0
T280	0	89	0	0
T330	0	62	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1457701023	4315	0	0
T3	185416	112	0	0
T5	852089	0	0	0
T6	53570	0	0	0
T7	141270	0	0	0
T16	415759	0	0	0
T17	48642	0	0	0
T25	335926	0	0	0
T26	111460	0	0	0
T36	0	40	0	0
T48	0	72	0	0
T54	0	35	0	0
T55	192966	0	0	0
T56	271150	0	0	0
T68	0	34	0	0
T77	0	29	0	0
T80	0	2	0	0
T277	0	27	0	0
T280	0	75	0	0
T330	0	55	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1457701023	1213	0	0
T3	185416	9	0	0
T5	852089	0	0	0
T6	53570	0	0	0
T7	141270	0	0	0
T16	415759	0	0	0
T17	48642	0	0	0
T25	335926	0	0	0
T26	111460	0	0	0
T36	0	29	0	0
T54	0	40	0	0
T55	192966	0	0	0
T56	271150	0	0	0
T83	0	17	0	0
T113	0	14	0	0
T139	0	18	0	0
T159	0	19	0	0
T166	0	15	0	0
T174	0	6	0	0
T333	0	23	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1457701023	1358	0	0
T3	185416	16	0	0
T5	852089	0	0	0
T6	53570	0	0	0
T7	141270	0	0	0
T16	415759	0	0	0
T17	48642	0	0	0
T25	335926	0	0	0
T26	111460	0	0	0
T36	0	45	0	0
T54	0	23	0	0
T55	192966	0	0	0
T56	271150	0	0	0
T80	0	6	0	0
T83	0	38	0	0
T113	0	21	0	0
T139	0	6	0	0
T159	0	25	0	0
T174	0	8	0	0
T333	0	36	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1457701023	1351	0	0
T3	185416	15	0	0
T5	852089	0	0	0
T6	53570	0	0	0
T7	141270	0	0	0
T16	415759	0	0	0
T17	48642	0	0	0
T25	335926	0	0	0
T26	111460	0	0	0
T36	0	28	0	0
T54	0	42	0	0
T55	192966	0	0	0
T56	271150	0	0	0
T80	0	6	0	0
T83	0	24	0	0
T113	0	15	0	0
T139	0	8	0	0
T159	0	15	0	0
T166	0	11	0	0
T174	0	15	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1457701023	1326	0	0
T3	185416	17	0	0
T5	852089	0	0	0
T6	53570	0	0	0
T7	141270	0	0	0
T16	415759	0	0	0
T17	48642	0	0	0
T25	335926	0	0	0
T26	111460	0	0	0
T36	0	38	0	0
T54	0	29	0	0
T55	192966	0	0	0
T56	271150	0	0	0
T80	0	5	0	0
T83	0	22	0	0
T113	0	5	0	0
T139	0	12	0	0
T159	0	18	0	0
T166	0	6	0	0
T174	0	1	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1457701023	4813	0	0
T3	185416	112	0	0
T5	852089	0	0	0
T6	53570	0	0	0
T7	141270	0	0	0
T16	415759	0	0	0
T17	48642	0	0	0
T25	335926	0	0	0
T26	111460	0	0	0
T36	0	30	0	0
T48	0	81	0	0
T54	0	27	0	0
T55	192966	0	0	0
T56	271150	0	0	0
T68	0	32	0	0
T77	0	47	0	0
T80	0	14	0	0
T277	0	26	0	0
T280	0	105	0	0
T330	0	84	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1457701023	4968	0	0
T3	185416	112	0	0
T5	852089	0	0	0
T6	53570	0	0	0
T7	141270	0	0	0
T16	415759	0	0	0
T17	48642	0	0	0
T25	335926	0	0	0
T26	111460	0	0	0
T36	0	39	0	0
T48	0	60	0	0
T54	0	21	0	0
T55	192966	0	0	0
T56	271150	0	0	0
T68	0	54	0	0
T77	0	58	0	0
T80	0	8	0	0
T277	0	17	0	0
T280	0	67	0	0
T330	0	71	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1457701023	4735	0	0
T3	185416	102	0	0
T5	852089	0	0	0
T6	53570	0	0	0
T7	141270	0	0	0
T16	415759	0	0	0
T17	48642	0	0	0
T25	335926	0	0	0
T26	111460	0	0	0
T36	0	42	0	0
T48	0	82	0	0
T54	0	44	0	0
T55	192966	0	0	0
T56	271150	0	0	0
T68	0	40	0	0
T77	0	47	0	0
T80	0	10	0	0
T277	0	19	0	0
T280	0	77	0	0
T330	0	72	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1457701023	4662	0	0
T3	185416	130	0	0
T5	852089	0	0	0
T6	53570	0	0	0
T7	141270	0	0	0
T16	415759	0	0	0
T17	48642	0	0	0
T25	335926	0	0	0
T26	111460	0	0	0
T36	0	48	0	0
T48	0	96	0	0
T54	0	28	0	0
T55	192966	0	0	0
T56	271150	0	0	0
T68	0	36	0	0
T77	0	52	0	0
T80	0	6	0	0
T277	0	20	0	0
T280	0	63	0	0
T330	0	71	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1457701023	4719	0	0
T3	185416	115	0	0
T5	852089	0	0	0
T6	53570	0	0	0
T7	141270	0	0	0
T16	415759	0	0	0
T17	48642	0	0	0
T25	335926	0	0	0
T26	111460	0	0	0
T36	0	41	0	0
T48	0	78	0	0
T54	0	45	0	0
T55	192966	0	0	0
T56	271150	0	0	0
T68	0	30	0	0
T77	0	32	0	0
T80	0	8	0	0
T277	0	27	0	0
T280	0	76	0	0
T330	0	86	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1457701023	4932	0	0
T3	185416	101	0	0
T5	852089	0	0	0
T6	53570	0	0	0
T7	141270	0	0	0
T16	415759	0	0	0
T17	48642	0	0	0
T25	335926	0	0	0
T26	111460	0	0	0
T36	0	51	0	0
T48	0	68	0	0
T54	0	28	0	0
T55	192966	0	0	0
T56	271150	0	0	0
T68	0	38	0	0
T77	0	47	0	0
T80	0	7	0	0
T277	0	48	0	0
T280	0	66	0	0
T330	0	93	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1457701023	4614	0	0
T3	185416	115	0	0
T5	852089	0	0	0
T6	53570	0	0	0
T7	141270	0	0	0
T16	415759	0	0	0
T17	48642	0	0	0
T25	335926	0	0	0
T26	111460	0	0	0
T36	0	27	0	0
T48	0	59	0	0
T54	0	26	0	0
T55	192966	0	0	0
T56	271150	0	0	0
T68	0	39	0	0
T77	0	43	0	0
T80	0	11	0	0
T277	0	23	0	0
T280	0	90	0	0
T330	0	62	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1457701023	5045	0	0
T3	185416	115	0	0
T5	852089	0	0	0
T6	53570	0	0	0
T7	141270	0	0	0
T16	415759	0	0	0
T17	48642	0	0	0
T25	335926	0	0	0
T26	111460	0	0	0
T36	0	37	0	0
T48	0	72	0	0
T54	0	35	0	0
T55	192966	0	0	0
T56	271150	0	0	0
T68	0	26	0	0
T77	0	71	0	0
T277	0	31	0	0
T280	0	66	0	0
T330	0	78	0	0
T332	0	41	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1457701023	2312	0	0
T3	185416	76	0	0
T5	852089	0	0	0
T6	53570	0	0	0
T7	141270	0	0	0
T16	415759	0	0	0
T17	48642	0	0	0
T25	335926	0	0	0
T26	111460	0	0	0
T36	0	33	0	0
T48	0	18	0	0
T54	0	54	0	0
T55	192966	0	0	0
T56	271150	1	0	0
T77	0	8	0	0
T80	0	7	0	0
T277	0	18	0	0
T280	0	29	0	0
T332	0	12	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1457701023	2011	0	0
T3	185416	2	0	0
T5	852089	0	0	0
T6	53570	0	0	0
T7	141270	0	0	0
T16	415759	0	0	0
T17	48642	0	0	0
T25	335926	0	0	0
T26	111460	0	0	0
T36	0	47	0	0
T54	0	25	0	0
T55	192966	0	0	0
T56	271150	0	0	0
T80	0	19	0	0
T83	0	37	0	0
T113	0	55	0	0
T139	0	118	0	0
T159	0	117	0	0
T174	0	8	0	0
T334	0	17	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1457701023	4432	0	0
T1	285650	1	0	0
T2	279424	0	0	0
T3	185416	5	0	0
T5	852089	0	0	0
T12	90098	0	0	0
T13	260881	0	0	0
T14	959355	0	0	0
T15	681137	0	0	0
T16	415759	0	0	0
T17	48642	0	0	0
T36	0	49	0	0
T43	0	9	0	0
T54	0	18	0	0
T80	0	27	0	0
T83	0	31	0	0
T158	0	1	0	0
T176	0	7	0	0
T190	0	5	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1457701023	1338	0	0
T3	185416	9	0	0
T5	852089	0	0	0
T6	53570	0	0	0
T7	141270	0	0	0
T16	415759	0	0	0
T17	48642	0	0	0
T25	335926	0	0	0
T26	111460	0	0	0
T36	0	44	0	0
T54	0	22	0	0
T55	192966	0	0	0
T56	271150	0	0	0
T80	0	11	0	0
T83	0	18	0	0
T113	0	9	0	0
T139	0	13	0	0
T159	0	14	0	0
T166	0	5	0	0
T174	0	12	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1457701023	5068	0	0
T3	185416	18	0	0
T5	852089	0	0	0
T6	53570	0	0	0
T7	141270	0	0	0
T16	415759	0	0	0
T17	48642	0	0	0
T22	0	35	0	0
T25	335926	0	0	0
T26	111460	0	0	0
T36	0	47	0	0
T54	0	20	0	0
T55	192966	0	0	0
T56	271150	0	0	0
T63	0	36	0	0
T66	0	86	0	0
T80	0	6	0	0
T83	0	193	0	0
T335	0	68	0	0
T336	0	62	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1457701023	6521	0	0
T3	185416	60	0	0
T5	852089	0	0	0
T6	53570	0	0	0
T7	141270	0	0	0
T16	415759	0	0	0
T17	48642	0	0	0
T25	335926	0	0	0
T26	111460	0	0	0
T36	0	103	0	0
T54	0	227	0	0
T55	192966	0	0	0
T56	271150	0	0	0
T118	0	52	0	0
T242	0	59	0	0
T283	0	90	0	0
T308	0	83	0	0
T337	0	48	0	0
T338	0	85	0	0
T339	0	28	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1457701023	5055	0	0
T3	185416	67	0	0
T5	852089	0	0	0
T6	53570	0	0	0
T7	141270	0	0	0
T16	415759	0	0	0
T17	48642	0	0	0
T25	335926	0	0	0
T26	111460	0	0	0
T36	0	93	0	0
T54	0	213	0	0
T55	192966	0	0	0
T56	271150	0	0	0
T118	0	63	0	0
T242	0	31	0	0
T283	0	66	0	0
T308	0	57	0	0
T337	0	57	0	0
T338	0	75	0	0
T339	0	73	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1457701023	5156	0	0
T3	185416	82	0	0
T5	852089	0	0	0
T6	53570	0	0	0
T7	141270	0	0	0
T16	415759	0	0	0
T17	48642	0	0	0
T25	335926	0	0	0
T26	111460	0	0	0
T36	0	106	0	0
T54	0	229	0	0
T55	192966	0	0	0
T56	271150	0	0	0
T118	0	94	0	0
T242	0	47	0	0
T283	0	70	0	0
T308	0	63	0	0
T337	0	60	0	0
T338	0	41	0	0
T339	0	72	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1457701023	1618	0	0
T3	185416	5	0	0
T5	852089	0	0	0
T6	53570	0	0	0
T7	141270	0	0	0
T16	415759	0	0	0
T17	48642	0	0	0
T25	335926	0	0	0
T26	111460	0	0	0
T36	0	34	0	0
T54	0	25	0	0
T55	192966	0	0	0
T56	271150	0	0	0
T80	0	6	0	0
T83	0	20	0	0
T113	0	16	0	0
T139	0	15	0	0
T159	0	27	0	0
T166	0	10	0	0
T174	0	6	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1457701023	1621	0	0
T3	185416	23	0	0
T5	852089	0	0	0
T6	53570	4	0	0
T7	141270	0	0	0
T16	415759	0	0	0
T17	48642	0	0	0
T25	335926	0	0	0
T26	111460	0	0	0
T32	0	2	0	0
T36	0	24	0	0
T54	0	43	0	0
T55	192966	0	0	0
T56	271150	0	0	0
T61	0	10	0	0
T79	0	7	0	0
T80	0	6	0	0
T243	0	1	0	0
T340	0	8	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1457701023	1619	0	0
T3	185416	18	0	0
T5	852089	0	0	0
T6	53570	7	0	0
T7	141270	0	0	0
T16	415759	0	0	0
T17	48642	0	0	0
T25	335926	0	0	0
T26	111460	0	0	0
T32	0	7	0	0
T36	0	26	0	0
T54	0	28	0	0
T55	192966	0	0	0
T56	271150	0	0	0
T61	0	23	0	0
T79	0	5	0	0
T80	0	7	0	0
T243	0	9	0	0
T340	0	8	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1457701023	1596	0	0
T3	185416	18	0	0
T5	852089	0	0	0
T6	53570	10	0	0
T7	141270	0	0	0
T16	415759	0	0	0
T17	48642	0	0	0
T25	335926	0	0	0
T26	111460	0	0	0
T32	0	4	0	0
T36	0	49	0	0
T54	0	41	0	0
T55	192966	0	0	0
T56	271150	0	0	0
T57	0	5	0	0
T61	0	11	0	0
T79	0	10	0	0
T80	0	12	0	0
T243	0	6	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1457701023	1490	0	0
T3	185416	13	0	0
T5	852089	0	0	0
T6	53570	2	0	0
T7	141270	0	0	0
T16	415759	0	0	0
T17	48642	0	0	0
T25	335926	0	0	0
T26	111460	0	0	0
T36	0	33	0	0
T54	0	22	0	0
T55	192966	0	0	0
T56	271150	0	0	0
T57	0	5	0	0
T61	0	12	0	0
T80	0	21	0	0
T83	0	38	0	0
T243	0	8	0	0
T340	0	6	0	0