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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.94 99.40 96.78 100.00 97.44 98.89 99.61 93.46


Total test records in report: 908
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html

T475 /workspace/coverage/default/27.sysrst_ctrl_flash_wr_prot_out.600314903 Apr 15 01:02:12 PM PDT 24 Apr 15 01:02:20 PM PDT 24 2610690487 ps
T295 /workspace/coverage/default/2.sysrst_ctrl_combo_detect.2132276943 Apr 15 01:01:06 PM PDT 24 Apr 15 01:04:37 PM PDT 24 153410479996 ps
T476 /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3787674924 Apr 15 01:01:05 PM PDT 24 Apr 15 01:01:12 PM PDT 24 2344629095 ps
T477 /workspace/coverage/default/39.sysrst_ctrl_ultra_low_pwr.4056361091 Apr 15 01:02:45 PM PDT 24 Apr 15 01:02:50 PM PDT 24 2824690735 ps
T478 /workspace/coverage/default/45.sysrst_ctrl_pin_override_test.3336570948 Apr 15 01:02:52 PM PDT 24 Apr 15 01:02:55 PM PDT 24 2543303083 ps
T301 /workspace/coverage/default/36.sysrst_ctrl_stress_all_with_rand_reset.1243485189 Apr 15 01:02:43 PM PDT 24 Apr 15 01:05:17 PM PDT 24 69300905650 ps
T281 /workspace/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.411957976 Apr 15 01:03:08 PM PDT 24 Apr 15 01:04:25 PM PDT 24 31710389332 ps
T479 /workspace/coverage/default/6.sysrst_ctrl_pin_override_test.1004872893 Apr 15 01:01:22 PM PDT 24 Apr 15 01:01:27 PM PDT 24 2520324566 ps
T403 /workspace/coverage/default/24.sysrst_ctrl_ultra_low_pwr.3963981421 Apr 15 01:02:03 PM PDT 24 Apr 15 01:02:43 PM PDT 24 1035829895576 ps
T480 /workspace/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.3109545300 Apr 15 01:02:17 PM PDT 24 Apr 15 01:02:25 PM PDT 24 2609812533 ps
T481 /workspace/coverage/default/18.sysrst_ctrl_alert_test.1947067823 Apr 15 01:01:52 PM PDT 24 Apr 15 01:01:58 PM PDT 24 2013339024 ps
T482 /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3238460835 Apr 15 01:01:12 PM PDT 24 Apr 15 01:01:14 PM PDT 24 2568161840 ps
T92 /workspace/coverage/default/36.sysrst_ctrl_ultra_low_pwr.1142511011 Apr 15 01:02:40 PM PDT 24 Apr 15 01:02:46 PM PDT 24 12862383111 ps
T145 /workspace/coverage/default/22.sysrst_ctrl_flash_wr_prot_out.4255275028 Apr 15 01:02:05 PM PDT 24 Apr 15 01:02:10 PM PDT 24 2621548763 ps
T146 /workspace/coverage/default/13.sysrst_ctrl_smoke.1065329134 Apr 15 01:01:34 PM PDT 24 Apr 15 01:01:37 PM PDT 24 2137865308 ps
T147 /workspace/coverage/default/8.sysrst_ctrl_edge_detect.3417280132 Apr 15 01:01:25 PM PDT 24 Apr 15 01:01:28 PM PDT 24 2637055702 ps
T148 /workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.1594064254 Apr 15 01:02:54 PM PDT 24 Apr 15 01:02:58 PM PDT 24 3577869774 ps
T149 /workspace/coverage/default/39.sysrst_ctrl_combo_detect_with_pre_cond.2068197833 Apr 15 01:02:46 PM PDT 24 Apr 15 01:03:20 PM PDT 24 26835823722 ps
T150 /workspace/coverage/default/20.sysrst_ctrl_auto_blk_key_output.2564013349 Apr 15 01:02:01 PM PDT 24 Apr 15 01:02:04 PM PDT 24 3489206555 ps
T151 /workspace/coverage/default/35.sysrst_ctrl_auto_blk_key_output.211867148 Apr 15 01:02:31 PM PDT 24 Apr 15 01:02:34 PM PDT 24 2985681659 ps
T152 /workspace/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.111794620 Apr 15 01:02:21 PM PDT 24 Apr 15 01:02:30 PM PDT 24 2610710222 ps
T153 /workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.1631907609 Apr 15 01:02:52 PM PDT 24 Apr 15 01:06:19 PM PDT 24 1403925665825 ps
T345 /workspace/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.3501096016 Apr 15 01:02:46 PM PDT 24 Apr 15 01:06:44 PM PDT 24 884282869285 ps
T372 /workspace/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.1766505206 Apr 15 01:03:05 PM PDT 24 Apr 15 01:06:04 PM PDT 24 307239236908 ps
T483 /workspace/coverage/default/40.sysrst_ctrl_pin_access_test.2790960751 Apr 15 01:02:48 PM PDT 24 Apr 15 01:02:49 PM PDT 24 2152087037 ps
T484 /workspace/coverage/default/23.sysrst_ctrl_smoke.3300364319 Apr 15 01:02:06 PM PDT 24 Apr 15 01:02:12 PM PDT 24 2112616536 ps
T485 /workspace/coverage/default/42.sysrst_ctrl_alert_test.3849756899 Apr 15 01:02:52 PM PDT 24 Apr 15 01:02:54 PM PDT 24 2048701788 ps
T282 /workspace/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.214127716 Apr 15 01:03:10 PM PDT 24 Apr 15 01:05:15 PM PDT 24 49088685949 ps
T486 /workspace/coverage/default/19.sysrst_ctrl_flash_wr_prot_out.372272541 Apr 15 01:01:52 PM PDT 24 Apr 15 01:01:54 PM PDT 24 2647580819 ps
T487 /workspace/coverage/default/32.sysrst_ctrl_smoke.1232142980 Apr 15 01:02:18 PM PDT 24 Apr 15 01:02:20 PM PDT 24 2121622662 ps
T488 /workspace/coverage/default/24.sysrst_ctrl_smoke.467365150 Apr 15 01:02:08 PM PDT 24 Apr 15 01:02:15 PM PDT 24 2107941703 ps
T489 /workspace/coverage/default/29.sysrst_ctrl_pin_access_test.240294448 Apr 15 01:02:14 PM PDT 24 Apr 15 01:02:18 PM PDT 24 2066121886 ps
T331 /workspace/coverage/default/12.sysrst_ctrl_auto_blk_key_output.2772294066 Apr 15 01:01:42 PM PDT 24 Apr 15 01:01:47 PM PDT 24 3397057778 ps
T490 /workspace/coverage/default/17.sysrst_ctrl_flash_wr_prot_out.1297445830 Apr 15 01:01:54 PM PDT 24 Apr 15 01:01:56 PM PDT 24 2629898632 ps
T491 /workspace/coverage/default/28.sysrst_ctrl_combo_detect.1205013173 Apr 15 01:02:15 PM PDT 24 Apr 15 01:03:13 PM PDT 24 100774589407 ps
T385 /workspace/coverage/default/31.sysrst_ctrl_combo_detect_with_pre_cond.2493944838 Apr 15 01:02:23 PM PDT 24 Apr 15 01:03:49 PM PDT 24 141712528311 ps
T105 /workspace/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.2961533407 Apr 15 01:01:06 PM PDT 24 Apr 15 01:02:29 PM PDT 24 59948781703 ps
T87 /workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.490810804 Apr 15 01:02:56 PM PDT 24 Apr 15 01:04:10 PM PDT 24 54137183528 ps
T119 /workspace/coverage/default/21.sysrst_ctrl_pin_override_test.3723652066 Apr 15 01:01:58 PM PDT 24 Apr 15 01:02:01 PM PDT 24 2519450971 ps
T120 /workspace/coverage/default/31.sysrst_ctrl_alert_test.3368724812 Apr 15 01:02:22 PM PDT 24 Apr 15 01:02:28 PM PDT 24 2010968361 ps
T121 /workspace/coverage/default/9.sysrst_ctrl_combo_detect.91208617 Apr 15 01:01:26 PM PDT 24 Apr 15 01:02:21 PM PDT 24 81617756340 ps
T122 /workspace/coverage/default/8.sysrst_ctrl_stress_all.3007745780 Apr 15 01:01:26 PM PDT 24 Apr 15 01:03:20 PM PDT 24 45616414316 ps
T123 /workspace/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.3773589148 Apr 15 01:03:19 PM PDT 24 Apr 15 01:05:24 PM PDT 24 103081945290 ps
T124 /workspace/coverage/default/30.sysrst_ctrl_stress_all.2967955848 Apr 15 01:02:27 PM PDT 24 Apr 15 01:08:15 PM PDT 24 121556624535 ps
T125 /workspace/coverage/default/33.sysrst_ctrl_stress_all_with_rand_reset.4039173375 Apr 15 01:02:27 PM PDT 24 Apr 15 01:04:38 PM PDT 24 556276825162 ps
T126 /workspace/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.3991874396 Apr 15 01:02:05 PM PDT 24 Apr 15 01:05:06 PM PDT 24 1750621467800 ps
T127 /workspace/coverage/default/39.sysrst_ctrl_smoke.2767869345 Apr 15 01:02:44 PM PDT 24 Apr 15 01:02:46 PM PDT 24 2128795288 ps
T205 /workspace/coverage/default/27.sysrst_ctrl_edge_detect.3055283384 Apr 15 01:02:11 PM PDT 24 Apr 15 01:02:15 PM PDT 24 4078257119 ps
T88 /workspace/coverage/default/47.sysrst_ctrl_edge_detect.1788914607 Apr 15 01:03:00 PM PDT 24 Apr 15 01:03:04 PM PDT 24 2452622156 ps
T196 /workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.3110242903 Apr 15 01:03:04 PM PDT 24 Apr 15 01:03:08 PM PDT 24 3508805296 ps
T197 /workspace/coverage/default/4.sysrst_ctrl_smoke.1207415534 Apr 15 01:01:10 PM PDT 24 Apr 15 01:01:16 PM PDT 24 2107988087 ps
T198 /workspace/coverage/default/13.sysrst_ctrl_ec_pwr_on_rst.3227571598 Apr 15 01:01:40 PM PDT 24 Apr 15 01:01:47 PM PDT 24 3492947253 ps
T199 /workspace/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.3058651086 Apr 15 01:03:06 PM PDT 24 Apr 15 01:03:53 PM PDT 24 75969813352 ps
T200 /workspace/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.3781220003 Apr 15 01:01:13 PM PDT 24 Apr 15 01:02:40 PM PDT 24 131182622800 ps
T201 /workspace/coverage/default/25.sysrst_ctrl_in_out_inverted.2204430182 Apr 15 01:02:03 PM PDT 24 Apr 15 01:02:05 PM PDT 24 2521176853 ps
T202 /workspace/coverage/default/0.sysrst_ctrl_in_out_inverted.2646763442 Apr 15 01:01:01 PM PDT 24 Apr 15 01:01:03 PM PDT 24 2494460084 ps
T203 /workspace/coverage/default/21.sysrst_ctrl_in_out_inverted.1586605054 Apr 15 01:02:00 PM PDT 24 Apr 15 01:02:07 PM PDT 24 2456278355 ps
T204 /workspace/coverage/default/31.sysrst_ctrl_ec_pwr_on_rst.2776409658 Apr 15 01:02:30 PM PDT 24 Apr 15 01:02:37 PM PDT 24 4844009600 ps
T300 /workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.1602593925 Apr 15 01:03:10 PM PDT 24 Apr 15 01:06:47 PM PDT 24 79725394721 ps
T391 /workspace/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.2849170253 Apr 15 01:03:03 PM PDT 24 Apr 15 01:04:13 PM PDT 24 53190850873 ps
T275 /workspace/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.2860937530 Apr 15 01:03:06 PM PDT 24 Apr 15 01:04:22 PM PDT 24 63120888541 ps
T106 /workspace/coverage/default/45.sysrst_ctrl_combo_detect.400105237 Apr 15 01:02:56 PM PDT 24 Apr 15 01:06:14 PM PDT 24 75932033861 ps
T492 /workspace/coverage/default/30.sysrst_ctrl_smoke.2022917734 Apr 15 01:02:16 PM PDT 24 Apr 15 01:02:18 PM PDT 24 2131165761 ps
T493 /workspace/coverage/default/31.sysrst_ctrl_pin_access_test.700925825 Apr 15 01:02:23 PM PDT 24 Apr 15 01:02:30 PM PDT 24 2239247514 ps
T494 /workspace/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.4034588652 Apr 15 01:02:56 PM PDT 24 Apr 15 01:03:04 PM PDT 24 33309416187 ps
T495 /workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.4245261744 Apr 15 01:02:54 PM PDT 24 Apr 15 01:03:03 PM PDT 24 3263782831 ps
T496 /workspace/coverage/default/17.sysrst_ctrl_ultra_low_pwr.4043138826 Apr 15 01:01:52 PM PDT 24 Apr 15 01:01:55 PM PDT 24 5440931052 ps
T497 /workspace/coverage/default/14.sysrst_ctrl_stress_all_with_rand_reset.1310475154 Apr 15 01:01:51 PM PDT 24 Apr 15 01:03:45 PM PDT 24 44559332002 ps
T498 /workspace/coverage/default/45.sysrst_ctrl_smoke.3669811746 Apr 15 01:02:56 PM PDT 24 Apr 15 01:02:58 PM PDT 24 2132935637 ps
T499 /workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.601766218 Apr 15 01:02:50 PM PDT 24 Apr 15 01:03:55 PM PDT 24 304736646215 ps
T500 /workspace/coverage/default/18.sysrst_ctrl_flash_wr_prot_out.1217917941 Apr 15 01:01:51 PM PDT 24 Apr 15 01:01:56 PM PDT 24 2613582616 ps
T501 /workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.3016178675 Apr 15 01:02:55 PM PDT 24 Apr 15 01:03:03 PM PDT 24 2740096701 ps
T276 /workspace/coverage/default/17.sysrst_ctrl_combo_detect_with_pre_cond.996646511 Apr 15 01:01:54 PM PDT 24 Apr 15 01:06:58 PM PDT 24 106952033229 ps
T502 /workspace/coverage/default/12.sysrst_ctrl_smoke.3730245642 Apr 15 01:01:32 PM PDT 24 Apr 15 01:01:36 PM PDT 24 2119583765 ps
T503 /workspace/coverage/default/0.sysrst_ctrl_auto_blk_key_output.1954180410 Apr 15 01:01:02 PM PDT 24 Apr 15 01:01:04 PM PDT 24 3449396234 ps
T504 /workspace/coverage/default/36.sysrst_ctrl_combo_detect_with_pre_cond.1075949699 Apr 15 01:02:38 PM PDT 24 Apr 15 01:03:27 PM PDT 24 36484481386 ps
T505 /workspace/coverage/default/46.sysrst_ctrl_alert_test.112826122 Apr 15 01:03:01 PM PDT 24 Apr 15 01:03:02 PM PDT 24 2111156381 ps
T506 /workspace/coverage/default/25.sysrst_ctrl_combo_detect.2906340825 Apr 15 01:02:09 PM PDT 24 Apr 15 01:03:14 PM PDT 24 96665854612 ps
T507 /workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.1567149200 Apr 15 01:02:59 PM PDT 24 Apr 15 01:03:07 PM PDT 24 2457355218 ps
T508 /workspace/coverage/default/36.sysrst_ctrl_pin_override_test.693699013 Apr 15 01:02:43 PM PDT 24 Apr 15 01:02:51 PM PDT 24 2510753484 ps
T509 /workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.3797144946 Apr 15 01:01:21 PM PDT 24 Apr 15 01:04:03 PM PDT 24 64346865128 ps
T290 /workspace/coverage/default/27.sysrst_ctrl_combo_detect_with_pre_cond.3987390789 Apr 15 01:02:10 PM PDT 24 Apr 15 01:02:24 PM PDT 24 66252003359 ps
T389 /workspace/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.4037504778 Apr 15 01:03:10 PM PDT 24 Apr 15 01:05:38 PM PDT 24 59489015980 ps
T510 /workspace/coverage/default/48.sysrst_ctrl_alert_test.1971407131 Apr 15 01:03:05 PM PDT 24 Apr 15 01:03:08 PM PDT 24 2038016528 ps
T225 /workspace/coverage/default/7.sysrst_ctrl_edge_detect.4120592888 Apr 15 01:01:23 PM PDT 24 Apr 15 01:01:30 PM PDT 24 3323549401 ps
T511 /workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.981449656 Apr 15 01:01:12 PM PDT 24 Apr 15 01:01:20 PM PDT 24 2542395497 ps
T512 /workspace/coverage/default/38.sysrst_ctrl_flash_wr_prot_out.2358402304 Apr 15 01:02:44 PM PDT 24 Apr 15 01:02:53 PM PDT 24 2614351194 ps
T162 /workspace/coverage/default/42.sysrst_ctrl_edge_detect.2357950417 Apr 15 01:02:48 PM PDT 24 Apr 15 01:03:01 PM PDT 24 5561485613 ps
T328 /workspace/coverage/default/2.sysrst_ctrl_sec_cm.2149350184 Apr 15 01:01:08 PM PDT 24 Apr 15 01:01:35 PM PDT 24 42279048607 ps
T513 /workspace/coverage/default/6.sysrst_ctrl_pin_access_test.1077571675 Apr 15 01:01:20 PM PDT 24 Apr 15 01:01:23 PM PDT 24 2230161063 ps
T136 /workspace/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.1405600280 Apr 15 01:01:53 PM PDT 24 Apr 15 01:03:29 PM PDT 24 36856256464 ps
T257 /workspace/coverage/default/19.sysrst_ctrl_ec_pwr_on_rst.506162916 Apr 15 01:01:52 PM PDT 24 Apr 15 01:01:56 PM PDT 24 3513156181 ps
T254 /workspace/coverage/default/26.sysrst_ctrl_stress_all.1922679383 Apr 15 01:02:10 PM PDT 24 Apr 15 01:02:19 PM PDT 24 13463027125 ps
T258 /workspace/coverage/default/1.sysrst_ctrl_ultra_low_pwr.2078385395 Apr 15 01:01:08 PM PDT 24 Apr 15 01:01:16 PM PDT 24 5591717484 ps
T259 /workspace/coverage/default/19.sysrst_ctrl_smoke.232542781 Apr 15 01:01:51 PM PDT 24 Apr 15 01:01:57 PM PDT 24 2112501247 ps
T260 /workspace/coverage/default/46.sysrst_ctrl_pin_access_test.4044341326 Apr 15 01:02:51 PM PDT 24 Apr 15 01:02:58 PM PDT 24 2238357024 ps
T261 /workspace/coverage/default/17.sysrst_ctrl_auto_blk_key_output.2311890636 Apr 15 01:01:58 PM PDT 24 Apr 15 01:02:03 PM PDT 24 3270053756 ps
T262 /workspace/coverage/default/10.sysrst_ctrl_smoke.4292221149 Apr 15 01:01:30 PM PDT 24 Apr 15 01:01:36 PM PDT 24 2106742259 ps
T263 /workspace/coverage/default/21.sysrst_ctrl_stress_all.568114041 Apr 15 01:01:59 PM PDT 24 Apr 15 01:02:27 PM PDT 24 10221088995 ps
T264 /workspace/coverage/default/48.sysrst_ctrl_smoke.3388926203 Apr 15 01:03:03 PM PDT 24 Apr 15 01:03:07 PM PDT 24 2118717584 ps
T244 /workspace/coverage/default/31.sysrst_ctrl_edge_detect.1996442736 Apr 15 01:02:22 PM PDT 24 Apr 15 01:24:27 PM PDT 24 1590336017771 ps
T514 /workspace/coverage/default/32.sysrst_ctrl_pin_override_test.3080505648 Apr 15 01:02:24 PM PDT 24 Apr 15 01:02:31 PM PDT 24 2509818359 ps
T291 /workspace/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.815124592 Apr 15 01:03:07 PM PDT 24 Apr 15 01:06:20 PM PDT 24 71622575158 ps
T137 /workspace/coverage/default/23.sysrst_ctrl_ultra_low_pwr.573090085 Apr 15 01:02:04 PM PDT 24 Apr 15 01:02:12 PM PDT 24 7119440347 ps
T292 /workspace/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.2289294774 Apr 15 01:03:12 PM PDT 24 Apr 15 01:03:45 PM PDT 24 48292693909 ps
T515 /workspace/coverage/default/3.sysrst_ctrl_smoke.1240527393 Apr 15 01:01:10 PM PDT 24 Apr 15 01:01:16 PM PDT 24 2111359104 ps
T369 /workspace/coverage/default/46.sysrst_ctrl_combo_detect.1564339172 Apr 15 01:02:56 PM PDT 24 Apr 15 01:05:38 PM PDT 24 117261788115 ps
T179 /workspace/coverage/default/26.sysrst_ctrl_edge_detect.2609587517 Apr 15 01:02:09 PM PDT 24 Apr 15 01:02:18 PM PDT 24 5347174307 ps
T516 /workspace/coverage/default/4.sysrst_ctrl_in_out_inverted.2061741788 Apr 15 01:01:08 PM PDT 24 Apr 15 01:01:10 PM PDT 24 2535054543 ps
T517 /workspace/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.2981738066 Apr 15 01:01:44 PM PDT 24 Apr 15 01:01:52 PM PDT 24 2781987509 ps
T518 /workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.3193505404 Apr 15 01:03:01 PM PDT 24 Apr 15 01:03:02 PM PDT 24 3692892199 ps
T255 /workspace/coverage/default/45.sysrst_ctrl_edge_detect.2375174678 Apr 15 01:03:00 PM PDT 24 Apr 15 01:03:04 PM PDT 24 2753083903 ps
T267 /workspace/coverage/default/32.sysrst_ctrl_combo_detect.3050549017 Apr 15 01:02:26 PM PDT 24 Apr 15 01:04:07 PM PDT 24 111670314544 ps
T268 /workspace/coverage/default/41.sysrst_ctrl_auto_blk_key_output.3489117406 Apr 15 01:02:48 PM PDT 24 Apr 15 01:02:50 PM PDT 24 3609988507 ps
T269 /workspace/coverage/default/22.sysrst_ctrl_pin_access_test.3373061152 Apr 15 01:02:04 PM PDT 24 Apr 15 01:02:07 PM PDT 24 2046340344 ps
T270 /workspace/coverage/default/18.sysrst_ctrl_in_out_inverted.3032064631 Apr 15 01:01:50 PM PDT 24 Apr 15 01:01:58 PM PDT 24 2482056112 ps
T271 /workspace/coverage/default/37.sysrst_ctrl_auto_blk_key_output.2060117405 Apr 15 01:02:37 PM PDT 24 Apr 15 01:02:40 PM PDT 24 3363776450 ps
T265 /workspace/coverage/default/0.sysrst_ctrl_edge_detect.2519738929 Apr 15 01:01:04 PM PDT 24 Apr 15 01:01:06 PM PDT 24 3255273165 ps
T272 /workspace/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.108390428 Apr 15 01:03:08 PM PDT 24 Apr 15 01:07:15 PM PDT 24 85340098222 ps
T273 /workspace/coverage/default/20.sysrst_ctrl_combo_detect_with_pre_cond.3823770072 Apr 15 01:01:58 PM PDT 24 Apr 15 01:03:04 PM PDT 24 25580212486 ps
T274 /workspace/coverage/default/36.sysrst_ctrl_in_out_inverted.2305132238 Apr 15 01:02:32 PM PDT 24 Apr 15 01:02:35 PM PDT 24 2494862995 ps
T519 /workspace/coverage/default/2.sysrst_ctrl_ultra_low_pwr.2208065548 Apr 15 01:01:07 PM PDT 24 Apr 15 01:01:14 PM PDT 24 9841973163 ps
T520 /workspace/coverage/default/16.sysrst_ctrl_pin_override_test.2602669050 Apr 15 01:01:43 PM PDT 24 Apr 15 01:01:45 PM PDT 24 2546757187 ps
T521 /workspace/coverage/default/47.sysrst_ctrl_alert_test.3921184370 Apr 15 01:03:01 PM PDT 24 Apr 15 01:03:03 PM PDT 24 2090987650 ps
T522 /workspace/coverage/default/36.sysrst_ctrl_pin_access_test.46938642 Apr 15 01:02:40 PM PDT 24 Apr 15 01:02:44 PM PDT 24 2181955920 ps
T523 /workspace/coverage/default/14.sysrst_ctrl_ultra_low_pwr.2369512399 Apr 15 01:01:40 PM PDT 24 Apr 15 01:01:42 PM PDT 24 3131987686 ps
T524 /workspace/coverage/default/16.sysrst_ctrl_stress_all.1974581405 Apr 15 01:01:44 PM PDT 24 Apr 15 01:02:03 PM PDT 24 6721446132 ps
T384 /workspace/coverage/default/30.sysrst_ctrl_combo_detect_with_pre_cond.3788240661 Apr 15 01:02:24 PM PDT 24 Apr 15 01:07:20 PM PDT 24 217824200596 ps
T402 /workspace/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.3968465710 Apr 15 01:03:07 PM PDT 24 Apr 15 01:04:31 PM PDT 24 60418285802 ps
T525 /workspace/coverage/default/2.sysrst_ctrl_edge_detect.2478707173 Apr 15 01:01:06 PM PDT 24 Apr 15 01:01:09 PM PDT 24 3448563416 ps
T526 /workspace/coverage/default/8.sysrst_ctrl_pin_access_test.2985417356 Apr 15 01:01:21 PM PDT 24 Apr 15 01:01:23 PM PDT 24 2026033963 ps
T527 /workspace/coverage/default/32.sysrst_ctrl_ultra_low_pwr.657430500 Apr 15 01:02:25 PM PDT 24 Apr 15 01:02:28 PM PDT 24 4837158436 ps
T528 /workspace/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.4285474802 Apr 15 01:01:36 PM PDT 24 Apr 15 01:01:39 PM PDT 24 2631584547 ps
T191 /workspace/coverage/default/23.sysrst_ctrl_edge_detect.1736318946 Apr 15 01:02:05 PM PDT 24 Apr 15 01:02:09 PM PDT 24 5466713486 ps
T529 /workspace/coverage/default/17.sysrst_ctrl_ec_pwr_on_rst.3658762868 Apr 15 01:01:52 PM PDT 24 Apr 15 01:01:56 PM PDT 24 3740143105 ps
T530 /workspace/coverage/default/40.sysrst_ctrl_pin_override_test.932151708 Apr 15 01:02:49 PM PDT 24 Apr 15 01:02:51 PM PDT 24 2541005920 ps
T107 /workspace/coverage/default/49.sysrst_ctrl_stress_all.4152424173 Apr 15 01:03:08 PM PDT 24 Apr 15 01:06:53 PM PDT 24 87266602106 ps
T192 /workspace/coverage/default/32.sysrst_ctrl_stress_all.545281402 Apr 15 01:02:23 PM PDT 24 Apr 15 01:07:36 PM PDT 24 126834436376 ps
T93 /workspace/coverage/default/7.sysrst_ctrl_ultra_low_pwr.1436109008 Apr 15 01:01:24 PM PDT 24 Apr 15 01:01:39 PM PDT 24 618855968416 ps
T246 /workspace/coverage/default/39.sysrst_ctrl_auto_blk_key_output.2204373863 Apr 15 01:02:45 PM PDT 24 Apr 15 01:03:34 PM PDT 24 113346162763 ps
T247 /workspace/coverage/default/36.sysrst_ctrl_smoke.1034751448 Apr 15 01:02:33 PM PDT 24 Apr 15 01:02:39 PM PDT 24 2113947021 ps
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T251 /workspace/coverage/default/43.sysrst_ctrl_pin_access_test.3980749446 Apr 15 01:02:56 PM PDT 24 Apr 15 01:03:03 PM PDT 24 2223520557 ps
T252 /workspace/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.103328180 Apr 15 01:03:07 PM PDT 24 Apr 15 01:04:04 PM PDT 24 88451323613 ps
T253 /workspace/coverage/default/41.sysrst_ctrl_ultra_low_pwr.3758746948 Apr 15 01:02:50 PM PDT 24 Apr 15 01:02:53 PM PDT 24 10293087887 ps
T531 /workspace/coverage/default/30.sysrst_ctrl_ec_pwr_on_rst.1070899255 Apr 15 01:02:24 PM PDT 24 Apr 15 01:02:29 PM PDT 24 2971412697 ps
T532 /workspace/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.4218716142 Apr 15 01:02:48 PM PDT 24 Apr 15 01:02:56 PM PDT 24 2612783665 ps
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T534 /workspace/coverage/default/21.sysrst_ctrl_pin_access_test.602443208 Apr 15 01:02:07 PM PDT 24 Apr 15 01:02:11 PM PDT 24 2105097749 ps
T535 /workspace/coverage/default/33.sysrst_ctrl_pin_access_test.2424221154 Apr 15 01:02:27 PM PDT 24 Apr 15 01:02:32 PM PDT 24 2222732083 ps
T383 /workspace/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.2785833574 Apr 15 01:03:14 PM PDT 24 Apr 15 01:04:04 PM PDT 24 39102863183 ps
T334 /workspace/coverage/default/35.sysrst_ctrl_stress_all.528018378 Apr 15 01:02:38 PM PDT 24 Apr 15 01:04:05 PM PDT 24 568170855962 ps
T154 /workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.4288803444 Apr 15 01:03:01 PM PDT 24 Apr 15 01:03:08 PM PDT 24 7814216026 ps
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T536 /workspace/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.2855918095 Apr 15 01:02:10 PM PDT 24 Apr 15 01:02:14 PM PDT 24 2628977453 ps
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T537 /workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.30853767 Apr 15 01:03:04 PM PDT 24 Apr 15 01:03:16 PM PDT 24 3952484115 ps
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T539 /workspace/coverage/default/19.sysrst_ctrl_pin_access_test.1428756366 Apr 15 01:01:58 PM PDT 24 Apr 15 01:02:00 PM PDT 24 2251473421 ps
T540 /workspace/coverage/default/36.sysrst_ctrl_ec_pwr_on_rst.3837000575 Apr 15 01:02:40 PM PDT 24 Apr 15 01:02:50 PM PDT 24 3397303088 ps
T541 /workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.1840303664 Apr 15 01:02:49 PM PDT 24 Apr 15 01:02:54 PM PDT 24 2467861324 ps
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T543 /workspace/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.1078537507 Apr 15 01:01:45 PM PDT 24 Apr 15 01:02:29 PM PDT 24 95495852510 ps
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T166 /workspace/coverage/default/27.sysrst_ctrl_stress_all_with_rand_reset.1368715123 Apr 15 01:02:14 PM PDT 24 Apr 15 01:02:47 PM PDT 24 40150203810 ps
T544 /workspace/coverage/default/39.sysrst_ctrl_stress_all_with_rand_reset.2920874504 Apr 15 01:02:43 PM PDT 24 Apr 15 01:03:05 PM PDT 24 34500545924 ps
T545 /workspace/coverage/default/38.sysrst_ctrl_auto_blk_key_output.1967434016 Apr 15 01:02:46 PM PDT 24 Apr 15 01:29:16 PM PDT 24 608277279945 ps
T546 /workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.2470314382 Apr 15 01:02:58 PM PDT 24 Apr 15 01:03:01 PM PDT 24 2627923572 ps
T547 /workspace/coverage/default/39.sysrst_ctrl_ec_pwr_on_rst.3036662779 Apr 15 01:02:46 PM PDT 24 Apr 15 01:02:54 PM PDT 24 4572232797 ps
T138 /workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.478313107 Apr 15 01:03:08 PM PDT 24 Apr 15 01:03:17 PM PDT 24 6121100844 ps
T548 /workspace/coverage/default/31.sysrst_ctrl_flash_wr_prot_out.1287178677 Apr 15 01:02:24 PM PDT 24 Apr 15 01:02:28 PM PDT 24 2623305990 ps
T378 /workspace/coverage/default/12.sysrst_ctrl_combo_detect.868121555 Apr 15 01:01:35 PM PDT 24 Apr 15 01:06:57 PM PDT 24 118401922992 ps
T549 /workspace/coverage/default/23.sysrst_ctrl_pin_override_test.1482576964 Apr 15 01:02:03 PM PDT 24 Apr 15 01:02:08 PM PDT 24 2518268943 ps
T550 /workspace/coverage/default/33.sysrst_ctrl_pin_override_test.1210730919 Apr 15 01:02:26 PM PDT 24 Apr 15 01:02:34 PM PDT 24 2507741702 ps
T551 /workspace/coverage/default/11.sysrst_ctrl_smoke.3996505344 Apr 15 01:01:34 PM PDT 24 Apr 15 01:01:41 PM PDT 24 2110780878 ps
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T388 /workspace/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.2994486084 Apr 15 01:03:13 PM PDT 24 Apr 15 01:06:45 PM PDT 24 87049308800 ps
T554 /workspace/coverage/default/31.sysrst_ctrl_pin_override_test.3755985533 Apr 15 01:02:21 PM PDT 24 Apr 15 01:02:28 PM PDT 24 2514867056 ps
T555 /workspace/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.3436352120 Apr 15 01:02:31 PM PDT 24 Apr 15 01:04:23 PM PDT 24 167546835855 ps
T556 /workspace/coverage/default/38.sysrst_ctrl_ec_pwr_on_rst.767784933 Apr 15 01:02:47 PM PDT 24 Apr 15 01:02:50 PM PDT 24 3404095661 ps
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T558 /workspace/coverage/default/24.sysrst_ctrl_flash_wr_prot_out.1941039485 Apr 15 01:02:04 PM PDT 24 Apr 15 01:02:13 PM PDT 24 2611825864 ps
T559 /workspace/coverage/default/15.sysrst_ctrl_smoke.3012853085 Apr 15 01:01:42 PM PDT 24 Apr 15 01:01:44 PM PDT 24 2131267206 ps
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T376 /workspace/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.2601578055 Apr 15 01:02:48 PM PDT 24 Apr 15 01:07:36 PM PDT 24 103409527587 ps
T561 /workspace/coverage/default/13.sysrst_ctrl_combo_detect_with_pre_cond.621565905 Apr 15 01:01:40 PM PDT 24 Apr 15 01:05:05 PM PDT 24 76012769253 ps
T562 /workspace/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.3691166201 Apr 15 01:01:52 PM PDT 24 Apr 15 01:02:48 PM PDT 24 83115779144 ps
T563 /workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.3288796732 Apr 15 01:02:51 PM PDT 24 Apr 15 01:02:58 PM PDT 24 4656055072 ps
T564 /workspace/coverage/default/23.sysrst_ctrl_pin_access_test.2127711969 Apr 15 01:02:07 PM PDT 24 Apr 15 01:02:10 PM PDT 24 2134159112 ps
T397 /workspace/coverage/default/11.sysrst_ctrl_combo_detect.1533521101 Apr 15 01:01:36 PM PDT 24 Apr 15 01:02:05 PM PDT 24 69875472432 ps
T565 /workspace/coverage/default/2.sysrst_ctrl_pin_override_test.3427406341 Apr 15 01:01:07 PM PDT 24 Apr 15 01:01:10 PM PDT 24 2529298939 ps
T566 /workspace/coverage/default/17.sysrst_ctrl_smoke.859392751 Apr 15 01:01:46 PM PDT 24 Apr 15 01:01:51 PM PDT 24 2114725213 ps
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T569 /workspace/coverage/default/34.sysrst_ctrl_ultra_low_pwr.3787965058 Apr 15 01:02:32 PM PDT 24 Apr 15 01:02:34 PM PDT 24 9620188785 ps
T377 /workspace/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.2353927044 Apr 15 01:03:18 PM PDT 24 Apr 15 01:07:02 PM PDT 24 82513671782 ps
T570 /workspace/coverage/default/10.sysrst_ctrl_auto_blk_key_output.2661116252 Apr 15 01:01:31 PM PDT 24 Apr 15 01:13:01 PM PDT 24 273789033778 ps
T373 /workspace/coverage/default/16.sysrst_ctrl_combo_detect.2677754200 Apr 15 01:01:44 PM PDT 24 Apr 15 01:04:43 PM PDT 24 100604509992 ps
T399 /workspace/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.3318842868 Apr 15 01:02:53 PM PDT 24 Apr 15 01:03:12 PM PDT 24 27351168931 ps
T571 /workspace/coverage/default/10.sysrst_ctrl_pin_access_test.721454674 Apr 15 01:01:31 PM PDT 24 Apr 15 01:01:34 PM PDT 24 2148219390 ps
T572 /workspace/coverage/default/24.sysrst_ctrl_in_out_inverted.2481572880 Apr 15 01:02:12 PM PDT 24 Apr 15 01:02:20 PM PDT 24 2460493565 ps
T226 /workspace/coverage/default/3.sysrst_ctrl_edge_detect.3731575971 Apr 15 01:01:22 PM PDT 24 Apr 15 01:01:25 PM PDT 24 5846163881 ps
T573 /workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.3148048039 Apr 15 01:02:51 PM PDT 24 Apr 15 01:03:05 PM PDT 24 4465393421 ps
T574 /workspace/coverage/default/49.sysrst_ctrl_combo_detect.1533092108 Apr 15 01:03:09 PM PDT 24 Apr 15 01:06:25 PM PDT 24 157855815203 ps
T575 /workspace/coverage/default/3.sysrst_ctrl_in_out_inverted.2010716760 Apr 15 01:01:11 PM PDT 24 Apr 15 01:01:18 PM PDT 24 2489649952 ps
T576 /workspace/coverage/default/1.sysrst_ctrl_ec_pwr_on_rst.3930928096 Apr 15 01:01:07 PM PDT 24 Apr 15 01:01:13 PM PDT 24 3554688382 ps
T231 /workspace/coverage/default/35.sysrst_ctrl_edge_detect.2625291924 Apr 15 01:02:31 PM PDT 24 Apr 15 01:02:34 PM PDT 24 3330114191 ps
T577 /workspace/coverage/default/6.sysrst_ctrl_stress_all.3250900699 Apr 15 01:01:21 PM PDT 24 Apr 15 01:01:24 PM PDT 24 6923837469 ps
T370 /workspace/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.2742588622 Apr 15 01:03:11 PM PDT 24 Apr 15 01:05:03 PM PDT 24 39800390302 ps
T578 /workspace/coverage/default/27.sysrst_ctrl_stress_all.1688889250 Apr 15 01:02:13 PM PDT 24 Apr 15 01:02:17 PM PDT 24 16139654593 ps
T579 /workspace/coverage/default/39.sysrst_ctrl_pin_override_test.1381221995 Apr 15 01:02:48 PM PDT 24 Apr 15 01:02:52 PM PDT 24 2523779278 ps
T580 /workspace/coverage/default/7.sysrst_ctrl_pin_override_test.585511033 Apr 15 01:01:24 PM PDT 24 Apr 15 01:01:30 PM PDT 24 2516641626 ps
T581 /workspace/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.3499100456 Apr 15 01:02:48 PM PDT 24 Apr 15 01:02:58 PM PDT 24 2923329361 ps
T582 /workspace/coverage/default/20.sysrst_ctrl_edge_detect.1311793856 Apr 15 01:01:59 PM PDT 24 Apr 15 01:02:04 PM PDT 24 5313579627 ps
T583 /workspace/coverage/default/33.sysrst_ctrl_in_out_inverted.4012031220 Apr 15 01:02:29 PM PDT 24 Apr 15 01:02:33 PM PDT 24 2458782226 ps
T584 /workspace/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.4148200044 Apr 15 01:02:50 PM PDT 24 Apr 15 01:02:55 PM PDT 24 2804357190 ps
T585 /workspace/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.3059012823 Apr 15 01:02:04 PM PDT 24 Apr 15 01:02:08 PM PDT 24 2742396671 ps
T586 /workspace/coverage/default/28.sysrst_ctrl_pin_access_test.333492442 Apr 15 01:02:16 PM PDT 24 Apr 15 01:02:18 PM PDT 24 2129534637 ps
T587 /workspace/coverage/default/27.sysrst_ctrl_ultra_low_pwr.1230584369 Apr 15 01:02:09 PM PDT 24 Apr 15 01:02:13 PM PDT 24 11067982995 ps
T588 /workspace/coverage/default/33.sysrst_ctrl_smoke.1503967843 Apr 15 01:02:34 PM PDT 24 Apr 15 01:02:41 PM PDT 24 2110462558 ps
T589 /workspace/coverage/default/15.sysrst_ctrl_alert_test.2632118649 Apr 15 01:01:49 PM PDT 24 Apr 15 01:01:51 PM PDT 24 2045132359 ps
T590 /workspace/coverage/default/2.sysrst_ctrl_alert_test.1855844133 Apr 15 01:01:21 PM PDT 24 Apr 15 01:01:23 PM PDT 24 2041037696 ps
T591 /workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.2013223205 Apr 15 01:02:59 PM PDT 24 Apr 15 01:03:05 PM PDT 24 3657558811 ps
T592 /workspace/coverage/default/13.sysrst_ctrl_in_out_inverted.1097529890 Apr 15 01:01:36 PM PDT 24 Apr 15 01:01:37 PM PDT 24 2563141637 ps
T593 /workspace/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.2501638172 Apr 15 01:02:02 PM PDT 24 Apr 15 01:02:12 PM PDT 24 3755894085 ps
T594 /workspace/coverage/default/48.sysrst_ctrl_pin_access_test.1924856196 Apr 15 01:03:02 PM PDT 24 Apr 15 01:03:08 PM PDT 24 2225383030 ps
T595 /workspace/coverage/default/3.sysrst_ctrl_ec_pwr_on_rst.1464626570 Apr 15 01:01:11 PM PDT 24 Apr 15 01:01:20 PM PDT 24 3170510059 ps
T387 /workspace/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.5115043 Apr 15 01:01:18 PM PDT 24 Apr 15 01:03:52 PM PDT 24 202592031675 ps
T596 /workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.591712218 Apr 15 01:01:17 PM PDT 24 Apr 15 01:01:20 PM PDT 24 2474963640 ps
T597 /workspace/coverage/default/2.sysrst_ctrl_flash_wr_prot_out.2254870731 Apr 15 01:01:13 PM PDT 24 Apr 15 01:01:17 PM PDT 24 2621930727 ps
T232 /workspace/coverage/default/20.sysrst_ctrl_stress_all.3185828628 Apr 15 01:02:00 PM PDT 24 Apr 15 01:07:14 PM PDT 24 225877950469 ps
T598 /workspace/coverage/default/38.sysrst_ctrl_combo_detect_with_pre_cond.3899662577 Apr 15 01:02:46 PM PDT 24 Apr 15 01:03:54 PM PDT 24 28332024382 ps
T599 /workspace/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.688633923 Apr 15 01:01:22 PM PDT 24 Apr 15 01:04:56 PM PDT 24 78126054354 ps
T139 /workspace/coverage/default/20.sysrst_ctrl_stress_all_with_rand_reset.22036566 Apr 15 01:02:12 PM PDT 24 Apr 15 01:04:12 PM PDT 24 116021880414 ps
T600 /workspace/coverage/default/21.sysrst_ctrl_smoke.355937048 Apr 15 01:01:58 PM PDT 24 Apr 15 01:02:04 PM PDT 24 2108876815 ps
T108 /workspace/coverage/default/11.sysrst_ctrl_auto_blk_key_output.186569071 Apr 15 01:01:32 PM PDT 24 Apr 15 01:01:35 PM PDT 24 2993529486 ps
T601 /workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.1203673051 Apr 15 01:01:17 PM PDT 24 Apr 15 01:01:21 PM PDT 24 3664280288 ps
T209 /workspace/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.5877758 Apr 15 01:03:01 PM PDT 24 Apr 15 01:04:03 PM PDT 24 24038186129 ps
T602 /workspace/coverage/default/20.sysrst_ctrl_in_out_inverted.4021578403 Apr 15 01:02:00 PM PDT 24 Apr 15 01:02:02 PM PDT 24 2564064936 ps
T603 /workspace/coverage/default/10.sysrst_ctrl_in_out_inverted.3843050469 Apr 15 01:01:31 PM PDT 24 Apr 15 01:01:40 PM PDT 24 2463173064 ps
T604 /workspace/coverage/default/25.sysrst_ctrl_pin_access_test.245956683 Apr 15 01:02:09 PM PDT 24 Apr 15 01:02:12 PM PDT 24 2066157736 ps
T605 /workspace/coverage/default/0.sysrst_ctrl_flash_wr_prot_out.871529642 Apr 15 01:01:04 PM PDT 24 Apr 15 01:01:07 PM PDT 24 2625698824 ps
T606 /workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.971818639 Apr 15 01:01:23 PM PDT 24 Apr 15 01:01:26 PM PDT 24 2641053935 ps
T607 /workspace/coverage/default/1.sysrst_ctrl_auto_blk_key_output.1720329068 Apr 15 01:01:13 PM PDT 24 Apr 15 01:01:18 PM PDT 24 3370280096 ps
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